As CT charges and discharges, an internal blanking pulse is generated that alternately drives the inputs of the upper and lower NOR gates high. This, in conjunction with a precise amount of delay time introduced into each chan- nel, produces well defined non-overlapping output duty cycles. Output 2 is enabled while CT is charging, and Output 1 is enabled during the discharge. Even at 500kHz, each output is capable of approximately 44% duty cycle,
M37263-502SP
Vendor: Package Cooled: D/C:
M37263-502SP In-stock Suppliers , Datasheet PDF download
About M37100M8
PDF/DataSheet Download
DathSheet: M37100M8
File Size: 1714556 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
Description
Applications
8. The minimum Full Scale Calibration Range (FSCR) is limited by the maximum allowed gain register value (with margin). The maximum FSCR is limited by the ∆Ó modulators 1s density range. See Analog Input section for details. Also see Limitations in Calibration Range.
Features
s A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. s Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. s Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application. s In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application. s Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values. s Low voltage reset (brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt. s Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 µA (total power-down with voltage comparators disabled). s Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available. s Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. s Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. s Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. s Port input pattern match detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. s LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip. s Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. s Only power and ground connections are required to operate the M37263-502SP/934/935/936 when internal reset option is selected. s Four interrupt priority levels. s Eight keypad interrupt inputs, plus two additional external interrupt inputs. s Schmitt trigger port inputs. s Second data pointer. s Emulation support.
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