Index "0"03-06-SNK034-1
Vendor:ABLECOM
0306YD104MAT2A
Vendor:AVXPackage Cooled:0306-104MD/C:04+
0306ZC103KAT4A
Vendor:ＡＶＸ ＣＯＲＰ
0306ZC104KAT2A
• Wide frequency rangeC250.0MHz to 500.0MHz • User specified tolerance available • Case at electrical ground • Will withstand vapor phase temperatures of 253C for 4 minutes maximum • All metal, resistance weld, hermetically sealed package • High shock resistance, to 1500g
0306ZC104KAT2A
• Wide frequency rangeC250.0MHz to 500.0MHz • User specified tolerance available • Case at electrical ground • Will withstand vapor phase temperatures of 253C for 4 minutes maximum • All metal, resistance weld, hermetically sealed package • High shock resistance, to 1500g
0306ZC104KAT4A
Vendor:ＡＶＸ ＣＯＲＰ
0306ZC224KAT2A
Vendor:N/APackage Cooled:N/AD/C:08+09+
0306ZC224MAT2A
Vendor:AVXD/C:2007+
ALABAMA, Huntsville ARIZONA, Tempe CALIFORNIA, Agoura Hills CALIFORNIA, Los Angeles CALIFORNIA, Irvine CALIFORNIA, Rosevllle CALIFORNIA, San Diego CALIFORNIA, Sunnyvale COLORADO, Colorado Springs COLORADO, Denver CONNECTICUT, Wallingford FLORIDA, Maitland FLORIDA, Pompano Beach/ Fort Lauderdal FLORIDA, Clearwater GEORGlA, Atlanta IDAHO, Boise ILLINOIS, Chicago/Hoffman Estates INDlANA, Fort Wayne ...
03-0709
03072508C
03-08-2092
030-9036-000
0309100001
Vendor:avanexPackage Cooled:dc0505D/C:4
03-09-1011
Vendor:MOLEXD/C:07+
The 03-09-1011 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The 03-09-1011 operates as a Slave device. Both th...
03-09-1022
Vendor:MOLEXD/C:07+
The Flash devices contain two separate banks of memory (bank a and bank b) for simultaneous READ and WRITE operations and are available in the following bank segmentation configuration: • Bank a is one-fourth of the memory containing 8 x 4K-word parameter blocks, while the remainder of bank a is split into 15 x 32K-word blocks. • Bank b represents three-fourths of the memory, is equall...
03-09-1030
03-09-1031
Vendor:MOLEX
Minimum time between read command (i.e., a write to communication register) and data read. Minimum time between data byte transfers during a multibyte read. Data access time after SCLK rising edge following a write to the communication register. Bus relinquish time after falling edge of SCLK.
03-09-1032
Vendor:MOLEXD/C:07+
Very High FEC performance : Hamming and "BCH-t=2" codes Bitrate customisable : 7 to 25 Mbits/s typical @ 5 iterations Large block sizes : up to 65 kbits On-the-fly change of the code Shortening facilities to adjust packet size and coding rate Single-chip PLD IP Core : Altera APEX, no external memory required Latency reduction by bank-swapping Two selectable configuration interface
03-09-1040
Vendor:MOLEXD/C:07+
1. Dimensions are in inches. 2. Metric equivalents are given for general information only. 3. See FED-STD-H28, Screw-Thread Standards for Federal Services. 4. The orientation of the terminals in relation to the hex flats is not controlled. 5. All three terminals. 6. The case temperature may be measured anywhere on the seating plane within .125 (3.18 mm) of the stud. 7. Terminal spacing measured at the base s...
03-09-1041
Vendor:MOLEXD/C:07+
Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider.
03-09-1042
Vendor:MOLEXD/C:07+
AMDs unique I/O macrocell offers major benefits through its versatile, programmable input/output cell structure, multiple clock choices, flexible Output Enable and feedback selection. Eight I/O macrocells with single feedback contain 9 EE cells, while the other eight ma- crocells contain 8 EE cells for programming the input/ output functions (see Table 1).
03-09-1049
Vendor:MOLEXD/C:07+
Can use external RAM as additional FIFO (addressed through A/D buses) • Special Autovectors for DMA and FIFO interrupts • 400-kHz or 100-kHz I2C operation • General Programmable Interface (GPIF) Allows direct connection to most parallel interfaces: 8- and 16-bit
03-09-1049
Vendor:MOLEXD/C:07+
Can use external RAM as additional FIFO (addressed through A/D buses) • Special Autovectors for DMA and FIFO interrupts • 400-kHz or 100-kHz I2C operation • General Programmable Interface (GPIF) Allows direct connection to most parallel interfaces: 8- and 16-bit
03-09-1052
Parameter Carrier Frequency Operating Voltage (VDD_MEM) Operating Voltage (VDD_PIO) RF Output Power RX Sensitivity Load Impedance Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Average Current Consumption
03-09-1061
Vendor:MOLEXD/C:07+
Master/Slave Synchronization. When it is open, a signal synchronous with the turn-off of the inter- nal power is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal. Connecting together the SYNC pin of two devices, the one with the higher frequency works as master and the other one, works as slave.
03-09-1061
Vendor:MOLEXD/C:07+
Master/Slave Synchronization. When it is open, a signal synchronous with the turn-off of the inter- nal power is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal. Connecting together the SYNC pin of two devices, the one with the higher frequency works as master and the other one, works as slave.
03-09-1063
Vendor:MolexD/C:08+
The Spartan series is the result of more than 14 years of FPGA design experience and feedback from thousands of customers. By streamlining the Spartan series feature set, leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles ...
03-09-1091
Vendor:MOLEXD/C:07+
The following describes a procedure for evaluating the RMBA19500A, a monolithic high efficiency power amplifier, in a surface mount package, designed for use as a driver stage for PCS1900 Base station or as the final output stage for Micro- and Pico-Cell base stations. Figure 1 shows the package outline and the pin designations. Figure 2 shows the functional block diagram of the packaged product. The RMBA...
03-09-1093
Vendor:MolexD/C:08+
Excellent temperature stability 20 ppm/C Linear frequency sweep Adjustable duty cycle 0.1% to 99.9% Two or four level FSK capability Wide sweep range 1000:1 min. Logic compatible input and output levels Wide supply voltage range 4V to 13V Low supply sensitivity 0.15%/V Wide frequency range 0.01 Hz to 1 MHz Simultaneous triangle and squarewave outputs
03-09-1094
Vendor:MOLEXD/C:07+
NOTES: 1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V LVTTL signals as well. 2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage. 3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. Thes...
03-09-1094
Vendor:MOLEXD/C:07+
NOTES: 1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V LVTTL signals as well. 2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage. 3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. Thes...
03-09-1125
Vendor:MOLEXD/C:07+
MPX12 series pressure sensors are available in differential and gauge configurations. Devices are available in the basic element package or with pressure port fittings which provide printed circuit board mounting ease and barbed hose pressure connections.
03-09-1126
Vendor:MOLEXD/C:07+
✔ Designed for 4-20mA Current Loops ✔ Automatic Reset - Will Not Interrupt Service ✔ Permanent Two-Stage Line Pair Protection ✔ Line-to-Ground (Common) & Line-to-Line (Differential) Protection ✔ Subnanosecond Response Time ✔ Effective Against Lightning, Inductive Switching & ESD
03-09-1126
Vendor:MOLEXD/C:07+
✔ Designed for 4-20mA Current Loops ✔ Automatic Reset - Will Not Interrupt Service ✔ Permanent Two-Stage Line Pair Protection ✔ Line-to-Ground (Common) & Line-to-Line (Differential) Protection ✔ Subnanosecond Response Time ✔ Effective Against Lightning, Inductive Switching & ESD
03-09-1151
Vendor:MOLEXD/C:07+
When MULTIPLEX is low, this is DB0. When MULTIPLEX is high this is the ABb signal, which is used to synchronize the multiplexed data. ABb changes synchronously with the Multiplexed "A" and "B" channels. ABb is "high" when "A" channel data is valid and is "low" when "B" channel data is valid.
03-09-1157
Vendor:MOLEX
The ADuC842 also incorporates additional analog functionality with two 12-bit DACs, power supply monitor, and a bandgap reference. On-chip digital peripherals include two 16-bit Ó∆ DACs, dual output 16-bit PWM, watchdog timer, time interval counter, three timers/counters, and three serial I/O ports (SPI, I2C and UART).
030-9173-006
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
03-09-2011
Vendor:MOLEXD/C:07+
CIS signal is level shifted to VRB in order to use the full range of the ADC. In the CIS configuration the input can also be AC coupled similar to the CCD configuration. This enables CIS signals with large black levels to be internally clamped to a DC reference equal to the black level. The DC reference is internally subtracted from the input signal.
03-09-2011
Vendor:MOLEXD/C:07+
CIS signal is level shifted to VRB in order to use the full range of the ADC. In the CIS configuration the input can also be AC coupled similar to the CCD configuration. This enables CIS signals with large black levels to be internally clamped to a DC reference equal to the black level. The DC reference is internally subtracted from the input signal.
03-09-2021
Vendor:MOLEXD/C:07+
!Features 1) Four channels of power MOS-H bridges are contained. 2) Available for PWM input. 3) Applicable for stepping-motor drive. 4) Separating VM into CH1, CH2 and CH3 / 4. 5) Low on-resistance 1.3Ω (typ.) 6) Low power consumption. 7) SSOP-B24 package.
03-09-2021
Vendor:MOLEXD/C:07+
!Features 1) Four channels of power MOS-H bridges are contained. 2) Available for PWM input. 3) Applicable for stepping-motor drive. 4) Separating VM into CH1, CH2 and CH3 / 4. 5) Low on-resistance 1.3Ω (typ.) 6) Low power consumption. 7) SSOP-B24 package.
03-09-2022
Vendor:MOLEXD/C:07+
Always use controlled impedance lines (microstrip, coplanar waveguide, etc.) for high-frequency signals. Always place decoupling capacitors as close to the VCC pins as possible; for long VCC lines, it may be nec- essary to add additional decoupling capacitors located further from the device. Always provide a low-induc- tance path to ground, and keep GND vias as close to the device as possible. Thermal relief...
03-09-2031
Vendor:MOLEXD/C:07+
The TLV320AIC32 contains four high-power output drivers as well as two fully differential output drivers. The high-power output drivers are capable of driving a variety of load configurations, including up to four channels of single-ended 16-Ω headphones using ac-coupling capacitors, or stereo 16-Ω headphones in a cap-less output configuration. In addition, pairs of drivers can be used to...
03-09-2031
Vendor:MOLEXD/C:07+
The TLV320AIC32 contains four high-power output drivers as well as two fully differential output drivers. The high-power output drivers are capable of driving a variety of load configurations, including up to four channels of single-ended 16-Ω headphones using ac-coupling capacitors, or stereo 16-Ω headphones in a cap-less output configuration. In addition, pairs of drivers can be used to...
03-09-2032
Vendor:MOLEXD/C:07+
The OPA743 series utilizes a state-of-the-art 12V analog CMOS process and offers outstanding AC performance, such as 7MHz GBW, 10V/µs slew rate and 0.0008% THD+N. Optimized for single supply operation up to 12V, the input common-mode range extends beyond the power supply rails and the output swings to within 100mV of the rails. The low quiescent current of 1.1mA makes it well suited for use in b...
03-09-2032
Vendor:MOLEXD/C:07+
The OPA743 series utilizes a state-of-the-art 12V analog CMOS process and offers outstanding AC performance, such as 7MHz GBW, 10V/µs slew rate and 0.0008% THD+N. Optimized for single supply operation up to 12V, the input common-mode range extends beyond the power supply rails and the output swings to within 100mV of the rails. The low quiescent current of 1.1mA makes it well suited for use in b...
03-09-2041
Vendor:MOLEXD/C:07+
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur- nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reli...
03-09-2042
Vendor:MOLEXD/C:07+
Note 2: Guaranteed by design. Note 3: Under these conditions: a) no spurious oscillations shall be observed at collector greater than -60dBc; b) no parametric degradation is observable when mismatch is removed; and c) no current draw in excess of the package dissipation capability is observed.
03-09-2042
Vendor:MOLEXD/C:07+
Note 2: Guaranteed by design. Note 3: Under these conditions: a) no spurious oscillations shall be observed at collector greater than -60dBc; b) no parametric degradation is observable when mismatch is removed; and c) no current draw in excess of the package dissipation capability is observed.
03-09-2062
Vendor:MOLEXD/C:07+
Note 2: Limits are 100% production tested at TA = +25C. Limits over operating temperature are guaranteed by design. Note 3: Guaranteed, but not 100% tested. Note 4: The SMBus logic block is a static design that works with clock frequencies down to DC. While slow operation is possible, it violates the 10kHz minimum clock frequency and SMBus specifications and may monopolize the bus.
03-09-2091
Vendor:MOLEXD/C:07+
The THELMA process is utilized to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and free to move on a plane parallel to the substrate itself. To be compatible with the traditional packaging tech- niques a cap is placed on top of the sensing element to avoid blocking the movin...
03-09-2092
Vendor:MOLEXD/C:07+
Multi-Input Wake Up (on the 8-bit Port L) Brown out detector Analog comparator Modulator timer (High speed PWM for IR transmission) 16-bit multi-function timer supporting PWM mode External event counter mode Input capture mode 1024 bytes of ROM 64 bytes of RAM
03-09-2121
Vendor:MOLEXD/C:07+
03-09-2121
Vendor:MOLEXD/C:07+
03-09-2151
Vendor:MolexD/C:08+
Note 1: Die parameters are production tested at room temperature only, but are guaranteed by design and characterization from -40C to +85C. Note 2: Source capacitance represents the total capacitance at the IN pad during characterization of the noise and bandwidth para- meters. Note 3: Guaranteed by design and characterization. Note 4: Input-referred noise is:
03-09-2158
Vendor:MOLEX
Vth can be expressed as voltage between gate and source when low operating current value is ID = 100 mA for this product. For normal switching operation, VGS (on) requires higher voltage than Vth and VGS (off) requires lower voltage than Vth. (relationship can be established as follows: VGS (off) < Vth < VGS (on) ) Please take this into consideration for using the device. VGS recommended voltage ...
03-09-2161
Vendor:MOLEX
030E55001
030K57191N
030SA9H030AFUSE
031-0061-0001
0310-193
Vendor:MITSUMIPackage Cooled:02+D/C:QFP-80
‡ Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage ...
0310-193C3
Vendor:InfineonD/C:02-03+
The PCA0310-193C3 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine.
0310-193C3
Vendor:InfineonD/C:02-03+
The PCA0310-193C3 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine.
03-1060
03108631ZB
031-100K
031-1113-007
03-1200
0312001.MXP
Vendor:LITTLEFUSED/C:12000
0312015H
Vendor:littelfusePackage Cooled:dc04D/C:700
The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction.
0312164PT3A
Vendor:IBMPackage Cooled:TSOP
Designed for Class A or Class AB base station applications with frequencies up to 1500 MHz. Suitable for analog and digital modulation and multicarrier amplifier applications. • Typical Two - Tone Performance @ 960 MHz, VDD = 28 Volts, IDQ = 125 mA, Pout = 10 Watts PEP Power Gain 18 dB Drain Efficiency 32% IMD - 37 dBc • Capable of Handling 10:1 VSWR, @ 28 Vdc, 960 MHz, 10 Watts CW ...
03-12-2022
Vendor:MOLEX
Undervoltage Lockout UVLO (undervoltage lockout) prevents the output MOSFET from turning on until IN (input voltage) ex- ceeds 2.5V typical. After the switch turns on, if the voltage drops below 2.3V typical, UVLO shuts off the output MOSFET and signals the fault flag. Undervolt- age detection functions only when at least one switch is enabled.
03-12-2036
Vendor:MolexPackage Cooled:connectorD/C:06+
0313M16
Package Cooled:TSOP24MD/C:2007+
0314002H
Vendor:littelfusePackage Cooled:dc03D/C:400
INT is an open-drain output. This allows alarm INT to be valid in battery-backup mode. To use this feature, INT must be con- nected to a power supply other than VCC. INT is asserted low when any event flag is set and the corresponding event enable bit is also set. INT becomes high-impedance whenever register C is read (see the Con- trol/Status Registers section).
0314012H
Vendor:little fusePackage Cooled:dc03D/C:1650
0314015.MXP
Vendor:LITTELFUSED/C:06+
It must also be noted that in (noninverting) gain configurations (with low values of gain resistor), a high level of input overdrive can result in a large input error current, which may result in a significant power dissipation in the input stage. This power must be included when computing the junction temperature rise due to total internal power.
0314015.MXP
Vendor:LITTELFUSED/C:06+
It must also be noted that in (noninverting) gain configurations (with low values of gain resistor), a high level of input overdrive can result in a large input error current, which may result in a significant power dissipation in the input stage. This power must be included when computing the junction temperature rise due to total internal power.
0314020H
Vendor:little fusePackage Cooled:dc03D/C:3700
The B9948 is a low-voltage clock distribution buffer with the capability to select either a differential LVPECL or a LVC- MOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The twelve outputs are 3.3V LVCMOS or LVTTL compatible and can drive two series terminated 50...
0314020M
Vendor:little fusePackage Cooled:dc00D/C:2000
0314025.M52LP
Vendor:LITTLEFUSED/C:49517
0314030.MXP
Vendor:LITTELFUSEPackage Cooled:N/AD/C:10
In addition to high integration, the CS8920A offers a broad range of performance features and config- urationoptions.ItsuniquePacketPage architecture automatically adapts to changing net- work traffic patterns and available system resources. The result is increased system efficien- cy and minimized CPU overhead.
03144-2031-02
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up.
0314E8010
Package Cooled:QFP
03151-0041-01
CMOS imager sensor CMOS imager sensor 2:1 Interlace2:1 Interlace 1/60 to 1/15,000 sec 1/60 to 1/15,000 sec Compos. video (75Ω) Compos. video (75Ω) 628 x 582 pixel510 x 492 pixel 5.78 x 4.19mm4.69 x 3.54mm 340 TV Lines340 TV Lines >42dB (AGC on )>42dB (AGC on ) 3Lux at f1.2 (3000K) 3Lux at f1.2 (3000K) 8 C 15 VDC8 C 15 VDC PWR, Video, GNDPWR, Video, GND f6.0mm F1.6, FOV 5...
03151-0042-02
This particular HEXFET® MOSFET is in the SuperD2PakTM and has the same outline and pinout as the standard D 2Pak but has increased current handling capability and >1mm lower profile. This makes it ideal to reduce component count in multiparallel D2Pak operation, reduce system power dissipation or upgrade existing design. This package has also been designed to meet automotive qualification stan...
0315M02
Vendor:OKIPackage Cooled:QFPD/C:07/08+
The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.
0316169CT3D
Package Cooled:TSOP50
Change in Magnitude of Driver Differential Output Voltage for Complementary Output States Driver Common-Mode Output Voltage Change in Magnitude of Driver Common-Mode Output Voltage for Complementary Output States Input High Voltage
0316169CT3D
Package Cooled:TSOP50
Change in Magnitude of Driver Differential Output Voltage for Complementary Output States Driver Common-Mode Output Voltage Change in Magnitude of Driver Common-Mode Output Voltage for Complementary Output States Input High Voltage
0316169CT3D80
Vendor:IBMPackage Cooled:07+D/C:753
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits the minimum time the clock is high or low must be at least 250 ns. The maximum time the clock can be high or low is 60 µs.
0316169CT3D80
Vendor:IBMPackage Cooled:07+D/C:753
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits the minimum time the clock is high or low must be at least 250 ns. The maximum time the clock can be high or low is 60 µs.
0316809C73C
Package Cooled:PQFP
0317HV518PJ
031-8526-0000
031-9095-038
031SZR
Package Cooled:BGAD/C:N/A
032-001
0322030.MXP
Vendor:LITTELFUSEPackage Cooled:06+D/C:699
Direction of Rotation: When the codewheel rotates counter- clockwise, as viewed looking down on the module (so the marking is visible), channel A will lead channel B. If the codewheel rotates in the opposite direction, channel B will lead channel A.