0.22UF/50V/Z/P5

Package Cooled:MEC

0.22UF/63V/20/P5

Package Cooled:MEC

0.26-0.9-7T-T

0.274301945

0.31-0.9-4TS-P-B

0.33100VDC22205

D/C:1860

0.33UF 250VAC PILLOW

Package Cooled:MEC

0.33UF 50V Y5V -2080 0805 CAP LF

0.33UF/16V/10/0805/T

Package Cooled:TAIYO YUDE

0.33UF/16V/Z/0603/T

Package Cooled:YAGEO

0.33UF/50V/10/P5

Package Cooled:MEC

0.33UF/50V/20/0805/T

Package Cooled:MEC

0.33UF/63V/20/P5/L

Package Cooled:MEC

0.33UF63VDC22205

D/C:5350

0.36 INCH SINGLE DIGIT DISPLAY A-3

0.39 RES5 2W

Package Cooled:TAIWAN

0.47UF/10V/10/0603/T

Package Cooled:YAGEO

0.47UF/25V/Z/0805/T

Package Cooled:YAGEO

0.47UF/50V/10/2225/B

Package Cooled:MEC

0.47UF/50V/Z/0603/T

Package Cooled:YAGEO

0.47UF250V

HIGH SPEED: tPD = 3.5ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA = 25C HIGH NOISE IMMUNITY: VNIH = VNIL = 10% VCC (MIN.) POWER DOWN PROTECTION ON INPUT SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) at VCC = 4.5V BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V IMPROVED LATCH-UP IMMUNITY

0.47UF25V

Vendor:AVX

0.4BCOA

Package Cooled:SMD-8

0.56UF/63V/20/P5

Package Cooled:MEC

0.5MM LOWER CONTACT

0.5MM UPPER LOCK

0.5PF/50V/0.25PF/0402/T

Package Cooled:PHYCOMP

0.5W110V

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

0.5W11V

VI TELEFILTERVectron International, Inc. Potsdamer Straße 18267 Lowell Road D 14 513 TELTOW / GermanyHudson, NH 03051 / USA Tel: (+49) 3328 4784-0 / Fax: (+49) 3328 4784-30Tel: (603) 598-0070 Fax: (603) 598-0075 E-Mail: tft@telefilter.comE-Mail: vti@vtinh.com VI TELEFILTER reserves the right to make changes to the product(s) and/or information contained herein without notice. No liability is assum...

0.5W12V

Vendor:COSPackage Cooled:DO-35D/C:07+

Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The contr...

0.5W15V

Vendor:COSPackage Cooled:DO-35D/C:07+

2.5 VDD 6 differential outputs Low skew: 100ps all outputs Selectable positive or negative edge synchronization Tolerant of spread spectrum input clock Synchronous output enable Selectable inputs Input frequency: 4.17MHz to 250MHz Output frequency: 12.5MHz to 250MHz 1.8V / 2.5V LVTTL: up to 250MHz HSTL / eHSTL: up to 250MHz Hot insertable and over-voltage tolerant inputs 3-level inputs for selecta...

0.5W18V

Vendor:COSPackage Cooled:DO-35D/C:07+

A 5% resistor value is recommended. In the OOK mode, this pin is usually driven with a logic-level data input (unshaped data pulses). OOK modulation is practical for data pulses of 200 µs or longer. In the ASK mode, this pin accepts analog modulation (shaped or unshaped data pulses). ASK modulation is practical for data pulses 8.7 µs or longer. This pin must be low in the power-down (sleep) mode. ...

0.5W19V

0.5W19V

0.5W2.2V

1.5 LAN feature set 1 Ethernet 10/100 MII (HPNA compatible) 2 UARTs, Bluetooth compatible Bridging: Transparent bridge: IEEE 801.1d, spanning tree, learning/filter bridge in hardware Embedded router: RIP1, RIP2, static routing NAT/PAT with extended ALG support DHCP server/client IP protocol: TCP/IP, ARP sharing access, ICMP, IGMP

0.5W2.4V

Vendor:COSPackage Cooled:DO-35D/C:07+

1. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications).

0.5W2.4V

Vendor:COSPackage Cooled:DO-35D/C:07+

1. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications).

0.5W2.7V

With 1mA load With 1mA load With 20pF maximum load capacitance mea- sured from 10% to 90% of output voltage Output at (VDD -0.3V) Output at 0.3V MCLK can be driven DC-coupled by a CMOS clock oscillator with rail-to-rail out- puts. Other oscillator configurations may require AC-coupling.

0.5W20V

Resistors R1 and R2 set the nominal Under-Voltage (UV) lockout and Overvoltage (OV) shutdown limits to 84 V and 378 V, respectively. UV lockout protects the supply from overheating at low line and eliminates power-up and power- down glitches. OV shutdown protects the power supply from line surges.

0.5W24V

24421-009-DTS Rev ADQ# 2009 All technical information is believed to be accurate, but no responsibility is assumed for errors or omissions. Interpoint reserves the right to make changes in products or specifications without notice. HR300 Series is a trademark of Interpoint. Copyright © 1991 - 1999 Interpoint. All rights reserved.

0.5W24V

24421-009-DTS Rev ADQ# 2009 All technical information is believed to be accurate, but no responsibility is assumed for errors or omissions. Interpoint reserves the right to make changes in products or specifications without notice. HR300 Series is a trademark of Interpoint. Copyright © 1991 - 1999 Interpoint. All rights reserved.

0.5W27V

Vendor:COSPackage Cooled:DO-35D/C:07+

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

0.5W27V

Vendor:COSPackage Cooled:DO-35D/C:07+

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

0.5W3.1V

660 mW (Military) Synchronous and asynchronous output enables On-chip edge-triggered registers Buffered common PRESET and CLEAR inputs EPROM technology, 100% programmable Slim 300-mil, 24-pin plastic or hermetic DIP, 28-pin LCC, or 28-pin PLCC 5V 10% VCC, commercial and military TTL-compatible I/O Direct replacement for bipolar PROMs

0.5W3.9V

Vendor:COSPackage Cooled:DO-35D/C:07+

Figure 12 shows a dual-trace photograph of a triangular signal being sampled-and-held for approximately 14ms with a 300pF storage capacitor. The center trace (expanded to 20mV/Div.) shows the worst-case tilt for all the steps shown in the upper trace. The total equivalent leakage current in this case is only 170pA (I = C dv/dt).

0.5W3.9V

Vendor:COSPackage Cooled:DO-35D/C:07+

Figure 12 shows a dual-trace photograph of a triangular signal being sampled-and-held for approximately 14ms with a 300pF storage capacitor. The center trace (expanded to 20mV/Div.) shows the worst-case tilt for all the steps shown in the upper trace. The total equivalent leakage current in this case is only 170pA (I = C dv/dt).

0.5W30V

Vendor:COSPackage Cooled:DO-35D/C:05+

High FSK Sensitivity: -106 dBm at 20 kBaud/-109.5 dBm at 2.4 kBaud (433.92 MHz) High ASK Sensitivity: -112.5 dBm at 10 kBaud/-116.5 dBm at 2.4 kBaud (433.92 MHz) Low Supply Current: 10.5 mA in RX and TX Mode (3 V/TX with 5 dBm) Data Rate 1 to 20 kBaud Manchester FSK, 1 to 10 kBaud Manchester ASK ASK/FSK Receiver Uses a Low-IF Architecture with High Selectivity, Blocking and Low Intermodulation (Typical Bloc...

0.5W33V

Hynix HYMP512S64MP8 series is designed for high speed and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4- bit prefetche...

0.5W36V

In applications where these voltage ratings could be exceeded, e.g. by transient signals induced into long buffered bus lines, Schottky diodes and 15 V zener diode clamps should be fitted between GND and the buffered bus pins as shown in Figure 7.

0.5W3V

3-State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

0.5W4.3V

Vendor:COSPackage Cooled:DO-35D/C:07+

Reduced parts count and high efficiency add to the reliability of the HPR10XX Series. The high efficiency of the HPR10XX Series means less internal power dissipation, as low as 190mW. With reduced heat dissipation the HPR10XX Series can oper- ate at higher temperatures with no degradation. In addition, the high efficiency of the HPR10XX Series means the series is able to offer greater than 13 W/inch3 of...

0.5W4.7V

Vendor:COSPackage Cooled:DO-35D/C:07+

All digital clocks generate unwanted energy in their harmonics. Conventional digital clocks are square waves with a duty cycle that is very close to 50%. Because of this 50/50 duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics, i.e., third, fifth, seventh, etc. It is possible to reduce the amount of energy contained in the fundamental and odd harmonics by increasing ...

0.5W5.6V

Vendor:COSPackage Cooled:DO-35D/C:07+

Note 8: CIN, COUT, C1, and C2: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Note 9: Output resistance is a model for the voltage drop at the output, resulting from internal switch resistance, capacitor ESR, and charge pump charge transfer characteristics. Output voltage can be predicted with the following equation: VOUT = -[VIN - (IOUT x ROUT)]

0.5W5.6V

Vendor:COSPackage Cooled:DO-35D/C:07+

Note 8: CIN, COUT, C1, and C2: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Note 9: Output resistance is a model for the voltage drop at the output, resulting from internal switch resistance, capacitor ESR, and charge pump charge transfer characteristics. Output voltage can be predicted with the following equation: VOUT = -[VIN - (IOUT x ROUT)]

0.5W6.2V

Vendor:COSPackage Cooled:DO-35D/C:07+

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition.

0.5W6.8

0.5W8.2V

Vendor:COSPackage Cooled:DO-35D/C:07+

• Well Defined Spatial Radiation Patterns • Viewing Angles: 6, 15, 23, 30 • High Luminous Output • Colors: 590 nm Amber 605 nm Orange 615 nm Reddish-Orange 626 nm Red • High Operating Temperature: TJ LED = +130C • Superior Resistance to Moisture • Four Package Options: With or Without Flange Base; With or Without Lead Stand- Offs

0.5W8.2V

Vendor:COSPackage Cooled:DO-35D/C:07+

• Well Defined Spatial Radiation Patterns • Viewing Angles: 6, 15, 23, 30 • High Luminous Output • Colors: 590 nm Amber 605 nm Orange 615 nm Reddish-Orange 626 nm Red • High Operating Temperature: TJ LED = +130C • Superior Resistance to Moisture • Four Package Options: With or Without Flange Base; With or Without Lead Stand- Offs

0.6 OFFSET 50PIN SMT WITH GND LF

0.6-2.5PF

Vendor:MFGPackage Cooled:4X4-2.5PD/C:08+

The direction of counting is set by the watchdog or VCC over- and undervoltage detec- tion. If the VCC monitoring detects an undervoltage condition, the failure signal VCCL (VCC low voltage) is set and starts the up counter. If the VCC monitoring detects an overvoltage condition, the failure signal VCCH (VCC high voltage) is set and starts the up counter.

0.68 RES5 5W

Package Cooled:TAIWAN

0.68P 50V +-0.25P C0G(NP0) 0402

0.68UF/50V/20/P5

Package Cooled:MEC

0.6A LD0REGULATOR SOT-223

0.6MM H4MM B/B FX8-80P-SV1 HRS LF

0.75A8V

Vendor:RAYCHEMD/C:03+

0.82UF/50V/20/P5

Package Cooled:MEC

00 6208 525 410 006

Vendor:KYOCERAPackage Cooled:08+D/C:1500

00.781.4868

Use the typical performance graphs as a guide for expected variations in current limit value with a given RCL and variations over temperature. The selected value of RCL must be added to the specified typical value of output resistance to calculate the total output resistance. Since the load current passes through RCL the value selected also affects the output voltage swing according to:

0000-033-051

0000045L6902

000-00528

Vendor:CREATIVEPackage Cooled:PQFP-208D/C:1

The TPS3803G15 device has a fixed-sense threshold voltage VIT set by an internal voltage divider, whereas the TPS3803C01 has an adjustable SENSE input that can be configured by two external resistors. In addition to the fixed sense threshold monitored at VDD, the TPS3805 devices provide a second adjustable SENSE input. RESET is asserted in case any of the two voltages drops below VIT.

000-00528

Vendor:CREATIVEPackage Cooled:PQFP-208D/C:1

The TPS3803G15 device has a fixed-sense threshold voltage VIT set by an internal voltage divider, whereas the TPS3803C01 has an adjustable SENSE input that can be configured by two external resistors. In addition to the fixed sense threshold monitored at VDD, the TPS3805 devices provide a second adjustable SENSE input. RESET is asserted in case any of the two voltages drops below VIT.

0000097P8164

Vendor:IBMPackage Cooled:N/AD/C:04+

PROTECTION SECTION Peak Current Limit Current Limit Delay Time(3) Thermal Shutdown Temperature(3) Shutdown Feedback Voltage Over Voltage Protection Shutdown Delay Current Leading Edge Blanking Time TOTAL DEVICE SECTION Operating Supply Current (control part only) Start-Up Charging Current Vstr Supply Voltage

0000097P8164

Vendor:IBMPackage Cooled:N/AD/C:04+

PROTECTION SECTION Peak Current Limit Current Limit Delay Time(3) Thermal Shutdown Temperature(3) Shutdown Feedback Voltage Over Voltage Protection Shutdown Delay Current Leading Edge Blanking Time TOTAL DEVICE SECTION Operating Supply Current (control part only) Start-Up Charging Current Vstr Supply Voltage

00000H4760

Vendor:IBMPackage Cooled:BGAD/C:02+

The LH1556FP is robust, ideal for telecom and ground fault applications. It contains two SPST nor- mally open switches (1 Form A) that replace electro- mechanical relays in many applications. It is constructed using a GaAs LED for actuation control and an integrated monolithic die for the switch output. The die, fabricated in a high-voltage dielectrically iso- lated BCDMOS technology, is comprised of...

00001341979

0000-6200-147-012-8

0000-6200-512-230-0

0000-6207-341-720-0

0000-8263-0412-00-0

0000-8263-1412-00-0

0000-8283-1012-00-0

0000-8370-091-000-8

0000-8370-207-000-8

0000915.568.

Vendor:PLCC-44PPackage Cooled:NSCD/C:2004+

This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a baseCemitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can re...

0000915.597.

Vendor:PLCC-44PPackage Cooled:NSCD/C:2004+

Device Protocol The X76F102 supports a bidirectional bus oriented pro- tocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as a receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operation...

0001.2513.BF

0001-003-01

Vendor:TELENEXPackage Cooled:PLCCD/C:07+

In operation, the HCPL-7860/ HCPL-786J Isolated Modulator (optocoupler with 3750 VRMS dielectric withstand voltage rating) converts a low- bandwidth analog input into a high-speed one-bit data stream by means of a Sigma-Delta (− ∆) over-sampling modulator. This modulation provides for high noise margins and excellent immunity against isolation-mode transients. The modulator data and on-chip...

0001-003-01

Vendor:TELENEXPackage Cooled:PLCCD/C:07+

In operation, the HCPL-7860/ HCPL-786J Isolated Modulator (optocoupler with 3750 VRMS dielectric withstand voltage rating) converts a low- bandwidth analog input into a high-speed one-bit data stream by means of a Sigma-Delta (− ∆) over-sampling modulator. This modulation provides for high noise margins and excellent immunity against isolation-mode transients. The modulator data and on-chip...

00015F4R7N0X

000-1900-005

000-1900-008

0-002

Vendor:NATIONAL

The HYM532810C M-Series is a 8Mx32-bit Fast Page mode CMOS DRAM module consisting of sixteen HY5117400C in 24/26 pin SOJ on a 72 pin glass-epoxy printed circuit board. 0.1µF and 0.01µF decoupling capacitors are mounted for each DRAM. The HYM532810CM is Tin plated and HYM532810CMG is Gold plated socket type Single In-line Memory Module suitable for easy interchange and addition of 32M byte memory.

0002062131

Vendor:MOLEXD/C:20000

0002091117

Vendor:MOLEX

0003061022

00031F2566

Vendor:TOSHIBAPackage Cooled:98+D/C:PLCC

0-0034070-0

Vendor:TYCOD/C:12000

0003-5

Vendor:INTERSILPackage Cooled:SOP-8P

Notes: 1. Derate above 91C at 0.53 mA/C. 2. See Figure 4 to establish pulsed conditions. 3. Derate above 53C at 0.45 mA/C. 4. Derate above 80C at 0.38 mA/C. 5. See Figure 5 to establish pulsed conditions. 6. Derate above 81C at 0.52 mA/C. 7. See Figure 6 to establish pulsed ocnditions. 8. Derate above 39C at 0.37 mA/C.