Index "1"Vendor:in stockPackage Cooled:PHILIPS D/C:06+
Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithman internal algorithm that automatically preprograms the array (if it is not already pro- grammed) before executing the erase operation. Dur- ing erase, the device automatically times the erase pulse widths and verifies proper cell margin.
Vendor:in stockPackage Cooled:PHILIPS D/C:06+
Figure 1-2 shows how the key values in EEPROM are used in the encoder. Once the encoder detects a button press, it reads the button inputs and updates the syn- chronization counter. The synchronization counter and crypt key are input to the encryption algorithm and the output is 32 bits of encrypted information. This data will change with every button press, its value appearing externally to randomly...
Vendor:in stockPackage Cooled:PHILIPS D/C:06+
Figure 1-2 shows how the key values in EEPROM are used in the encoder. Once the encoder detects a button press, it reads the button inputs and updates the syn- chronization counter. The synchronization counter and crypt key are input to the encryption algorithm and the output is 32 bits of encrypted information. This data will change with every button press, its value appearing externally to randomly...
Vendor:PHILIPSPackage Cooled:SOT-23
Vdd=2.7V~3.3V, TA = 0C to 70C(C) / -25C to 85C(E), unless otherwise specified -70-85 #SymbolParameter Min. Max. Min. Max. Read Cycle 1tRCRead Cycle Time70-85- 2tAAAddress Access Time-70-85 3tACSChip Select Access Time-70-85 4tOEOutput Enable to Output Valid-20-30 5tBA/LB, /UB Access Time-70-85 6tCLZChip Select to Output in Low Z10-10- 7tOLZOutput Enable to Output in Low Z5-5- 8tBLZ/LB, /...
Some of the topologys advantages are: 1) Stepping up or down the input voltage can easily be done by setting the turns ratio. 2) The transformer provides isolation between the input and output. 3) Each switch cycle applies VIN across the transformer in opposite polarities. Therefore, the transformer core never saturates and a separate reset circuit is not necessary.
Vendor:in stockPackage Cooled:PHILIPS D/C:06+
The epoxy TO-92 and TO-220 configurations feature Teccor's electrically-isolated construction where the case or mounting tab is internally isolated from the semiconductor chip and lead attachments. Non-isolated epoxy TO-202 packages are available as well as TO-251 and surface mount TO-252 (D-Pak). Tape- and-reel capability and tube packing also are available. See Packing Options section of this catalog.
Vendor:availPackage Cooled:PHILIPS D/C:06+
2 For practical applications a more precise description of the real R/T curve may be required. Either more complicated approaches (e.g the Steinhart-Hart equation) are used or the resistance/ temperature relation as given in tabulated form. The below table has been experimentally determined with utmost accuracy for temperature increments of 1 degree.
Vendor:availPackage Cooled:PHILIPS D/C:06+
For the pre-recorded voice prompts, the Philips International Language Library (PILL) tools are available for a standard multimedia PC platform under Windows 95/NT. These tools provide a way to compile a range of multi-lingual voice prompts for efficient storage in the speech (flash) memory. The PILL tools support various languages and their grammar adaptations.
Vendor:availPackage Cooled:PHILIPS D/C:06+
If a specific pattern is repetitive, the Deserializer could enter false lock - falsely recognizing the data pattern as the clocking bits. We refer to such a pattern as a repetitive multi-transition, RMT. This occurs when more than one Low-High transition takes place in a clock cycle over multiple cycles. This occurs when any bit, except DIN 9, is held at a
Vendor:availPackage Cooled:PHILIPS D/C:06+
• HFBR-5701L: Dual specified 1.25 GBd Ethernet (1000BASE-SX) and 1.0625 GBd Fibre Channel (100-M5- SN-I, 100-M6-SN-I) SFP • HFBR-5720L: 2.125 GBd Fibre Channel (200-M5-SN-I, 200-M6-SN-I) Multi-Mode SFP • HFBR-5730L: 1.0625 GBd Fibre Channel (100-M5-SN-I, 100-M6-SN-I) Multi-Mode SFP • HDMP-1687: Quad Channel SerDes IC 1.25 GBd Ethernet • HDMP-1646A: Single Channel ...
Vendor:PHILIPS
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated). An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull- ...
Fairchild's RUF series of Insulated Gate Bipolar Transistors (IGBTs) provides low conduction and switching losses as well as short circuit ruggedness. The RUF series is designed for applications such as motor control, uninterrupted power supplies (UPS) and general inverters where short circuit ruggedness is a required feature.
Vendor:availPackage Cooled:PHILIPS D/C:06+
PFC Driver Output. This pin must be connected to the PFC power MOSFET gate. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 10KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 250mA sink.
Notes: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR<10MHz, ZO...
Vendor:availPackage Cooled:PHILIPS D/C:06+
OUTPUT LEVELS: For the 49BV1604(T), Output High Levels (VOH) are equal to VCCQ - 0.2V (not VCC). For 2.7V - 3.6V output levels, VCCQ must be tied to V CC. For 1.8V - 2.2V output levels, VCCQ must be regulated to 2.0V 10% while VCC must be regulated to 2.7V - 3.0V (for minimum power).
Vendor:PHILIPS
OUTPUT VOLTAGE RANK LIST Device NameVOUTDevice Name NJM287*BF151.5VNJM287*BF26 NJM287*BF181.8VNJM287*BF27 NJM287*BF191.9VNJM287*BF28 NJM287*BF022.0VNJM287*BF29 NJM287*BF212.1VNJM287*BF03 NJM287*BF232.3VNJM287*BF31 NJM287*BF252.5VNJM287*BF32
Vendor:PHILIPSPackage Cooled:SOT323D/C:05+PBF
The 1PS70SB82 uses a 5 volt tolerant, industry-standard I2C-bus serial interface that runs at either low speed (100 kHz) or high speed (400 kHz). The interface uses 12 word addresses for control and status: one write-only, eight read/write, and three read-only addresses.
Vendor:PhilipsPackage Cooled:Sot-323D/C:09+
The CLBs are used to implement most of the logic in an FPGA. The principal CLB elements are shown in the simpli- fied block diagram in Figure 2. There are three look-up tables (LUT) which are used as logic function generators, two flip-flops and two groups of signal steering multiplexers. There are also some more advanced features provided by the CLB which will be covered in the Advanced Features Desc...
Vendor:PhilipsPackage Cooled:Sot-323D/C:09+
The CLBs are used to implement most of the logic in an FPGA. The principal CLB elements are shown in the simpli- fied block diagram in Figure 2. There are three look-up tables (LUT) which are used as logic function generators, two flip-flops and two groups of signal steering multiplexers. There are also some more advanced features provided by the CLB which will be covered in the Advanced Features Desc...
Vendor:PHILIPSPackage Cooled:SOT323D/C:01+
The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and con- trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will...
Vendor:PHILIPSPackage Cooled:SOT323D/C:01+
To drive the FET properly, the gate voltage must be referenced to its source. For enhancement-mode MOSFETs, this gate potential is of the same polarity as the MOSFETs drain voltage. To turn on, the n-channel MOSFET requires a positive gate-source voltage, whereas the p-channel MOSFET requires a negative gate-source potential.
Vendor:PHILIPSPackage Cooled:SOT523D/C:05+PBF
Hynix HYMP512S64MP8 series is designed for high speed and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4- bit prefetche...
Vendor:PHILIPSPackage Cooled:SOT523D/C:05+PBF
Hynix HYMP512S64MP8 series is designed for high speed and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4- bit prefetche...
Vendor:PHILIPSPackage Cooled:SOD323D/C:05+PBF
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Currents are...
Vendor:PHILIPSPackage Cooled:SOT-323D/C:08+
o +2.7V to +5.5V Input Range o Output Voltages +0.4V to +3.4V Output at 600mA (Top Circuit) +1.5V Output at 600mA (Bottom Circuit) o Dynamically Variable Output Voltage (Top Circuit) o Adjustable Output Voltage Through Resistive Voltage-Divider (Bottom Circuit) o Internal Switch and Synchronous Rectifier o 0.1µA (typ) IC Shutdown Current o 1MHz PWM Switching Frequency o Syncable to 13MHz O...
Vendor:in stockPackage Cooled:PHILIPSD/C:07+
M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Separate upper-byte and lower-byte controls for multi- plexed bus and bus matching compatibility LVTTL-compatible, single 3.3V (0.3V) power supply Availabl...
Vendor:NXP/PHILIPSD/C:07/08+
VIN: Supplies the current to the collector of the output-power transistor only. The dropout (VIN−VOUT) is under 100 mV for light loads; maximum dropout is 450 mV at 3 A for TJ = 0C to 100C. (Dropout is derated for junction temperatures over 100C.) At full load, the majority of the VB current is going to the load.
Vendor:NXPD/C:08+
The TLE214x and TLE214xA devices are high-performance, internally compensated operational amplifiers built using Texas Instruments complementary bipolar Excalibur process. The TLE214xA is a tighter offset voltage grade of the TLE214x. Both are pin-compatible upgrades to standard industry products.
Vendor:PHILIPSD/C:南北桥显卡
The two-tone IMD test signal can be generated by a number of means of which the following three are the most common: System A A two-tone audio signal is formed by algebraically adding two sine wave voltages of equal amplitude which are not harmonically related, e.g., 800 Hz and 1.8 kHz. This two-tone audio signal is fed into a balanced modulator together with an RF carrier, one sideband filtered o...
Vendor:NXP
Vendor:NXP/PHILIPSD/C:07/08+
Serial data from the demodulator is passed first through the data descrambler and then through the SYNC/ASYNC converter. The ASYNC/ASYNC converter will reinsert any deleted stop bits and output data at an intra-character rate (bit-to-bit timing) of no greater than 1219 bit/s. An incoming break signal (low through two characters) will be passed through without incorrectly inserting a stop bit.
REF: Precision 5.0V reference pin. REF can supply up to 5mA to external circuits. REF is off until VDD exceeds 9V (C1 and C3 versions) or activates the 15V clamp (C2 and C4 versions) and turns off again when VDD droops below 8.5V. Bypass REF to GND with a 1mF capacitor.
Package Cooled:QFPD/C:00+
The alignment-free DRX 3960A needs no special external components. All control functions and status registers are accessible via I2C bus interface. There- fore, it simplifies the design of high-quality, highly stan- dardized IF stages.
Reverberation and echo effects of audio equipment such as radio cassette recorder, car radio, portable radio, portable stereo, echo microphone and Karaoke machine, etc. Sound effect of electronic musical instruments Variable or fixed delay of analog signals
Vendor:in stockPackage Cooled:PHILIPSD/C:07+
These pins accept the 12 data inputs from a digital video port of a graphics controller. The levels are 0 to DVDDV, and the VREF signal is used as the threshold level. External Clock Inputs These inputs form a differential clock signal input to the CH7009 for use with the H, V, DE and D[11:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF.
Vendor:PHILIPSPackage Cooled:SOT523D/C:05+PBF
SymbolParameter Output Characteristics VOT(+)Differential Output Voltage for the True Binary State VOT(-)Differential Output Voltage for the False Binary State ∆VOTChange in VOT Between Complementary Output States VOSOutput Common Mode Voltage (Offset Voltage) ∆VOSChange in VOS Between Complementary Output States IOSOutputs Short Circuit Current Differential Outputs Short Circuit Cu...
Vendor:PHILIPSPackage Cooled:SOT-323D/C:07+环保
Function DAC1 Lch Negative Analog Output Pin DAC1 Lch Positive Analog Output Pin Zero Input Detect 3 Pin Zero Input Detect 2 Pin Zero Input Detect 1 Pin Chip Address 0 Pin Auto Setting Mode Disable Pin (Pull-down Pin) L: Auto Setting Mode, H: Manual Setting Mode Power-Down Mode Pin When at L, the 1PS89SB74 is in the power-down mode and is held in reset. The 1PS89SB74 should always be reset u...
Vendor:PHILIPSPackage Cooled:SOT523D/C:04+PBF
Analog-to-Digital Converters − 24-Bit Linear PCM or 1-Bit Direct Stream Digital (DSD) Output Data − Supports PCM Output Sampling Rates up to 216kHz − Supports 64fS and 128fS DSD Output Data Rates Dynamic Performance: PCM Output − Dynamic Range: 118dB − THD+N: −105dB Dynamic Performance: DSD Output − Dynamic Range: 115dB − THD+N: −103dB Audio Se...
Vendor:PHILIPSPackage Cooled:SOT-523D/C:07+环保
Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active and is not driven from an external source.
The Si6924AEDQ is a dual n-channel MOSFET with ESD protection and gate over-voltage protection circuitry incorporated into the MOSFET. The device is designed for use in Lithium Ion battery pack circuits. The common-drain contsruction takes advantage of the typical battery pack topology, allowing a further reduction of the devices on-resistance. The 2-stage input protection circuit is a unique design, ...
Vendor:ROHMPackage Cooled:732
Vendor:KEMETPackage Cooled:735
Vendor:KEMETPackage Cooled:736
Vendor:KEMETPackage Cooled:732
Vendor:KEMETPackage Cooled:738
Vendor:AVXPackage Cooled:732
Vendor:BUSSMANNPackage Cooled:726
Vendor:SAMTECPackage Cooled:712
Vendor:NAVMANPackage Cooled:N/AD/C:0421
1. Stresses beyond those listed may cause permanent damage to the device. These are stress rating only and functional operation of the device at these or any other conditions beyond those under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Vendor:AGILENTD/C:0037+/0038/0033
The result of the most recent Main Memory Page to Buffer Compare operation is indi- cated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer.
Package Cooled:DIP-36D/C:99+
Differential Input: This input pair is the signal to be buffered. These inputs accept AC or DC- coupled signals as small as 100mV. Each pin of this pair internally terminates to a VT pin through 50Ω. Note that this input will default to an indeterminate state if left open. Please refer to the Input Interface Applications section for more details.
C Standard specific digital picture carrier recovery: • alignment-free • quartz-stable and accurate • stable frequency lock at 100% modulation and overmodulation up to 150% • quartz-accurate AFC information
Package Cooled:08+D/C:800
Package Cooled:08+D/C:800
Package Cooled:08+D/C:800
Package Cooled:08+D/C:800
Package Cooled:08+D/C:800
Vendor:ADVANCED INTERCONNECTIONSD/C:N/A
Vendor:N/APackage Cooled:30D/C:N/A
Vendor:N/APackage Cooled:30D/C:N/A
Vendor:HPPackage Cooled:9949+
Case: Molded Epoxy Epoxy Meets UL94, VO at 1/8 Weight: 70 mg (approximately) Finish: All External Surfaces Corrosion Resistant and Terminal Leads are Readily Solderable Lead and Mounting Surface Temperature for Soldering Purposes: 260C Max. for 10 Seconds Polarity: Polarity Band Indicates Cathode Lead ESD Ratings: Machine Model = C ESD Ratings: Human Body Model = 3B Available in 12 mm Tape, 5000 Units...
Vendor:HPPackage Cooled:9949+
Case: Molded Epoxy Epoxy Meets UL94, VO at 1/8 Weight: 70 mg (approximately) Finish: All External Surfaces Corrosion Resistant and Terminal Leads are Readily Solderable Lead and Mounting Surface Temperature for Soldering Purposes: 260C Max. for 10 Seconds Polarity: Polarity Band Indicates Cathode Lead ESD Ratings: Machine Model = C ESD Ratings: Human Body Model = 3B Available in 12 mm Tape, 5000 Units...
Vendor:AGILENTPackage Cooled:CGA3535D/C:01+/03+
Places the 1-bit bypass register between the TDI and TDO pins, which allows the boundary scan test data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins.
Vendor:AGILENTPackage Cooled:CGA3535D/C:01+/03+
Places the 1-bit bypass register between the TDI and TDO pins, which allows the boundary scan test data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins.
Vendor:HPPackage Cooled:BGA2727D/C:99+
The capacitor connected to this pin sets the Cycle Skip period. Once a cycle skip fault is detected, the capacitor connected to this pin is discharged. The capacitor is then charged with a constant current of 12 mA. The cycle skip period expires, once the voltage on this capacitor reaches 2.0 V. A soft−start sequence follows at the conclusion of the fault period.
Vendor:AgilentPackage Cooled:9918/21D/C:2133
Parameter SK Clock Frequency SK High Time SK Low Time Minimum CS Low Time CS Setup Time DI Setup Time CS Hold Time DI Hold Time Output Delay to "1" Output Delay to "0" CS to Status Valid CS to DO in 3-state Write Cycle Time 5V, 25ºC
Vendor:AgilentPackage Cooled:9918/21D/C:2133
Parameter SK Clock Frequency SK High Time SK Low Time Minimum CS Low Time CS Setup Time DI Setup Time CS Hold Time DI Hold Time Output Delay to "1" Output Delay to "0" CS to Status Valid CS to DO in 3-state Write Cycle Time 5V, 25ºC
Vendor:AGILENTPackage Cooled:BGA2727D/C:00+/04+
NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top computers for the first three years of five yea...
Vendor:HPPackage Cooled:30D/C:N/A
The TLK4250 device is a four-channel, multi-gigabit transceiver used in high-speed bidirectional point-to-point data transmission systems. The four channels in the transceiver are configured as four separate links. The transceiver supports an effective serial interface speed of 1.0 Gbps to 2.5 Gbps per channel, providing up to 2.25 Gbps of data bandwidth per channel.
Vendor:AGILENTPackage Cooled:00+D/C:720
Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC- VAC, Post Office Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.
Vendor:IN STOCKPackage Cooled:9836D/C:HP
The ADSP-BF535 Blackfin processor is a highly integrated system-on-a-chip solution for the next generation of digital com- munication and portable Internet appliances. By combining industry-standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The ADSP-BF535 Blackfin processor system periph...
The ADSP-BF535 Blackfin processor is a highly integrated system-on-a-chip solution for the next generation of digital com- munication and portable Internet appliances. By combining industry-standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The ADSP-BF535 Blackfin processor system periph...
The Hardware Integrity function uses transmission line theory to measure the arrival time and electrical characteristics of the wave reflected back from an incident test wave launched on the media. With these measurements, opens, shorts, and degraded cable quality can be located along the wire, and lead the network manager to the location of the problem.
Operates from 2.7V to 44V Over-The-Top®: Input Common Mode Range Extends 44V Above V C, Independent of V + Micropower: 35µA IQ Offset Voltage: 1.5mV Max 5-Pin SOT-23 Package Valid Output with Either Input 5V Below V C Rail-to-Rail Output Swing Output Can Drive Loads Above V + Internal Pull-Up Current C 40C to 125C Operating Temperature Range
Vendor:availPackage Cooled:AGILENTD/C:04+
With a 1.0 V internal reference. Measured at fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure. 4Measured at AC Specifications conditions without output drivers. 5Measured with a dc input, CLK pin inactive (i...
Vendor:PLCC-32PPackage Cooled:AGILENTD/C:2004+
† All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full range for the µA741C is 0C to 70C, the µA741I is C 40C to 85C, and the µA741M is C 55C to 125C. NOTE 5: This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback.