100B221JP200X

Vendor:AMERICAN TECHNICAL CERAMICSD/C:0041

100B2R0-B-AW-X-500

100B330MW500XT

Vendor:AMERICAN TECHNICAL CERAMICSD/C:0011

100B331FW200X

Vendor:AMERICAN TECHNICAL CERAMICSD/C:0015+

100B360JW500X

Vendor:AMERICAN TECHNICAL CERAMICSD/C:0530

100B390KP

100B3R0BP500X

100B3ROBW500XT

Vendor:ATCPackage Cooled:1210D/C:0105

The HC27 and HCT27 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family.

100B470JP500X

Vendor:AMERICAN TECHNICAL CERAMICSD/C:9835+

100B4R7BP500X

100B54R4EAW500X

100B-560KP

100B5R6CW500X

Vendor:AMERICAN TECHNICAL CERAMICSD/C:9946

100B8R2JW500XT

D/C:2000

This document describes part-number-specific changes to recommended operating conditions and revised electrical specifications, as applicable, from those described in the general MPC8241 Integrated Processor Hardware Specifications (Order No. MPC8241EC/D). The MPC8241 combines a MPC603e PowerPC™ core microprocessor with a PCI bridge.

100BGQ015

Parameter RESOLUTION Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION (PSRR) ANALOG INPUTS (AIN, AIN)1 Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance Input Bandwidth VSWR 2 POWER SUPPLY 3 Supply Current IAVCC (AVCC = 5.0 V) IEVCC (EVCC = 3.3 V) ...

100BGQ015

Parameter RESOLUTION Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION (PSRR) ANALOG INPUTS (AIN, AIN)1 Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance Input Bandwidth VSWR 2 POWER SUPPLY 3 Supply Current IAVCC (AVCC = 5.0 V) IEVCC (EVCC = 3.3 V) ...

100BGQ015J

100BGQ030J

Notes a. Surface Mounted on 1 x 1 FR4 Board. b. Junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJF + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of a heat carrying (...

100BGQ045

Vendor:VishayPackage Cooled:PowerTabD/C:08+

* Start-up by SPEED key a. function turn off (OFF key) b. wind mode select (MODE key) c. start-up function and wind speed select (SPEED key) d. timer setting (TIMER key) e. swing head or tuner for swing angle (SW1 and SW2 key) f. lighting control (LIGHT key)

100C120B

100C150B

100C20B

Vendor:850

100C25B

100C30B

100C50B

100C60B

100CE100KXT

100CE2R2BS

100CE2R2C

100CE3R3FS

100CE4R7C

100CE4R7FS

100CEF2025V

100CER47FS

100-CG0974

100E016FN

Vendor:MOTPackage Cooled:PLCCD/C:03+

Packaged in a small, 32-pin TDIP, the functionally complete ADS-944 contains a fast-settling sample-hold amplifier, a subranging (two-pass) A/D converter, an internal reference, timing and control logic, three-state outputs, and error- correction circuitry. Digital input and output levels are TTL.

100E116FN

Vendor:MOTPackage Cooled:PLCCD/C:03+

The 100E116FN is an OC-12/STM-4, Quad OC-3/ STM-1 POS/ATM Framer with integrated CDRs. ATM direct mapping and cell delineation are supported, so are packets (PPP) over SONET for POS mapping and frame processing. The 100E116FN contains an in- tegral SONET framer which provides framing and er- ror accumulation in accordance with ANSI/ITU-T specifications. The configuration of this device is through in...

100E116FN

Vendor:MOTPackage Cooled:PLCCD/C:03+

The 100E116FN is an OC-12/STM-4, Quad OC-3/ STM-1 POS/ATM Framer with integrated CDRs. ATM direct mapping and cell delineation are supported, so are packets (PPP) over SONET for POS mapping and frame processing. The 100E116FN contains an in- tegral SONET framer which provides framing and er- ror accumulation in accordance with ANSI/ITU-T specifications. The configuration of this device is through in...

100E131FN

Vendor:MOTPackage Cooled:PLCCD/C:03+

The DSP supports nested and nonnested interrupts. Each inter- rupt type has a register in the interrupt vector table. Also, each has a bit in both the interrupt latch register and the interrupt mask register. All interrupts are fixed as either level-sensitive or edge-sensitive, except the IRQ3C0 hardware interrupts, which are programmable.

100E143FN

Vendor:MOTPackage Cooled:PLCCD/C:03+

Fourth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications.

100EL11M

This application note presents the design of a temperature display LIN slave node. It was developed as part of a complete door project which also included the keypad module described in application note AN2205. The messaging scheme for the door incorporated a byte for temperature in the mirror response field as shown in table 1. The LIN master is, in this case, the body controller. On a regular basis, sa...

100EL14

Vendor:ONPackage Cooled:SOP20

Notes: 1. Load and Line Regulation are specified at a constant junction temperature. Pulse testing with low duty cycle is used. Changes in output voltage due to heating effects must be taken into account separately. 2. If not tested, shall be guaranteed to the specified limits. 3. The • denotes the specifications which apply over the full operating temperature range.

100EL15

100EL15

100EL16M

Vendor:fscPackage Cooled:dc03D/C:2320

The LC/LV/LD549 is an 8 pin, low voltage, push-pull audio frequency output stage amplifier with a single unbalanced input. The circuit utilizes two internal negative feedback loops to stabilize the DC operating point for temperature stability and to linearize the transfer function over a wide dynamic range. The circuit operates near ideal class B conditions resulting in low distortion and very low quiescent ...

100EL16M

Vendor:fscPackage Cooled:dc03D/C:2320

The LC/LV/LD549 is an 8 pin, low voltage, push-pull audio frequency output stage amplifier with a single unbalanced input. The circuit utilizes two internal negative feedback loops to stabilize the DC operating point for temperature stability and to linearize the transfer function over a wide dynamic range. The circuit operates near ideal class B conditions resulting in low distortion and very low quiescent ...

100EL29

Vendor:ONPackage Cooled:SOP20

Altera® ACEX 1K devices provide a die-efficient, low-cost architecture by combining look-up table (LUT) architecture with EABs. LUT-based logic provides optimized performance and efficiency for data-path, register intensive, mathematical, or digital signal processing (DSP) designs, while EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. These elements make ACEX 1K suitab...

100EL38

Vendor:ONPackage Cooled:03/99+D/C:607

Decouple the output of the UC385 with at least 100 µF of high quality tantalum or Sanyo OSCON capacitors close to the VOUT pin for maximum stability. Many applications involving ultrafast GTL or BTL applications require additional capacitance close to the load. The exact amount will vary according to speed and magnitude of the load transients and the tolerance allowed for transients on VOUT. When sp...

100EL57

Vendor:MOTPackage Cooled:SOPD/C:07/08+

The upper and lower gates are held low until the driver is initialized. Once the VCC voltage surpasses the VCC Rising Threshold (See Electrical Specifications), the PWM signal takes control of gate transitions. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [tPDLLGATE], the lower gate begins to fall. Typical fall times [tFLGATE] are ...

100EL59

Vendor:MOT

Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is possible depending on burst length, CAS latency and speed grade of the device.

100EL91

Vendor:ONPackage Cooled:SOP20

If the FIFO is configured to have two write enables, when Write Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation.

100ELT16LVD-LF

Vendor:ONPackage Cooled:N/AD/C:08+

100ELT22M

Vendor:Fairchild

In designing a crystal oscillator, the values of C1 and C2 as shown in the reference design are dependent on the selected crystal. R1 is critical to the start up performance and drive level to the crystal. Because the system load is isolated by the internal buffer in the 74LVC1GX04, these calculations can be done once for many different system loads. For the reference design as shown, the crystal load cap...

100EP14

Vendor:ONPackage Cooled:TSOP

Notes: 1. NC pins are not connected to the die. 2. C2 (DNU) can be left as NC or VSS to ensure proper application. 3. VIL(min.) = C2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.

100EP14

Vendor:ONPackage Cooled:TSOP

Notes: 1. NC pins are not connected to the die. 2. C2 (DNU) can be left as NC or VSS to ensure proper application. 3. VIL(min.) = C2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.

100EP210UTG

100EP40

Vendor:ONPackage Cooled:TSSOP-20D/C:03

Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

100EP451LTG

100EP56

Vendor:ONPackage Cooled:TSSOP-20D/C:03

The BIU uses a set of control registers to determine how many wait states and hold states are to be used when ac- cessing flash EEPROM program memory, ISP memory and the I/O area (Port B and Port C). Upon start-up the configu- ration registers are set for slowest possible memory access. To achieve fastest possible program execution, appropriate values should be programmed. These settings vary with the clock ...

100EP56

Vendor:ONPackage Cooled:TSSOP-20D/C:03

The BIU uses a set of control registers to determine how many wait states and hold states are to be used when ac- cessing flash EEPROM program memory, ISP memory and the I/O area (Port B and Port C). Upon start-up the configu- ration registers are set for slowest possible memory access. To achieve fastest possible program execution, appropriate values should be programmed. These settings vary with the clock ...

100EP90

Vendor:ONPackage Cooled:SOP

COL A, COL B (Pins 3, 14): These are the open collectors of the output power switches. They are connected to the outer terminals of the center tap transformer. Large cur- rents flow into these pins so external traces should be kept as short as possible.

100EPT21DS

100FL34

Vendor:ONPackage Cooled:SOP-16D/C:03

The second mechanism controls the replacement algorithm, when a TLB miss occurs. The RC4700 provides a random replacement algo- rithm to select a TLB entry to be written with a new mapping; however, the processor provides a mechanism whereby a system specific number

100FL34

Vendor:ONPackage Cooled:SOP-16D/C:03

The second mechanism controls the replacement algorithm, when a TLB miss occurs. The RC4700 provides a random replacement algo- rithm to select a TLB entry to be written with a new mapping; however, the processor provides a mechanism whereby a system specific number

100G6P43

Vendor:TOSHIBA

Settling Time, tS C The time required by the device, after tPO, and after a valid magnetic signal has been applied, to provide proper output transitions. Settling time is a function of magnetic offset, offset polarity, signal phase, signal frequency, and signal amplitude.

100GC2T6N8JQS

D/C:07+

The 100GC2T6N8JQS stereo DAC is a high performance 24-bit digital to analog audio converter. Dynamic range is 107dB (A- weighted). The sensible pinout and easy user interface are unprecedented. The part contains an internal high quality phase- locked loop that eliminates the need for external high frequency clocks.

100H602

Vendor:MOTPackage Cooled:PLCCD/C:03+

This pin is the positive supply pin, and should always be the most positive point in the circuit. Internal circuitry connected to this pin is used to provide power on reset of the microprocessor, so an external reset signal is not required. Refer to the Electrical Characteristics section for further information.

100H602

Vendor:MOTPackage Cooled:PLCCD/C:03+

This pin is the positive supply pin, and should always be the most positive point in the circuit. Internal circuitry connected to this pin is used to provide power on reset of the microprocessor, so an external reset signal is not required. Refer to the Electrical Characteristics section for further information.

100H603

Vendor:MOTPackage Cooled:PLCC28D/C:07/08+

100H643

Vendor:MOTPackage Cooled:PLCCD/C:03+

The Am29LV652D offers access times of 90 and 120 ns and is offered in a 63-ball FBGA package. To elimi- nate bus contention the Am29LV652D device contains two separate chip enables (CE# and CE2#). Each chip enable (CE# or CE2#) is connected to only one of the two dice in the Am29LV652D package. To the sys- tem, this device is the same as two independent Am29LV065D on the same board. The only differ- ence ...

100H643

Vendor:MOTPackage Cooled:PLCCD/C:03+

The Am29LV652D offers access times of 90 and 120 ns and is offered in a 63-ball FBGA package. To elimi- nate bus contention the Am29LV652D device contains two separate chip enables (CE# and CE2#). Each chip enable (CE# or CE2#) is connected to only one of the two dice in the Am29LV652D package. To the sys- tem, this device is the same as two independent Am29LV065D on the same board. The only differ- ence ...

100H646

Vendor:MOTPackage Cooled:PLCCD/C:03+

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Non−repetitive current pulse per Figure 1 (Pin 5 to Pin 2)

100H646

Vendor:MOTPackage Cooled:PLCCD/C:03+

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Non−repetitive current pulse per Figure 1 (Pin 5 to Pin 2)

100HF646

Vendor:LUCENTPackage Cooled:PLCC

The device can be used in applications where two buses need to be addressed simultaneously. The FSTU32160A is designed so that the A Port demultiplexes into B1 or B2 or both. The A and B Ports have undershoot hardened cir- cuit protection to support an extended range to 2.0V below ground. Fairchilds integrated Undershoot Hardened Cir- cuit, UHC senses undershoot at the I/Os, and responds by pr...

100ID/LQFP

External tone modulation. To improve design flexibility and to allow implementation of proposed LNB remote control standards, an analog modulation input terminal is available (EXTM). An appropriate dc-blocking capacitor must be used to couple the modulating signal source to the EXTM terminal. The peak-to-peak input amplitude should stay within 100-mV to 125-mV to ensure the DiSEqC amplitude specific...

100ID/LQFP

External tone modulation. To improve design flexibility and to allow implementation of proposed LNB remote control standards, an analog modulation input terminal is available (EXTM). An appropriate dc-blocking capacitor must be used to couple the modulating signal source to the EXTM terminal. The peak-to-peak input amplitude should stay within 100-mV to 125-mV to ensure the DiSEqC amplitude specific...

100JB1L

Vendor:IOEPackage Cooled:模块

The device can be used in applications where two buses need to be addressed simultaneously. The FSTU32160 is designed so that the A Port demultiplexes into B1 or B2 or both. The A and B Ports have undershoot hardened cir- cuit protection to support an extended range to 2.0V below ground. Fairchilds integrated Undershoot Hardened Circuit (UHC) senses undershoot at the I/Os, and responds by prev...

100K OHM 0402 5 T-XPB

Package Cooled:YAGEO

100K OHM 0603 5 T

Package Cooled:YAGEO

100K OHM 0805 1 T

Package Cooled:YAGEO

100K OHM 1206 5 T-XPB

Package Cooled:YAGEO

100K14W

100KBII

100KPF/ 1812/ X7R/ 10/ 100V

D/C:06+

100LDDUMMY

Vendor:VLSIPackage Cooled:PQFP-100D/C:99

Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When Logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising ...

100LDDUMMY

Vendor:VLSIPackage Cooled:PQFP-100D/C:99

Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When Logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising ...

100LDTQFP

The large (32K-byte) program cache translates to a high hit rate for most applications. This prevents most program/data access conflicts to the on-chip memory. It also enables effective program execution from an off-chip memory such as an SDRAM.

100LEAD

Vendor:.Package Cooled:2005D/C:500

Fully compliant with the Universal Serial Bus Specification, version 1.1 USB keyboard design is compliant with USB Device Class Definition for Human Interface Devices (HID), version 1.1 Built-in 3.3v voltage regulator allows single +5V operating voltage drawing directly from USB bus Intergrated USB full speed transceiver Support for 19 x 8 standard key matrix. An Fn pin to select alternative matrix. Eac...

100LEAD

Vendor:.Package Cooled:2005D/C:500

Fully compliant with the Universal Serial Bus Specification, version 1.1 USB keyboard design is compliant with USB Device Class Definition for Human Interface Devices (HID), version 1.1 Built-in 3.3v voltage regulator allows single +5V operating voltage drawing directly from USB bus Intergrated USB full speed transceiver Support for 19 x 8 standard key matrix. An Fn pin to select alternative matrix. Eac...

100LQFP

Note 1: All parameters tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCLs falling edge. Note 3: Guaranteed by design. Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x V...

100LQFP

Note 1: All parameters tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCLs falling edge. Note 3: Guaranteed by design. Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x V...

100LT100

Vendor:LATTICEPackage Cooled:QFPD/C:00+

100LV39

Package Cooled:2226D/C:05+

100LVE111

Vendor:MOTOROLAPackage Cooled:PLCC28

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface−mounted on FR4 board using 1 in sq pad size. 2. Surfa...

100LVE111

Vendor:MOTOROLAPackage Cooled:PLCC28

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface−mounted on FR4 board using 1 in sq pad size. 2. Surfa...

100LVE92

Vendor:MOTPackage Cooled:SOPD/C:08+

The bq2050H Lithium Ion Power Gauge™ IC is intended for battery- pack or in-system installation to maintain an accurate record of available battery capacity. The IC monitors a voltage drop across a sense resistor connected in series between the negative battery termi- n a l a n d g r ou n d t o d e t e r m i n e charge and discharge activity of the battery. Compensations for bat- tery temperature, ...

100LVEL11M

Vendor:Fairchild

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

100LVEL13

Vendor:ONPackage Cooled:SOPD/C:N/A

This ultrafast recovery rectifier diode series is military qualified to MIL-PRF- 19500/477 and is ideal for high-reliability applications where a failure cannot be tolerated. These industry-recognized 2.5 Amp rated rectifiers for working peak reverse voltages from 50 to 150 volts are hermetically sealed with voidless-glass construction using an internal Category I metallurgical bond. They are also availabl...

100LVEL13

Vendor:ONPackage Cooled:SOPD/C:N/A

This ultrafast recovery rectifier diode series is military qualified to MIL-PRF- 19500/477 and is ideal for high-reliability applications where a failure cannot be tolerated. These industry-recognized 2.5 Amp rated rectifiers for working peak reverse voltages from 50 to 150 volts are hermetically sealed with voidless-glass construction using an internal Category I metallurgical bond. They are also availabl...

100LVEL14

D/C:96+

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