1303418020

130362

Vendor:HARRISPackage Cooled:DIP-40D/C:9732

(1)Pulse generator (PG) characteristics : PRR=1kHz, tw = 10µs, tr = 6ns, tf = 6ns, Zo = 50Ω, VP = 3VP-P (2)Input-output conditions : RL = 500Ω, Vo = 10V, VCC = 6V (3)Electrostatic capacity CL includes floating capacitance at connections and input capacitance at probes

130362N

Active-Low. Reset is asserted when VCC drops below VTH and remains asserted until VCC rises above VTH for the duration of the reset timeout period. The MAX6323 has a push-pull output and the MAX6324 has an open-drain output. Connect a pullup resistor from RESET to any supply voltage up to +6V.

13038120-001

Vendor:PHILIPSD/C:O9+

The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When ...

13038126

13038138-002

130-3846-001

• Full-Duplex Audio Processing for AMPS/ NAMPS Cellular Systems • On-Chip Speech and SAT Capabilities C TX/RX Filtering & Gain C SAT Channel Pre-/De-Emphasis C Deviation Limiter • Serial µProcessor Interface • Sidetone Output Available • Access to External Processes C Companding C Signaling C VSR Codec (Store/Play)

13038624DM

130-3880-001

Vendor:TPackage Cooled:PLCC

Case B Small Deadtime (Voltage on Pin 9 > Pin 11) A small differential voltage between Pin 9 and 11 provides the necessary time delay to reduce the chances of mo- mentary short circuit in the output stage during transi- tions, especially where power-amplifiers are used. Refer to Figure 3B.

130391

ance state. The output control does not affect the in- ternal operation of flip-flops. That is, the old data can be retained or the new data can be entered even while the outputs are off. The application engineer has a choice of combination of inverting and non-in- verting outputs. The 3-state output configuration and the wide choice of outline make bus-organized systems simple. All inputs are equipp...

130392

Vendor:HARRISPackage Cooled:DIP-40D/C:9217

ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS.

130392

Vendor:HARRISPackage Cooled:DIP-40D/C:9217

ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS.

13039D

D/C:08+

130426

Vendor:HARRISPackage Cooled:95+D/C:PLCC

PROCESSOR MODE In Processor Mode the CPU writes data to the Connection Memory Low locations which correspond to the output link and channel number. The contents of the Connection Memory Low are transferred to the parallel-to-serial converter one channel before it is to be output and are transmitted each frame to the output until it is changed by the CPU.

130436

Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the Start bit. The microprocessor must send a start bit periodically to prevent a RESET sig- nal. The start bit must occur prior to the expiration of the watchdog time-out period. The state of three nonvolatile control bits in the Control Register determines the watch- dog timer period. The microprocessor can ...

130446

Vendor:HARRISPackage Cooled:94+D/C:PLCC

130451

In Figure 1, the IC's switch-mode controller operates with an external inductor, two diodes, and two capacitors to produce 6.5V. FETs Q1 and Q2 ensure start-up for the circuit by disconnecting the load until these switch-mode supply voltages are present. Note that Q1 must be a logic-level device.

130451

In Figure 1, the IC's switch-mode controller operates with an external inductor, two diodes, and two capacitors to produce 6.5V. FETs Q1 and Q2 ensure start-up for the circuit by disconnecting the load until these switch-mode supply voltages are present. Note that Q1 must be a logic-level device.

130451//B1276-CH

Vendor:HARD/C:93+

Inputs Are TTL-Voltage Compatible 3-State Version of ACT11153 Permits Multiplexing From N Lines to One Line Performs Parallel-to-Serial Conversion Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enha...

130453

Vendor:availPackage Cooled:HARD/C:04+

The ICL8038 waveform generator is a monolithic integrated circuit capable of producing high accuracy sine, square, tri- angular, sawtooth and pulse waveforms with a minimum of external components. The frequency (or repetition rate) can be selected externally from 0.001Hz to more than 300kHz using either resistors or capacitors, and frequency modula- tion and sweeping can be accomplished with an externa...

130466E

Vendor:HARPackage Cooled:DIP-40D/C:2007

The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal must be connected to VDD through a 1-kΩ resistor. The SE and SM terminals must be tied to ground through a 1-kΩ resistor.

130466E

Vendor:HARPackage Cooled:DIP-40D/C:2007

The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal must be connected to VDD through a 1-kΩ resistor. The SE and SM terminals must be tied to ground through a 1-kΩ resistor.

130471

Vendor:N/APackage Cooled:30D/C:N/A

5V tolerant inputs and outputs 10 mA ICCQ max Power-down high impedance inputs and outputs Supports live insertion withdrawal 2 0VC3 6V VCC supply operation g24 mA output drive Implements patented Quiet SeriesTM noise EMI reduction circuitry Functionally compatible with the 74 series 273 Latch-up performance exceeds 500 mA ESD performance Human Body Model l 2000V Machine Model l 200V

130475PT-101

Vendor:INTERSILPackage Cooled:QFP

Parameter Remote On/Off Signal Interface (VI = 0 V to 75 V; open collector or equivalent compatible; signal referenced to VI(C) terminal; see Figure 12 and Feature Descriptions.): HW125x1 Preferred Logic: Logic LowModule On Logic HighModule Off HW125x Optional Logic: Logic LowModule Off Logic HighModule On Logic Low: At Ion/off = 1.0 mA At Von/off = 0.0 V Logic High: At Ion/off = 0.0 &...

130482

The HYM5V64804A Z-Series is a 8Mx64-bit EDO mode CMOS DRAM module consisting of eight 8Mx8 TSOP and one 2048-bit EEPROM on a 144 pin glass-epoxy printed circuit board. 0.1µF and 0.01µF decoupling capacitors are mounted for each DRAM. The HYM5V64804AZ G-series is gold plated socket type Dual In-line Memory Module suitable for easy interchange and addition of 64M byte memory.

1304831100

130486A

Vendor:HARPackage Cooled:95+D/C:DIP

130493

1304A

Vendor:AMPackage Cooled:SOPD/C:98+

Out of Phase Operation The 1304A drives its two output stages 180o out of phase. In 2-phase configuration, the two inductor ripple currents cancel each other and result to a reduction of the output current ripple and contribute to a smaller out- put capacitor for the same ripple voltage requirement.

130513

Vendor:HARRISPackage Cooled:95+D/C:PLCC

130515

Vendor:INTEYSILPackage Cooled:DIPD/C:08+

DEVICE OPERATION The operating modes of the M27C801 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPP and 12V on A9 for Elec- tronic Signature and Margin Mode Set or Reset. Read Mode The M27C801 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E)...

130518

Vendor:DIPPackage Cooled:HARRISD/C:2004+

Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM Users Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.

130518.00

Vendor:HARRISPackage Cooled:DIPD/C:98+

130523

Vendor:HARRISPackage Cooled:95+D/C:PLCC

Recovery time required when the device goes from power-down mode into bypass mode (test mode with AVDD at GND). ¶ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, s...

130523

Vendor:HARRISPackage Cooled:95+D/C:PLCC

Recovery time required when the device goes from power-down mode into bypass mode (test mode with AVDD at GND). ¶ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, s...

130542

D/C:96

130542

D/C:96

130542UEI

D/C:95

The two ACCESS.bus (ACB) interface modules support a two-wire serial interface compatible with the ACCESS.bus physical layer. It is also compatible with Intels System Man- agement Bus (SMBus) and Philips I2C bus. The ACB mod- ules can be configured as a bus master or slave, and they can maintain bidirectional communications with both multi- ple master and slave devices.

130545

Vendor:HARPackage Cooled:PLCC-44PD/C:6+

The CY7C133 and CY7C143 are high-speed CMOS 2K by 16 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C133 can be utilized as either a stand-alone 16-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C143 slave dual-port device in systems requiring 32-bit or greater word widths. It is the solution to applications requi...

130545580594.00

Vendor:HARRISPackage Cooled:PLCCD/C:97+

130549

Vendor:HARRISPackage Cooled:PLCC44D/C:98+

Transmit microphone input and the level adjustment. MAIN is connected to the noninverting input of the op-amp, and MAO is connected to the output of the op-amp. The level adjustment should be configured as shown below. During power saving and power down modes, the MAO output is in high impedance state.

130556

Vendor:HARRISD/C:95

Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. V...

130557

Vendor:REIPackage Cooled:95+D/C:PLCC

tpLZ7nsDisable time, low-level-to-high-impedance output (1) All typical values are at 25C and with a 3.3-V supply voltage. (2) tsk(bb), which only applies to the SN65MLVD129, is the magnitude of the difference between the tPLH and tPHL of two outputs of any bank. (3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operat...

130559

130565.00

Vendor:INTEYSILPackage Cooled:DIPD/C:96+

130570

Vendor:HARPackage Cooled:PLCC44D/C:N/A

The DE-SERIES SPICE Model is illustrated in Figure 1. The model is an expansion of the SPICE level 3 MOSFET model. It includes the stray inductive terms LG, LS and LD. Rd is the RDS(ON) of the device, Rds is the resistive leakage term. The output capacitance, COSS, and reverse transfer capacitance, CRSS are modeled with reversed biased diodes. This provides a varactor type re- sponse necessary for a high powe...

13058

Vendor:HARPackage Cooled:PLCC-44PD/C:6+

130583

CE is active LOW. Chip enables must be active when data read from or write to the device. If chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected.

130583.00

Vendor:HARRISPackage Cooled:PLCCD/C:96+

130588

Vendor:HARPackage Cooled:99+D/C:PLCC-44P

130593

Vendor:INTEYSILPackage Cooled:DIPD/C:08+

The passive bias circuits used in these designs include a dropping resistor in the collector bias line and a voltage divider from collector-to-base. Using this scheme the amplifier can be biased from a single supply voltage. The collector-dropping resistor is sized to drop 2-3V depending on the desired VCE . The voltage divider from collector-to-base, in conjunction with the dropping resistor, will stabiliz...

1305BP

Package Cooled:MSOPD/C:04+

13060

The AHCT574 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

130602

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). AC specifications are guaranteed by characterization, but not production tested. For propagation delays, tpdh refers to the specified signal going high; tpdl refers to it going low. GBD: Guaranteed by design; not tested in production. Specifications subject to change without notice.

130602

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). AC specifications are guaranteed by characterization, but not production tested. For propagation delays, tpdh refers to the specified signal going high; tpdl refers to it going low. GBD: Guaranteed by design; not tested in production. Specifications subject to change without notice.

130605

Vendor:HARRISPackage Cooled:PLCC44D/C:96+

130605

Vendor:HARRISPackage Cooled:PLCC44D/C:96+

130610

Vendor:HARRISPackage Cooled:QFPD/C:08+

When setting S1 at a high level or S2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high- impedance state, allowing OR-tie with other chips and memory expansion by S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as ICC3 or ICC4, and the memory data can be held...

130610.00

Vendor:HARRISPackage Cooled:QFPD/C:98+

130610IKC

Vendor:HARRISD/C:O9+

NOTES: 1. The falling edge of the Vin(C) signals a charge command, while the rising edge signals a spark command. 2. During start mode, stall conditions are prevented. 3. During a stall, the coil is discharged slowly and a quick charge and spark occur on the next spark command.

130610IKC

Vendor:HARRISD/C:O9+

NOTES: 1. The falling edge of the Vin(C) signals a charge command, while the rising edge signals a spark command. 2. During start mode, stall conditions are prevented. 3. During a stall, the coil is discharged slowly and a quick charge and spark occur on the next spark command.

130610IKC6-27-90

Vendor:INTERSILPackage Cooled:QFP

Hynix HYMD232726A(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipe...

130615

Vendor:HARRISPackage Cooled:PLCCD/C:08+

• International standard packages JEDEC TO-247 AD • Low RDS (on) HDMOSTM process • Rugged polysilicon gate cell structure • Unclamped Inductive Switching (UIS) rated • Low package inductance (< 5 nH) - easy to drive and to protect • Fast intrinsic Rectifier

130615.00

Vendor:HARRISPackage Cooled:PLCCD/C:99+

1306200A01

Vendor:GPSPackage Cooled:SOP16D/C:94+

The architecture allows reprogramming of the timers to support different media, DVD or CD standards, and different speeds. The programming is accomplished through a serial interface port. Two outputs are provided to support dual- laser multi-standard optical heads. The clock and NRZ inputs can be either standard CMOS or LVDS, selectable through a program bit.

130626.00

Vendor:HARRISPackage Cooled:PLCCD/C:97+

130632-OT46N

Vendor:eupec

Vcc = 5.0V10%, TA = 0C to 70C, unless otherwise specified. -15 # SymbolParameter Min Max READ CYCLE 1TRCRead Cycle Time15- 2TAAAddress Access Time-15 3TACSChip Select Access Time-15 4TOEOutput Enable to Output Valid-7 5TCLZChip Select to Output in Low Z3- 6TOLZOutput Enable to Output in Low Z3- 7TCHZChip Deselecting to Output in High Z08 8TOHZ Out Disable to Output in High Z08 9TOHO...

130667

130668

Single Voltage, Range 3V to 3.6V Supply 3-Volt-Only Read and Write Operation Software Protected Programming Fast Read Access Time - 150 ns Low Power Dissipation 15 mA Active Current 50 µA CMOS Standby Current Sector Program Operation Single Cycle Reprogram (Erase and Program) 512 Sectors (128 words/sector) Internal Address and Data Latches for 128 Words Fast Sector Program Cycle Time - 20 m...

13066T

Vendor:HARRISD/C:O9+

13066T

Vendor:HARRISD/C:O9+

130672

130672

1306F-1R0L-B026

Vendor:FRONTIERD/C:24000

The filter is followed by a base-band amplifier which boosts the de- tected signal to the BBOUT pin. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak signal level are proportionately less. The detected signal is riding on a 1.1 Vdc level that ...

1307/

Package Cooled:TSSOP

Chrontels CH7004 digital PC to TV encoder is a stand- alone integrated circuit which provides a PC 99 compliant solution for TV output. It provides a universal digital input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts this directly into NTSC or PAL TV format. This circuit integrates a digital NTSC/PAL encoder with 9-bit DAC interface, and new adapt...

130700A

Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations

130700A

Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations

13070-2M-50-15

Vendor:TTEPackage Cooled:MODULE

In the receive path, the input amplifier sums the signals from the line and hybrid paths to perform first-order analog echo cancel- lation. The resultant signal is then digitized by a fourth-order cascaded delta-sigma A/D converter with an OSR (OverSampling Ratio) of 24x. The subsequent oversampled

130721

Vendor:HARPackage Cooled:PLCC44D/C:N/A

SUPPLY VOLTAGE C VDD = 1.7V to 2.0V for program, erase and read C VDDQ = 1.7V to 2.0V for I/O Buffers C VPP = 9V for fast program (12V tolerant) SYNCHRONOUS / ASYNCHRONOUS READ C Synchronous Burst Read mode: 54MHz C Asynchronous Page Read mode C Random Access: 85ns SYNCHRONOUS BURST READ SUSPEND PROGRAMMING TIME C 10µs typical Word program time using Buffer Program MEMORY ORGANIZATION...

130721.00

Vendor:HARRISPackage Cooled:PLCCD/C:97+

130725

Vendor:HARRISPackage Cooled:PLCCD/C:08+

Notes: (i) For operation below 0 C the external capacitors m ust bave stable characteristics. use either a low ESR tantalum, Os-Con, or ceramic capacitor. (ii) During reflow of SMD package version do not elevate peak temperature of the module, pins or internal components above the stated maximum.

130726(145-044)

Vendor:HARRISPackage Cooled:PLCCD/C:08+

The MAX3873 successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxims continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxims quality and reliability standards.

130732

Vendor:QFPD/C:97+

Note 6: The limits are based on bench characterization of the devices jitter response over the power supply voltage range. Output clock jitter is measured with a cycle-to-cycle jitter of 10% at a 1µs rate applied to the transmitters input clock signal (CLKIN) while data inputs are switching with internal PRBS generator enabled without DC-Balance. The typical data is measured with a cycle-to-cycle jitt...

130742

High CTRCE(SAT) comparable to Darlingtons CTR guaranteed 0C to 70C High common mode transient rejection 5kV/µs Data rates up to 150 kbits/s (NRZ) Underwriters Laboratory (UL) recognized (file #E90700) VDE recognized (file #94766) C Add option 300 (e.g., MCT5211.300)

130743

Peaking frequency calibration pin. ∗ Controlled with DC voltages of 0 to 5V. High = Peaking frequency increased Low = Peaking frequency reduced ∗ Leave this pin open when not using the peaking frequency calibration function.

130743.00

Vendor:INTEYSILPackage Cooled:DIPD/C:00+

130746(TC102HV1)

Vendor:HARRISPackage Cooled:PLCCD/C:08+

AC CHARACTERISTICS PARAMETER DQM to input data delay WRITE command to input data delay Data-in to ACTIVATE command w/ Auto precharge Data-in to precharge Last data-in to precharge command LOAD MODE REGISTER command to command Data-out to high impedance from precharge

130746(TC102HV1)

Vendor:HARRISPackage Cooled:PLCCD/C:08+

AC CHARACTERISTICS PARAMETER DQM to input data delay WRITE command to input data delay Data-in to ACTIVATE command w/ Auto precharge Data-in to precharge Last data-in to precharge command LOAD MODE REGISTER command to command Data-out to high impedance from precharge

130746.00

Vendor:HARRISPackage Cooled:PLCCD/C:97+

1307Z

Vendor:DSPackage Cooled:SMDD/C:064+

A separate 6-bit control register (WCR) independently controls the wiper tap position for each DPP. Associated with each wiper control register are four 6-bit non- volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a 2-wire serial bus (I2C-like). On power-up, the contents of the

130-8233-2001

Vendor:SECONPackage Cooled:ModuleD/C:00+

130851-E

1308B

Vendor:LTPackage Cooled:SOIC8D/C:04+

130AR25T150DT

Isense (Current Sense) The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the external Power Switch. When Isense reaches the internal threshold of the Current Limit Comparator, the Driver output is disabled. By this mean the Over Current Detection is realized. Furthermore the current information is provided for the PWM-Comparator to realize the Curren...

130D601R05

130E3P/R61060

Vendor:TIPackage Cooled:00+D/C:DIP-8

There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with e...

130E3P/R61060

Vendor:TIPackage Cooled:00+D/C:DIP-8

There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with e...

130F-108-422

130F120

Package Cooled:SANREX

202 or CCITT V.23 FSK format and transmitted at 1200 baud from the serving end office to the subscribers terminal. Additionally in off-hook signalling, the special dual tone CAS is used to alert the terminal before FSK data transmission. BT uses CAS to alert the terminal prior to FSK in both on- hook (Idle State) and off-hook (Loop State) signalling.

130F160

Package Cooled:SANREX

High current sink/source 25 mA/25 mA Up to 47 I/O pins with individual direction control Three external interrupt pins Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler Timer1 module: 16-bit timer/counter (time-base for CCP) Timer2 module: 8-bit timer/counter with 8-bit period register Timer3 module: 16-bit timer/counter Secondary oscillator clock option - Timer1/Timer3 ...