Index "1"NOTES 1Tester measures code transitions by dithering the voltage of the analog input (VIN). The difference between the measured and the ideal code width is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage 2Guaranteed. Not tested. 3All channel input pins and ground reference pin have protection which becomes active above 60 V. 4All digital ...
Vendor:AMIPackage Cooled:30D/C:N/A
• Low output noise = 4.0nA/rt-Hz • High-performance laser diode driver • Pin compatible with EL6257 • Voltage-controlled output current source to 150 mA per channel, requiring one external set resistor per channel • Current-controlled output current source to 150 mA per channel • Rise time = 1.0 ns • Fall time = 1.1 ns • On chip oscillator with freque...
Vendor:LTPackage Cooled:SOIC8D/C:04+
Vendor:ALCATELPackage Cooled:TQFP100D/C:03+
Package Cooled:BGAD/C:06+
Package Cooled:晶振
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OEAB should be tied to VCC through a pullup resistor and OEAB and OEBA should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
Vendor:ALCATELPackage Cooled:TQFP100D/C:03+
Vendor:N/APackage Cooled:30D/C:N/A
Vendor:N/APackage Cooled:30D/C:N/A
Package Cooled:SOPJ20D/C:2007+
SDA is a bidirectional pin used to transfer addresses, data or control information into the device or to transfer data out of the device. The output is open drain, performing a wired AND function with any number of other open drain or open collector devices. The SDA bus requires a pull-up resistor to VCC.
Package Cooled:SOPJ20D/C:2007+
Vendor:HARPackage Cooled:TO-39D/C:NULL
Package Cooled:07+D/C:4941
4.4.3 Group C inspection. Group C inspection shall be conducted in accordance with the conditions specified for subgroup testing in appendix E, table VII of MIL-PRF-19500. Electrical measurements (end points) and delta requirements shall be in accordance with the applicable steps of table III herein.
The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 15MHz bandwidth. The 68dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source.
Vendor:n/aPackage Cooled:SOP8D/C:5
The standard device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus conten- tion the device contains separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Package Cooled:YAGEO
D/C:08+
In addition to having the same functions as port P1, these pins function as input pins for INT1 to INT3 and INT5 to INT7. Also, pins P55 to P57 function as input pins for timers B0 to B2 and as input pins for position data in the three-phase waveform mode; and pins P52 and P53 function as trigger-input pins in the pulse output port mode.
D/C:08+
In addition to having the same functions as port P1, these pins function as input pins for INT1 to INT3 and INT5 to INT7. Also, pins P55 to P57 function as input pins for timers B0 to B2 and as input pins for position data in the three-phase waveform mode; and pins P52 and P53 function as trigger-input pins in the pulse output port mode.
Vendor:SENSYMD/C:2001+
In the 10-bit mode the 8b/10b Codec is disabled, and the externally encoded data are latched in the DDR input registers in increments of 10 bits. In this case, the user is responsible for generating and applying the proper input in the form of ordered sets, data, and correct comma group signals, to ensure data coherence. The LSB (TDX[0]) is shifted out first on the serial side, and the MSB (TDX[9]) is shifte...
D/C:08+
• Available on Both Encoder Modules (HEDS-9000 Series) and Encoder Kit Housing (HEDS-5500 Series) • Complementary Outputs • Industry Standard Line Driver IC • Single 5 V Supply • Onboard Bypass Capacitor • 70C and 100C Versions Available
D/C:08+
• Available on Both Encoder Modules (HEDS-9000 Series) and Encoder Kit Housing (HEDS-5500 Series) • Complementary Outputs • Industry Standard Line Driver IC • Single 5 V Supply • Onboard Bypass Capacitor • 70C and 100C Versions Available
Vendor:AD
Vendor:JATPackage Cooled:SOTD/C:05+
Requires few external parts Low distortion (total harmonic distortion = 0.01% at 3 W) Low noise (at Rg = 620 Ω, noise is 0.15 mV (muting off) or 0.1 mV (muting on)) Popping noise minimized Highly reliable current-limiting ASO protector keeps speakers safe from all kinds of trouble. Reliability is further enhanced by a fast-acting thermal shutdown protection circuit with on/off hysteresis.
D/C:08+
Package Cooled:SOP44WD/C:2007+
4. Oscillator Stability In some cases, parasitic oscillations may be induced by the PCB layout. This oscillation can be eliminated by adding the components listed below. Note that the optimal capacitor value must be verified by testing in the actual mounted state in the end product. • Connect a capacitor and resistor (0.1µF and 2.2Ω) in series between each output pin and ground.
The Intersil SLIC incorporates many of the BORSHT functions on a single IC chip. This includes DC battery feed, a ring relay driver, supervisory and hybrid functions. This device is designed to maintain transmission performance in the presence of externally induced longitudinal currents. Using the unique Intersil dielectric isolation process, the SLIC can operate directly with a wide range of station b...
D/C:07+
Vendor:AMERICAN PRECISION INDD/C:9722+
signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-21365/6 con- tain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce over- head, increase performance, and simplify implementation. Circular buffers can start and end a...
Vendor:PROMINETPackage Cooled:QFP208D/C:99+
Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the ICS660 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation.
Vendor:PROMINETPackage Cooled:QFP208D/C:99+
Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the ICS660 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation.
Vendor:PHILIPSPackage Cooled:TSSOPD/C:N/A
2.4V TO 3.6V SINGLE SUPPLY OPERATION 0.5mg RESOLUTION OVER 100Hz BW 2g/6g USER SELECTABLE FULL-SCALE OUTPUT VOLTAGE, OFFSET AND SENSITIVITY RATIOMETRIC TO THE SUPPLY VOLTAGE FACTORY TRIMMED DEVICE SENSITIVITY AND OFFSET EMBEDDED SELF TEST HIGH SHOCK SURVIVABILITY
Vendor:PHILIPSPackage Cooled:TSSOPD/C:N/A
2.4V TO 3.6V SINGLE SUPPLY OPERATION 0.5mg RESOLUTION OVER 100Hz BW 2g/6g USER SELECTABLE FULL-SCALE OUTPUT VOLTAGE, OFFSET AND SENSITIVITY RATIOMETRIC TO THE SUPPLY VOLTAGE FACTORY TRIMMED DEVICE SENSITIVITY AND OFFSET EMBEDDED SELF TEST HIGH SHOCK SURVIVABILITY
The STTH60L06, which is using ST Turbo 2 600V technology, is specially suited for use in switching power supplies, and industrial applications, as rectification and discontinuous mode PFC boost diode. Thanks to its low VF characteristics, this device exhibits high performances in free- wheeling applications.
Vendor:PHIPackage Cooled:TSOP16D/C:2007+
Use for maximum MOSFET junction temperature calculations. Use for overall efficiency and dissipation calculations. Typical parameters are representative of actual device performance but are for reference only. Parameter is 100% tested on production devices. All other parameters are guaranteed.
Package Cooled:CDIP14D/C:2007+
Vendor:PLCCPackage Cooled:LUCENTD/C:2004+
Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. VDD = 5 V. 2Package Power Dissipation = (TJ max C TA) / JA
Vendor:LUCENTPackage Cooled:PLCCD/C:98+
Vendor:AMP/TYCOD/C:0228
Vendor:TycoPackage Cooled:连接器D/C:2000pcs
Suffix denotes Vz tolerance: non suffix for 20%, A suffix for 10%. Measures with 10%, 60 Hz AC superimposed on Izt. Measured from 1000 to 3000 Hz. Difference between Vz at Izt and IzL. VF @ 200mA = 1.2V Max. Power rating is 400 mW @ 25C, derate linearly to zero @ 175C Package StyleDO-7
Vendor:FREESCALEPackage Cooled:MLP-S40PD/C:06+
Vendor:FREESCALEPackage Cooled:MLP-S40PD/C:06+
Program Store-Enable Output, Active Low. This signal is commonly connected to external ROM memory as a chip enable. PSEN provides an active-low pulse width of 2.25 XTAL1 cycles with a period of four XTAL1 cycles. PSEN is driven high when data memory (RAM) is being accessed through the bus and during a reset condition.
Vendor:AMP/TYCOD/C:0421
Minimizes Distortion and Error Voltages On-Resistance Matching Channels, 0.8Ω typ On-Resistance Flatness, 3Ω typ Low Charge Injection Reduces Glitch Errors. Q = 4pC typ Replaces Mechanical Relays High Speed. tON= 10ns typ Low Off-Isolation: -72dB@1MHz Wide -3dB Bandwidth: 170 MHz High-Current Channel Capability: >100mA TTL/CMOS Logic Compatible Low Power Consumption (0.5µW typ) P...
The 74HC/HCT377 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.
Unless otherwise noted, these specifications apply for V+ = 2.65V to 3.6V for the LM74CIBP -3, V+ = 3.0V to 3.6V for the LM74CIM -3 and V+ = 4.5V to 5.5V for the LM74 -5 (Note 6). Boldface limits apply for TA = TJ = TMIN to TMAX; all other lim- its TA = TJ =+25˚C, unless otherwise noted.
Vendor:TYCOPackage Cooled:05+D/C:240
No Connection A logic I/O port. External encode clock input or internal data clock output. Clock frequency is dependent upon Clock Mode 1, 2 inputs and Xtal frequency (see Clock Mode pins). The encoder digital output. This is a three-state output whose condition is set by the Data Enable and Powersave inputs. See Table 2. When this pin is at a logical 0 the encoder is forced to an idle state and the ...
Vendor:TYCO
Package Cooled:PQFP44D/C:2007+
Vendor:FUJPackage Cooled:MQFPD/C:06+
VBIAS (VCC, VBS1,2,3) = 15V, VS0,1,2,3 = VSS and TA = 25C unless otherwise specified. The VIN, VTH and I IN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3 . The VO and IO parameters are referenced to VS0,1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Vendor:AMIPackage Cooled:30D/C:N/A
The wide operating supply range and high accuracy make the LTC6101 ideal for a large array of applications from automotive to industrial and power management. A maxi- mum input sense voltage of 500mV allows a wide range of currents to be monitored. The fast response makes the LTC6101 the perfect choice for load current warnings and shutoff protection control. With very low supply current, the LTC6101 is suit...
Vendor:FUJITSUPackage Cooled:QFPD/C:1999
Fujitsu resonators C4 series (G type) feature originally developed single crystals with a high electromechanical coefficient (LiNbO3 lithium niobate), the result is ultra compact packaging. C4 series (G type) with built-in capacitors for exclusive use in microcomputer clocks, and this series is chip type device for surface-mount.
Vendor:FUJIPackage Cooled:TQFPD/C:2000
The first one is the ROM/SRAM/Flash-style interface that has programmable wait-state timings and includes burst-mode capability, with six chip selects each decoding 256-Mbyte sections of addressable space. For maximum flexibility, each bank can be specified to be 8, 16, or 32 bits wide. This allows the use of 8-bit-wide boot ROM options to minimize over- all system cost. The on-chip boot ROM can be u...
Vendor:FUJIPackage Cooled:TQFPD/C:2000
The first one is the ROM/SRAM/Flash-style interface that has programmable wait-state timings and includes burst-mode capability, with six chip selects each decoding 256-Mbyte sections of addressable space. For maximum flexibility, each bank can be specified to be 8, 16, or 32 bits wide. This allows the use of 8-bit-wide boot ROM options to minimize over- all system cost. The on-chip boot ROM can be u...
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?72417.
Vendor:FUJPackage Cooled:N/AD/C:2002
The 576Mbit RDRAM devices are extremely high-speed CMOS DRAMs organized as 32M words by 18 bits. The use of Rambus Signaling Level (RSL) technology permits up to 1200 MHz transfer rates while using conventional system and board design technologies. RDRAM devices are capable of sustained data transfers up to 0.833ns per two bytes (6.7ns per sixteen bytes).
Vendor:FUJPackage Cooled:N/AD/C:2002
The 576Mbit RDRAM devices are extremely high-speed CMOS DRAMs organized as 32M words by 18 bits. The use of Rambus Signaling Level (RSL) technology permits up to 1200 MHz transfer rates while using conventional system and board design technologies. RDRAM devices are capable of sustained data transfers up to 0.833ns per two bytes (6.7ns per sixteen bytes).
Package Cooled:SHENHE
Package Cooled:SHENHE
Vendor:ERICSSONPackage Cooled:SOPD/C:2007+
Make connection to B side with pink wire for Light ON Make connection to v side with pink wire for Dark ON Note: When switching a power source, make ground connection to the frame ground termi- nal or to the ground terminal. This will assure more stable operation.
Vendor:MOTPackage Cooled:TSSOPD/C:97+
Vendor:5600
This document describes part-number-specific changes to recommended operating conditions and revised electrical specifications, as applicable, from those described in the general MPC7455 RISC Microprocessor Hardware Specifications (Order No. MPC7455EC). The MPC7455 is a PowerPC™ microprocessor.
Vendor:JRCPackage Cooled:08+D/C:800
D/C:94
DESCRIPTION The M74HC4020 is an high speed CMOS 14 STAGE BINARY COUNTER fabricated with silicon gate C2MOS technology. A clear input is used to reset the counter to the all low level state. A high level on CLEAR accomplishes the reset function. A negative transition on the CLOCK input increments the counter by one.
Vendor:N/APackage Cooled:PLCCD/C:0212+
Vendor:RCAPackage Cooled:04+D/C:DIP-8
CT - This is the oscillator timing pin. The free-running frequency can be set by connecting a timing capacitor to this pin. The oscillator produces a sawtooth waveform with a programmable frequency range of 100kHz to 1.2MHz. Figure 4 may be used as a guideline in selecting the capacitor value required for a given frequency.
Vendor:RCAPackage Cooled:04+D/C:DIP-8
CT - This is the oscillator timing pin. The free-running frequency can be set by connecting a timing capacitor to this pin. The oscillator produces a sawtooth waveform with a programmable frequency range of 100kHz to 1.2MHz. Figure 4 may be used as a guideline in selecting the capacitor value required for a given frequency.
Vendor:5600
When the voltage drop to the positive input of the com- parator (i,e,VB) is higher than VREF, VOUT goes high, M1 turns off, and VB is expressed as VBH=VDD ´ (RB+RC) / (RA+RB+RC). If VDD is decreased so that VB falls to a value less than VREF, the comparator output in- verts from high to low, VOUT goes low, VC is high, M1 turns on, RC is bypassed, and V B becomes: VBL=VDD´RB / (RA+RB), which...
Vendor:5600
When the voltage drop to the positive input of the com- parator (i,e,VB) is higher than VREF, VOUT goes high, M1 turns off, and VB is expressed as VBH=VDD ´ (RB+RC) / (RA+RB+RC). If VDD is decreased so that VB falls to a value less than VREF, the comparator output in- verts from high to low, VOUT goes low, VC is high, M1 turns on, RC is bypassed, and V B becomes: VBL=VDD´RB / (RA+RB), which...
Vendor:MOTOROLAPackage Cooled:功放Power moduleD/C:92+
Ruotare il selettore su OS . Quando lalimentazione a ON e si applica il segnale di start tra i ter- minali A1 e B1, inizia il conteggio e luscita va subito a ON per la durata del tempo impostato. Luscita torna allo stato iniziale a fine conteggio o se viene tolta lalimentazione.
Vendor:5600
Input offset voltage is trimmed to less than 60µV. The low drift and excellent long-term stability guarantee a high accuracy over temperature and time. The 300pA maxi- mum input bias current and 120dB minimum voltage gain further maintain this precision over operating conditions.
Vendor:5600
Notes 11. Output Fault Detect Thresholds with outputs programmed OFF. Output Fault Detect Thresholds are the same for output open and shorts. 12. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded to be OFF. 13. This parameter is guaranteed by design but not product...
Vendor:5600
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.