202A33EW

202AT-2

Vendor:120

202AT-2

Vendor:120

202BDSC-27

202CBNZ

Vendor:ICPackage Cooled:SOPD/C:0544+

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

202-DSPGAT-000

Vendor:CYPRESSPackage Cooled:PLCCD/C:08+

Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Zero Gate Voltage Drain Current Static Drain-to-Source ➃ On-State Resistance (TO-3) Static Drain-to-Source ➃ On-State Resistance (SMD-1) Diode Forward Voltage ➃

202ECBNZ

Vendor:ICPackage Cooled:SOPD/C:0544+

Secondary-side control assumes that output voltage and current measurements are interfaced directly to an output ground-referenced PWM stage that develops the power switch command for the supply. This digital PWM command can then be transmitted to the primary-side power switch through a simple and low-cost isolating pulse transformer. With secondary-side control, it is much easier to monitor and control t...

202F DABU

Package Cooled:TSSOP

202FDABU

202K132-25

202R18N150JV4E

Vendor:JOHANSOND/C:04+

Phase-Lock Loop Clock Distribution 10MHz to 200MHz operating frequency Distributes one clock input to one bank of five outputs Zero Input-Output Delay Output Skew < 250ps Low jitter <200 ps cycle-to-cycle 202R18N150JV4E-1 for Standard Drive 202R18N150JV4E-1H for High Drive No external RC network required Operates at 3.3V VDD Power down mode Spread spectrum compatible Available in SOIC package

202R18N271JV4E

Vendor:JOHANSONPackage Cooled:1206-271J 2KV

202R18N330KV4E

Vendor:JOHANSOND/C:12000

202R18N680JV4E

D/C:8140

Model WS81. The WS81 donut shaped 100 ohm RTD element offers fast, accurate temperature measurement as well as a convenient means of attaching to a surface without cement. These highly versatile units can be secured to a surface by a machine screw and washer or by a rivet. They can also be directly cemented with or without the use of a vertical centering post. Rated temperature is from -50 to ...

202R18N820JV4E

Vendor:JOHANSOND/C:4500

202R18W102KV4E

Vendor:JOHANSONPackage Cooled:N/AD/C:08+

VREF: The module senses the voltage at this input to regu- late the output voltage, VTT. The voltage at VREF is also the reference voltage for the system bus receiver com- parators. It is normally set to precisely half the bus driver supply voltage (VDDQ 2), using a resistor divider (see standard application). The Thevenin impedance of the network driving the VREF pin should not exceed 500 Ω.

202R18W102KV4E(ROHS)

Vendor:JOHANSOND/C:2890

202R18W102MV4E

Vendor:JOHANSOND/C:279000

202R18W151KV4E

Vendor:JohansonD/C:72000

202R18W221KV4E

D/C:7164

The 202R18W221KV4EA is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of eight D flipCflops with common Clock and Reset inputs. Each flipCflop is loaded with a lowCtoChigh transition of the Clock input. Reset is asynchronous and active low.

202R18W471KV4E

Vendor:JOHANSOND/C:36564

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values ar...

202R18W471KV4E

Vendor:JOHANSOND/C:36564

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values ar...

202R29W102KV4E

Vendor:出口锋华Package Cooled:1808-102D/C:08+

The ZL30414 accepts a CMOS compatible reference at 19.44 MHz and generates four LVPECL differential output clocks at 622.08 MHz, a CML differential clock at 155.52 MHz and a single-ended CMOS clock at 19.44 MHz. The output clocks can be individually enabled or disabled. The ZL30414 provides a LOCK indication.

202R29W102KV4R

202R29W151KV4E

Vendor:JOHANSONPackage Cooled:1808-151K 2KV

On a 2 V supply, the Sx and Sy thresholds are approaching half the supply rail. On a 5V supply their (0.65V) threshold is much closer to GND than usual for logic inputs. This causes some additional delay in the effective propagation time on falling edges, and reduces those delays on the rising edges.

202R29W152KV4E

Vendor:JDID/C:07+

NOTES: 1. Always design to the specified minimum/maximum electrical limits (where applicable). 2. Current Transfer Ratio (CTR) = IC/IF x 100%. 3. For test circuit setup and waveforms, refer to Figure 7. 4, For this test, Pins 1 and 2 are common, and Pins 4 are 5 are common.

202R29W152MV4

Vendor:JOHANSOND/C:1239

202R29W471KV4E

D/C:16000

A wide input voltage range and integrated thermal and overcurrent protection enhance overall system reliability. Reference accuracy and excellent temperature characteristics are provided. A chip-enable input gives the designer complete control over power up, standby, or power down. This device is supplied in a 16-lead surface-mount plastic SOIC with exposed pad to provide a low-resistance path for max...

202R29W471KV4E

D/C:16000

A wide input voltage range and integrated thermal and overcurrent protection enhance overall system reliability. Reference accuracy and excellent temperature characteristics are provided. A chip-enable input gives the designer complete control over power up, standby, or power down. This device is supplied in a 16-lead surface-mount plastic SOIC with exposed pad to provide a low-resistance path for max...

202S41W102KV4E

Vendor:JOHANSONPackage Cooled:N/AD/C:08+

202S41W272KV4E

202S43W102KV4E

Vendor:JOHANSOND/C:3000

Notes: 5. Distribution data sample size is 500 samples taken from 5 different wafers and 3 different lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 6. Measurements are made on production test board, which represents a trade-off between optimal OIP3, NF and VSWR. Circuit losses have been de-embedded from actual measurements.

202S43W102KV4E

Vendor:JOHANSOND/C:3000

Notes: 5. Distribution data sample size is 500 samples taken from 5 different wafers and 3 different lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 6. Measurements are made on production test board, which represents a trade-off between optimal OIP3, NF and VSWR. Circuit losses have been de-embedded from actual measurements.

202S43W272KV6E

202S43W471KV4E

Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

202S43W472MV4E

Vendor:JOHANSONPackage Cooled:1812-472M 2KV

203001

20300255125V25AF

20302

Package Cooled:99D/C:2352

The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).

203-02320

203036-1

Vendor:AMP/TYCOD/C:N/A

20306

D/C:08+/09+

Data Output Bit 10 Data Output Bit9 Data Output Bit 8 Data Output Bit 7 Data Output Bit 6 Data Output Bit 5 Data Output Bit 4 Data Output Bit 3 Data Output Bit 2 Data Output Bit 1 Data Output Bit 0 Analog Power Supply Analog Power Supply Analog Ground (Substrate) Red Positive Analog Input

2030M

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible wit...

2030M

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible wit...

2030SMTDK

D/C:3042

Q and Q outputs. This device can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respec...

2030W0ZTQD

2030WOZBQ1

Vendor:INTELD/C:05+

The HCT245 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

2030WOZBQ1

Vendor:INTELD/C:05+

The HCT245 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

2030WOZTQ2

2031005EKSWA2BM

D/C:07+

NOTES: 1. All test data is referenced to 25C ambient. 2. Operating Temperature Range - 55C to + 125C 3. DC current (A) that will cause an approximate ∆T of 40C. 4. DC current (A) that will cause Lo to drop approximately 20% 5. The part temperature (ambient + temp rise) should not exceed 125C under worst case operating conditions. Circuit design, component placement, PWB trace size and thicknes...

203-103

203-11-1-66-752-L-1

Vendor:ＮＸＰ

2031-5002-00

Vendor:MA/COMMPackage Cooled:n/aD/C:97

2031-5002-02

2031-5006-00

(5) When designing your equipment, comply with the guaranteed values, in particular those of maxi- mum rating, the range of operating power supply voltage and heat radiation characteristics. Other- wise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may n...

2031579-00

Vendor:EPSOND/C:99+

2031A

Vendor:N/APackage Cooled:50D/C:N/A

This pin provides an access to the output current control loop for the NCP5009 version. The current sunk to ground from this pin is subtracted from the output current mirror. Primary use is the ambient light automatic adjustment by means of an external photo transistor connected across this pin and ground. The output current decreases as the ambient light increases. The internal circuit provides a 1/1 cur...

20320

D/C:96

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4,000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADR380/ADR381 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avo...

2032-110LJ

Vendor:.Package Cooled:2005D/C:500

The ADR512 is a 1.2 V precision shunt voltage reference. It is designed to operate without an external output capacitor be- tween the positive and negative terminals for stability. An external capacitor can be used for additional filtering of the supply.

2032135LJ

203-2-1-65-751-4-1-13

Vendor:AIRPAXD/C:9112

2032-16TS

203-22-1-62F-252-4-3-1

2032-80/135IJ

2032-80LJ

Vendor:LATTICEPackage Cooled:PLCC

Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Unless otherwise noted, all voltages are referenced to GND. The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of -55C to +125C. For TC = +100C to +125C, derate li...

2032A/B

Vendor:PHIPackage Cooled:30D/C:N/A

This device assumes a standby mode if either CE1 is disabled (high) or CE2 is disabled (low). It will also automatically go into a standby mode whenever all input signals are quiescent (not toggling) regardless of the state of CE1 or CE2. In order to achieve low standby current in the enabled mode (CE1 low and CE2 high), all inputs must be within 0.2 volts of either V CC or V SS .

2032A8ISPLSI0LJ44

Vendor:LATTPackage Cooled:PLCCD/C:2000+

2032B/A

2032E-110LT44

Vendor:1200

When the device is operating as a timing master, the internal digital PLL is in use. In this mode, an external 20.000 MHz crystal is required for the on-chip crystal oscillator. The DPLL is phase-locked to one of four input reference signals (which can be 8 kHz, 1.544, 2.048, 4.096, 8.192, 16.384 or 19.44 MHz provided on REF0 - 3). The on-chip DPLL operates in normal, holdover or freerun mode and offers jitt...

2032ISOLT44

Vendor:ISPLSIPackage Cooled:QFPD/C:N/A

203-2X18TS

20332

Package Cooled:SOP8D/C:802

203442H

2034-5004-28

203489

Vendor:RAYPackage Cooled:TO3D/C:76+

2035-30-B5LF(ROHS)

Vendor:BOURNSD/C:6210

203557C

2035-602

203583

2035D

Package Cooled:DIPD/C:03+

Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply Rejection test. Tested for the 10V (MAX196) and 4.096V (MAX198) input ranges. External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB. Ground on channel; sine wave applied to all off channels. Maximum full-power input frequency for 1LSB error with 10ns j...

2036.0/1-10

20360-001

(known as dioxin) < 2 ppb. In the lists themselves, details of content and composition are separated into the individual parts of the semiconductor component. The most important of these are: Active element: The active element is either a silicon chip or, for optoelectronic components, a chip con- taining combinations of Ga (Al) (As, P). These are doped with very small amounts of boron, arsenic, p...

2036-30-B3

2036T

On Board 24Mhz Crystal Driver Circuit Can be clocked by 48MHz external source On-Chip 1.8V Regulator for Low Power Core Operation Internal PLL for 480Mhz USB2.0 Sampling, Configurable MCU clock Supports firmware upgrade via USB bus if boot block Flash program memory is used 15 GPIOs for special function use: LED indicators, button inputs, power control to memory devices, etc.

2036T

On Board 24Mhz Crystal Driver Circuit Can be clocked by 48MHz external source On-Chip 1.8V Regulator for Low Power Core Operation Internal PLL for 480Mhz USB2.0 Sampling, Configurable MCU clock Supports firmware upgrade via USB bus if boot block Flash program memory is used 15 GPIOs for special function use: LED indicators, button inputs, power control to memory devices, etc.

2037-20-B5/2037-20-A

2037-5006-00

COMP and FB are the available external pins of the PWM converter error amplifier. The FB pin is the inverting input of the error amplifier. Similarly, the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter.

20378009-92

20-37801

Vendor:STPackage Cooled:SOPD/C:N/A

The ADC104S101 operates with a single supply, that can range from +2.7V to +5.25V. Normal power consumption using a +3V or +5V supply is 3.9 mW and 11.4 mW, respec- tively. The power-down feature reduces the power consump- tion to just 0.12 µW using a +3.6V supply, or 0.47 µW using a +5.5V supply. The ADC104S101 is packaged in a 10-lead MSOP package. Operation over the industrial temperat...

2037AC

indicating an overcurrent fault condition has been detected at VOUT. There is a built-in 10msec (min.) fault blanking delay after the overcurrent fault condition has been detected, before this output becomes active low. The OC# output deasserts only when both the overcurrent condition stops and when the voltage drop across the switch is less than 1V. An external pull-up resistor of 10k - 100k is required if...

2037B2

Vendor:InfineonPackage Cooled:QFN

• Low Dropout Voltage 1.2V at 1.2A • Adjustable or Fixed Voltage (1.8V, 2.5V, 3.3V, 5V) • Over Current Protection • Thermal Overload Protection • Maximum Line Regulation 0.45% • Maximum Load Regulation 0.4% • Adjust Pin Current Less Than 90 uA

2037B2

Vendor:InfineonPackage Cooled:QFN

• Low Dropout Voltage 1.2V at 1.2A • Adjustable or Fixed Voltage (1.8V, 2.5V, 3.3V, 5V) • Over Current Protection • Thermal Overload Protection • Maximum Line Regulation 0.45% • Maximum Load Regulation 0.4% • Adjust Pin Current Less Than 90 uA

2037C

input to the slot identification and enables the STA111 for subsequent scan operations. The Local Scan Port Network (LSPN) contains multiplexing logic used to select different port configurations. The LSPN control block contains the Local Scan Port Controllers (LSPC) for each Local Scan Port (LSP0, LSP1 ... LSPn). This control block receives input from the STA111 instruction register, mode registers, a...

2037I

Vendor:TIPackage Cooled:SOP-8D/C:08+

After the output signal has been recorded, the floating capacitor is discharged ("reset", "clamped", "dumped") and made ready to accept charge from the next pixel. This is when the problems begin. (This is a somewhat oversimplified explanation in that the floating capacitor is not usually "discharged" but, in fact, "recharged" to some predetermined dc vo...

203839-2

20383REV.B

20-391-BLK

203A/NAAU

203A14

The 2.5-V controller senses the output voltage via the SEN_V25 pin. This pin is tied to an internal resistor divider that essentially halves the sensed output voltage and feeds it back to the controller for comparison to the internal bandgap reference.

203CNQ080

Vendor:IRD/C:N/A

The MM54HCT573 MM74HCT573 octal D-type latches and MM54HCT574 MM74HCT574 Octal D-type flip flops ad- vanced silicon-gate CMOS technology which provides the inherent benefits of low power consumption and wide power supply range but are LS-TTL input and output characteristic pin-out compatible The TRI-STATE outputs are capable of driving 15 LS-TTL loads All inputs are protected from damage due to stati...