20SLD ES

Vendor:NSCPackage Cooled:LLPD/C:2003+

20SM10M

20SM3R3M

20SM68MS

20SOWB

Vendor:UNISEMPackage Cooled:SOP20D/C:06+

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

20SOWB

Vendor:UNISEMPackage Cooled:SOP20D/C:06+

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

20SP180M

Vendor:sanyoPackage Cooled:capacitanceD/C:09+

20SPS68M

20SS100M

20SS10M

20SS150M

20SS22M

20SS4R7M

20SVP150M

Vendor:SANYOPackage Cooled:04+D/C:4400

20SVP47M

Vendor:SANYOPackage Cooled:N/AD/C:07+

Passive Aging +85C, 1000Hours, 5% Typical Resistance Change Humidity Aging +85C, 85%R.H., 1000Hours, 5% Typical Resistance Change Thermal Shock: MIL-STD-883C, Method 107G, +125C / -10C, 10 Times, 5% Typical Resistance Change Vibration MIL-STD-883C, Method 2007,1 No Resistance Change

20SVPB15M

20TH OCT

Vendor:LTPackage Cooled:QFN

20THOCT

Notes 1. All voltages referenced to Vss. 2. An initial pause of 100 µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensure. (Vdd and VddQ must be powered-up simultaneously Vss and VssQ must be at the same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. Icc specificati...

20TPP02-A

Vendor:n/aPackage Cooled:SOPD/C:06+

Data Transfer After the address information has been transmitted, data transfer between the bus master and the 20TPP02-A can begin. For a read operation the 20TPP02-A will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the 20TPP02-A will transfer the next sequential byte. If the acknowledge is not sent, the 20TPP02-A will end the read operation....

20TQ035S

Vendor:IRD/C:06+

The ADM2486 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines and complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E).

20TQ040

Vendor:IRD/C:06+

In addition, several other facilities are provided to ease system testing. Loop-back of the serial signals is available under external pin or MII control. Suitable control and status registers are available through the IEEE standard MDIO/MDC system. If the Built-in-Self-Test function (BIST) is in use, the serial TX data instead is derived from a PRBS 2^23 -1 pattern generator. In this BIST mode, the received ...

20TQ040S

Vendor:IRD/C:06+

Six and eight channels of EMI filtering Utilizes Praetorian™ inductor-based design tech- nology for true L-C filter implementation OptiGuard™ coating for improved reliability 15kV ESD protection on each channel (IEC 61000-4-2 Level 4, contact discharge) 30kV ESD protection on each channel (HBM) Better than 40dB of attenuation at 1GHz Chip Scale Package features extremely low lead inducta...

20TQ045 TO-220AC

Vendor:TO220ACPackage Cooled:IR

20TQ045PBF

Vendor:N/APackage Cooled:N/AD/C:08+09+

Hynix HYMD116M645A(L)6-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous oper- ations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pip...

20TQ045PBF

Vendor:N/APackage Cooled:N/AD/C:08+09+

Hynix HYMD116M645A(L)6-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous oper- ations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pip...

20TQC15M

20TQC47M

20TSSOP

The CY7C1380D/CY7C1382D SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip En...

20TSSOP

The CY7C1380D/CY7C1382D SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip En...

20TSSOPEP

Vendor:UNTSEMPackage Cooled:TSSOP20D/C:2

For packing material that is returned to us un- sorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the ex- press written approval of ...

20TWP5REV-3

Vendor:N/APackage Cooled:1500D/C:N/A

Hynix HYMD232726A(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD232726A(L)8J-J series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD232726A(L)8J-J series provide a high performance 8-byte interface in 5.25" width form fac...

20TWP5REV-3

Vendor:N/APackage Cooled:1500D/C:N/A

Hynix HYMD232726A(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD232726A(L)8J-J series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD232726A(L)8J-J series provide a high performance 8-byte interface in 5.25" width form fac...

20V/10UF

are included on the CY7C138/9 to handle situations when mul- tiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C138/9 can be utilized as a standalone 8/9-bit dual-port static RAM or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port st...

20V10UF

!Features 1) Each high-performance filter, 6dB amplifier, and 75Ω driver for DVD are incorporated into a single chip. 2) Driver 6ch (Y, C, MIX, and PY, Pb, Pr for progressive) 3) Group delay difference between chroma signal and luminance signal is a small number of nsec. 4) Drive 2 lines of each signal 5) Operating by 5V single power supply 6) Built-in mute circuit

20V2.2UF

Vendor:FUJITSUPackage Cooled:B

Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

20V251

Vendor:n/aPackage Cooled:SOTD/C:97

Note 1: Power dissipation is 500 mW when mounted as recommended. Derate at 4.0 mW/C for operation above 25 C. Gen Note: Exceeding the Absolute Maximum Ratings may damage the device. Gen Note: Parameters with min. or max. values are 100% tested at TA = 25 C. Gen Note: Ripple rejection is @ 60 dB when f = 400 Hz, CL = 10 µF, CN = 0.1 µF, input noise = 100 mVrms, VIN = VOUT(TYP) + 1.5 V and IOUT =...

20V34

The Am30LV0064D is entirely command set compati- ble with industry standard NAND instructions and timing. Commands are written to the command regis- ter through the 8-bit I/O bus using standard NAND write timing. Register contents serve as inputs to an internal state-machine that controls the read, erase, and programming circuitry. Write cycles also internally latch addresses and data needed for the read, pr...

20V6.8UF

Vendor:N/APackage Cooled:D#

20V8H-10

Vendor:PALCEPackage Cooled:PLCCD/C:07+

HPC family core features 16-bit architecture both byte and word operations 16-bit data bus ALU and registers 64 kbytes of direct memory addressing FAST 200 ns for fastest instruction when using 20 0 MHz clock 134 ns at 30 0 MHz High code efficiency most instructions are single byte 16 x 16 multiply and 32 x 16 divide Eight vectored interrupt sources Four 16-bit timer counters with 4 synchron...

20V8H-10

Vendor:PALCEPackage Cooled:PLCCD/C:07+

HPC family core features 16-bit architecture both byte and word operations 16-bit data bus ALU and registers 64 kbytes of direct memory addressing FAST 200 ns for fastest instruction when using 20 0 MHz clock 134 ns at 30 0 MHz High code efficiency most instructions are single byte 16 x 16 multiply and 32 x 16 divide Eight vectored interrupt sources Four 16-bit timer counters with 4 synchron...

20V8H-10JC/4

Package Cooled:PLCCD/C:06+

One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see Table 1). This register is written after the PCA9544A has been addressed. The three LSBs of the control byte are used to determine which channel (or channels) is to be selected. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This en...

20V8H-10JC/4

Package Cooled:PLCCD/C:06+

One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see Table 1). This register is written after the PCA9544A has been addressed. The three LSBs of the control byte are used to determine which channel (or channels) is to be selected. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This en...

20V8H-15JC/4

Vendor:PALCEPackage Cooled:PLCCD/C:96+

DoCD™ Debug Unit C its a real-time hard- ware debugger provides debugging capability of a whole SoC system. In contrast to other on- chip debuggers DoCD™ provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memo- ries, all SFRs including user def...

20V8H-15PC/4

Vendor:AMDPackage Cooled:DIPD/C:N/A

Precision, pulse by pulse phase current match- ing Active drooping allows for best transient response Input Sensing Current mode control Programmable DAC step size/offset allows Compliance with VRM9.0, VRM8.3 or VRM8.4 Externally programmable soft-start 5V or 12V input for next generation processors 0% minimum duty cycle improves transient re- sponse Externally Programmable UVLO with hysteresis Cycle ...

20V8H-25PC

Vendor:PALCED/C:07+

PC0~PC3 constitute a 4-bit bidirectional input/output port with Schmitt trig- Pull-high or None ger input capability. On the port, such can be configured as CMOS output or CMOS or NMOS NMOS input/output with or without pull-high resistor by options.

20V8H-25PC/4

Vendor:300

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability.

20V8H-7JC/5

Vendor:AMDPackage Cooled:PLCC

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, pre- cautions must be taken to avoid applications of any voltage higher than maximum rated volt- ages to this highCimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS(Vin or Vout)VDD. Unused inputs must always be tied to an appropriat...

20V8N-15JC

20V8N-20JC/4

D/C:99

The 20V8N-20JC/4/859 is comprised of three modules that each use a 32-bit internal bus: 20V8N-20JC/4xx core, system integration unit (SIU), and communication processor module (CPM). The 20V8N-20JC/4P block diagram is shown in Figure 1 on page 6. The 20V8N-20JC/4P/859T/859DSL block diagram is shown in Figure 2 on page 7.

20V8Q-15JR/4

Vendor:PLCC-28Package Cooled:PALCED/C:04+

Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required.

20V8Q-25

20VC10P-25

The interrupt controller organizes hardware interrupts coming from individual EUs into a single maskable interrupt, IRQ_B, for the host processor. Multiple internal interrupt sources are logically ORed to create a single, non-prioritized interrupt for the host processor. The controller lets the host read the unmasked interrupt source status as well as the request status of masked interrupt sources, thereby i...

20VLSS10

Vendor:ＶＩＳＨＡＹ

Write Software command accomplishes program and erase operations via the command latch in the device, when high voltage is supplied to VPP. The contents of the latch serve as input to the internal controller. The controller output dictates the function of device. The command latch is written by bringing WE to low level, while CE is at low level and OE is at high level. Addresses are latched on the fall...

20W 0.1 OHM 5 SQP

Package Cooled:HKR

20W256

Vendor:NECD/C:08+

The Hynix HYM71V16C735AT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The Hynix HYM71V16C735AT8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

20WB60

Vendor:SHINDENGEND/C:124

The MSM7716 is a single-channel CODEC CMOS IC for voice signals that contains filters for linear A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, the device is optimized for applications for the analog interfaces of audio signal processing DSPs and digital wireless systems. The analog output signal can directly drive a ceramic type handset receiver. In addit...

20WZ01

Vendor:SHARPPackage Cooled:SOP

20WZ11

Vendor:194Package Cooled:SHARPD/C:N/A

3-Channel CMOS ADC Single 3.3-V Supply 8-Bit 30-MSPS A/D Conversion Very Low Power: <300 mW Typical Differential Linearity Error: < 0.5 LSB Max Integral Linearity Error: < 0.75 LSB Max Analog Input Voltage Range: 1 Vpp Max 64-Pin Thin QFP Package Analog Input Bandwidth: >130 MHz Selectable Clamping Function for YUV or RGB Applications High-Precision Clamp: 0.5 LSB Selectable Output Data Form...

20Y-DZD20Y

Vendor:TOSHIBAPackage Cooled:23-20VD/C:08+

Advanced multi-bit Delta-Sigma architecture 24-bit conversion Supports all audio sample rates including 192 kHz 101 dB Dynamic Range at 5 V -94 dB THD+N High-pass filter to remove DC offsets Analog/digital core supplies from 3.3 V to 5 V Supports logic levels between 1.8 V and 5 V Low-latency digital filter Auto-mode selection Pin compatible with the CS5341

21 624 358-8

21 624 358-8

21.0086.01(A007T07947800UH)

Vendor:/Package Cooled:/D/C:/

21.6MHZ

21.7MQ15A

Vendor:MERCURYD/C:41310

21.855MHZ

Vendor:N/AD/C:N/A

21/2A63V

Vendor:LITTELFU

210.0787.00

Package Cooled:N/AD/C:N/A

210-0003-002

Vendor:HARRISPackage Cooled:CDIP8D/C:00+

• Decodes MPEG2 MP@ML, MPEG1 video bitstreams • Decode DVD, SVCD (D1, 2/3 D1, 1/2 D1), VCD • Supports 720 480 at 30 Hz and 720 576 at 25 Hz • Supports 8 bits YCbCr • On-chip TV, NTSC/PAL, timing generator • DVD sub-picture and highlight processing • Supports SVCD OGT functions • Supports aspect ratios in 16:9 and 4:3 TV, by Pan & Scan and Letter Box con...

210-0008-00

21-00026

11CPDPower Dissipation Capacitance (Note 6)pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the noCload dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.

210-0051-006

The NCP1000 through NCP1002 series of integrated switching regulators, combine a fixed frequency PWM controller with an integrated high voltage power switch circuit. This chip allows for simple design and minimal parts count for very low cost applications which utilize an ac input. This chip is designed to power a single ended topology, typically a discontinuous mode flyback, with secondary side sensin...

210-0051-006

The NCP1000 through NCP1002 series of integrated switching regulators, combine a fixed frequency PWM controller with an integrated high voltage power switch circuit. This chip allows for simple design and minimal parts count for very low cost applications which utilize an ac input. This chip is designed to power a single ended topology, typically a discontinuous mode flyback, with secondary side sensin...

21-00064

• PLL clock distribution optimized for SSTL_2 DDR SDRAM applications. • Distributes one differential clock input pair to five differential clock output pairs. • Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 • Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 • External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input. • Operates at AVDD = 2.5V for core ...

2100-0704

21-00079

Vendor:INTERSILD/C:03+

Over Vin range Measured at center of case, auto-reset Surface temprature of module pins or case Per Bellcore TR-332 50% stress, Ta =40C, ground benign Mil-STD-883D, Method 2002.3 Half Sine, mounted to a fixture Mil-STD-883D, Method 2007.2, 20-2000 Hz, PCB mounted Materials meet UL 94V-0

21001

Vendor:HITPackage Cooled:QFP18

A collision occurs when two or more transmitters simultaneously transmit on the transmission media. A collision is detected by comparing the average DC level of the transmission media to a collision threshold. The received signal at RXI is buffered and sent through a low pass filter, then compared in the collision threshold circuit. If the average DC level exceeds a collision threshold, a 10 MHz sign...

21001

Vendor:HITPackage Cooled:QFP18

A collision occurs when two or more transmitters simultaneously transmit on the transmission media. A collision is detected by comparing the average DC level of the transmission media to a collision threshold. The received signal at RXI is buffered and sent through a low pass filter, then compared in the collision threshold circuit. If the average DC level exceeds a collision threshold, a 10 MHz sign...

2100-12SF1

Vendor:WIESON

2100-1758

2100-1853

2100-1857

21001B

Vendor:SOP-16Package Cooled:ELMOSD/C:2004+

The 21001B is a low cost linear regulator designed to provide a desired output voltage or termination voltage for various applications by converting voltage supplies ranging from 1.6V to 6.0V. The desired output voltage could be programmable by two external voltage divider resistors.

2100-2034

2100-2526

21002558AC

These modes are entered by placing a high voltage VPP on pin 19, with pins 18 and 20 set to VILP. In this state, pin 21 becomes a latch signal, allowing the upper 5 address bits to be latched into an onboard register, pin 22 becomes an active LOW program (PGM) signal and pin 23 becomes an active LOW verify (VFY) signal. Pins 22 and 23 should never be active LOW at the same time. The PROGRAM mode exists when P...

21002559

Vendor:INFINEONPackage Cooled:TQFP144D/C:06+

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. The heat generated must be less than the thermal conductivity from Jun...

2100-29371K

2100-2962

21003210

Vendor:THOMSONPackage Cooled:SSOP

The 80L186EB is the 3V version of the 80C186EB The 80L186EB is functionally identical to the 80C186EBembeddedprocessorCurrent 80C186EB users can easily upgrade their designs to use the 80L186EB and benefit from the reduced power consumption inherent in 3V operation

21-0036

Vendor:INTERSIL

21003P

D/C:08+

The Hynix HYM71V32755AT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The Hynix HYM71V32755AT8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band- width.

21003P

D/C:08+

The Hynix HYM71V32755AT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The Hynix HYM71V32755AT8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band- width.

210-040-064

Vendor:PCSIPackage Cooled:3.9mm

The 210-040-064 powers-up in a low-power idle state; to initiate a temperature measurement and A-to-D conversion, the master must issue a Convert T [44h] command. Following the conversion, the resulting thermal data is stored in the 2-byte temperature register in the scratchpad memory and the 210-040-064 returns to its idle state. The 210-040-064 output data is calibrated in degrees centigrade; for Fahrenhei...

210-040-064

Vendor:PCSIPackage Cooled:3.9mm

The 210-040-064 powers-up in a low-power idle state; to initiate a temperature measurement and A-to-D conversion, the master must issue a Convert T [44h] command. Following the conversion, the resulting thermal data is stored in the 2-byte temperature register in the scratchpad memory and the 210-040-064 returns to its idle state. The 210-040-064 output data is calibrated in degrees centigrade; for Fahrenhei...

21-0043

Vendor:IORPackage Cooled:BGA91D/C:0624+

These diodes are optimized to reduce losses and EMI/ RFI in high frequency power conditioning systems. The softness of the recovery eliminates the need for a snubber in most applications. These devices are ideally suited for HF welding, power converters and other applications where switching losses are not significant portion of the total losses.

21-0043

Vendor:IORPackage Cooled:BGA91D/C:0624+

These diodes are optimized to reduce losses and EMI/ RFI in high frequency power conditioning systems. The softness of the recovery eliminates the need for a snubber in most applications. These devices are ideally suited for HF welding, power converters and other applications where switching losses are not significant portion of the total losses.

21-0043TR

2-100526-0

Vendor:TYCOPackage Cooled:N/AD/C:02+

64Mbit of Flash Memory Page Program (up to 256 Bytes) in 1.4ms (typical) Sector Erase (512Kbit) Bulk Erase (64Mbit) 2.7 to 3.6V Single Supply Voltage SPI Bus Compatible Serial Interface 50MHz Clock Rate (maximum) Electronic Signatures C JEDEC Standard Two-Byte Signature (2017h) C RES Instruction, One-Byte, Signature (16h), for backward compatibility More than 100000 Erase/Program Cycles pe...

210-055

21006505

Vendor:N/APackage Cooled:30D/C:N/A

DESCRIPTION The L4962 is a monolithic power switching regula- tor delivering 1.5A at a voltage variable from 5V to 40V in step down configuration. Features of the device include current limiting, soft start, thermal protection and 0 to 100% duty cycle for continuous operating mode.