2S008

2S010

2S015

2S017

Package Cooled:CAND/C:560

2S018

Package Cooled:CAND/C:550

2S020

Package Cooled:CAND/C:668

2S024

Package Cooled:四方三脚铁帽D/C:08+

2S026

2S032

2S033

Vendor:WPackage Cooled:金属帽D/C:025

VREF: The module senses the voltage at this input to regu- late the output voltage, VTT. The voltage at VREF is also the reference voltage for the system bus receiver com- parators. It is normally set to precisely half the bus driver supply voltage (VDDQ 2), using a resistor divider (see standard application). The Thevenin impedance of the network driving the VREF pin should not exceed 500 Ω.

2S033

Vendor:WPackage Cooled:金属帽D/C:025

VREF: The module senses the voltage at this input to regu- late the output voltage, VTT. The voltage at VREF is also the reference voltage for the system bus receiver com- parators. It is normally set to precisely half the bus driver supply voltage (VDDQ 2), using a resistor divider (see standard application). The Thevenin impedance of the network driving the VREF pin should not exceed 500 Ω.

2S043

2S044

2S046

2S050

2S051

2S062

2S070

2S071

2S074

2S078

2S082

2S083

2S084

2S0880R

Vendor:FAIRCHILDPackage Cooled:08+D/C:2000

Notes: 1. Resistor value 1.5KΩ is recommended, but may be greater for slower two-wire speed. 2. VDD and VAA supplies must be at same potential to avoid excess current draw. Care must be taken to avoid noise injection in the analog supply is cases where a single supply is used.

2S093

2S094

2S095

2S096

2S09655

Vendor:SEC

One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency SCOPE Instruction Set C IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ C Parallel-Signature Analysis at Inputs C Pseudo-Random Pattern Generation From Outputs C Sample Inputs/Toggle Outputs C Binary Count From Outputs C Device Identification C Even-Parity Opcodes Packaged in 64-Pin Plastic Thin Quad F...

2S09655

Vendor:SEC

One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency SCOPE Instruction Set C IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ C Parallel-Signature Analysis at Inputs C Pseudo-Random Pattern Generation From Outputs C Sample Inputs/Toggle Outputs C Binary Count From Outputs C Device Identification C Even-Parity Opcodes Packaged in 64-Pin Plastic Thin Quad F...

2S0965R

Vendor:FAIPackage Cooled:N/AD/C:TO-3 P P5

2S098

2S100

Vendor:TID/C:07+/08+

Edition Jun. 2002 This edition was realized using the software system FrameMakerâ. Published by Infineon Technologies, Marketing-Kommunikation, Balanstraße 73, 81541 Mnchen © Infineon Technologies 6/30/2002. All Rights Reserved.

2S101

Package Cooled:CAND/C:668

Widerstandswert bei der Temperatur T Widerstandswert am Beginn des betreffenden Temperaturintervalls Temperatur in C am Beginn des betreffenden Temperaturintervalls Interessierende Temperatur in C (Tx < T < Tx+1) Temperaturkoeffizient bei der Temperatur Tx

2S102

Package Cooled:CAND/C:560

Temperature Error Using Remote Diode of 0.13 micron Pentium 4 with typical non-ideality of 1.0021 and series R= 3.64Ω. For other processors email hardware.monitor.team@nsc.com to obtain the latest data. (TD is the Remote Diode Junction Temperature)

2S103

Package Cooled:CAND/C:689

o 8-Channel Single-Ended or 4-Channel Differential Inputs o Single +5V or 5V Operation o Low Power: 1.5mA (operating mode) 2µA (power-down mode) o Internal Track/Hold, 133kHz Sampling Rate o Internal 4.096V Reference (MAX186) o SPI-, QSPI-, Microwire-, TMS320-Compatible 4-Wire Serial Interface o Software-Configurable Unipolar or Bipolar Inputs o 20-Pin DIP, SO, SSOP Packages o Evaluation...

2S105

Package Cooled:CAND/C:557

Array Description The X9269 is comprised of a resistor array (see Figure 1). Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs).

2S106

Package Cooled:CAND/C:625

The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays The TFP401 and TFP401A are compliant to the DVI Specification Rev. 1.0. The TFP401/401A has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V supplies. The TFP401A incor...

2S107

Package Cooled:CAND/C:560

The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct con- nection to a separate SNAPHAT housing contain- ing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high t...

2S107

Package Cooled:CAND/C:560

The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct con- nection to a separate SNAPHAT housing contain- ing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high t...

2S108

Package Cooled:CAND/C:689

2.2 Specifications, standards, and handbooks. The following specifications, standards, and handbooks form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DODISS) and supplement thereto, cited in the solicitation (see 6.2).

2S109

Package Cooled:CAND/C:667

For applications requiring On/Off control of the output voltage, the 20-A programmable regulators incorporate a standby function. This feature may be used for power- up/shutdown sequencing, or to change the output voltage while input power is applied. See related note: Pin-Coded Output Voltage Adjustment of 20-A Programmable Regu- lators

2S109

Package Cooled:CAND/C:667

For applications requiring On/Off control of the output voltage, the 20-A programmable regulators incorporate a standby function. This feature may be used for power- up/shutdown sequencing, or to change the output voltage while input power is applied. See related note: Pin-Coded Output Voltage Adjustment of 20-A Programmable Regu- lators

2S110

Package Cooled:CAND/C:557

Instructions and Programming The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a seven-bit counter. The output of this counter is decoded to select one of one-hundred wiper pos...

2S111

Package Cooled:CAND/C:625

DM74184 BCD-TO-BINARY CONVERTERS The 6-bit BCD-to-binary function of the DM74184 is analo- gous to the algorithm a Shift BCD number right one bit and examine each dec- ade Subtract three from each 4-bit decade containing a binary value greater than seven

2S112

Package Cooled:CAND/C:625

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

2S112

Package Cooled:CAND/C:625

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

2S114

Package Cooled:CAND/C:550

The FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE) input is low. When OE is high, the bus output is in the high-impedance state. ...

2S115

Package Cooled:CAND/C:540

2S115

Package Cooled:CAND/C:540

2S116

Package Cooled:CAND/C:668

Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifica- tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari- ables. Fairchild does not recommend operation outside databook specifica- tions.

2S117

Package Cooled:CAND/C:560

2S117

Package Cooled:CAND/C:560

2S118

Package Cooled:CAND/C:689

2S119

Package Cooled:CAND/C:667

These Precision Optical Perform- ance AlInGaP LEDs provide superior light output for excellent readability in sunlight and are extremely reliable. AlInGaP LED technology provides extremely stable light output over long periods of time. Precision Optical Performance lamps utilize the aluminum indium gallium phos- phide (AlInGaP) technology.

2S120

Package Cooled:CAND/C:557

The LCX245 contains eight non-inverting bidirectional buff- ers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage (2.5V and 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The T/R input determines the direction of data flow through the device. The OE input dis- ables both the A and B ports by placing them in a hi...

2S121

Package Cooled:CAND/C:625

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device spcification sheets before using any SHARP device.

2S122

Package Cooled:CAND/C:560

Unless otherwise specified R14 e R15 e 1 kX C e 15 pF pin 16 to VEE RL e 50X pin 4 to ground Curve A Large Signal Bandwidth Method of Figure 7 VREF e 2 Vp-p offset 1 V above ground Curve B Small Signal Bandwidth Method of Figure 7 RL e 250X VREF e 50 mVp-p offset 200 mV above ground Curve C Large and Small Signal Bandwidth Method of Figure 9 (no op amp RL e 50X) RS e 50X VREF e 2V VS e 100 mVp-p center...

2S123

Package Cooled:CAND/C:689

2S124

Package Cooled:CAND/C:667

2S125

Package Cooled:CAND/C:557

2S125

Package Cooled:CAND/C:557

2S126

Package Cooled:CAND/C:625

Specifications are for the output (OUTA or OUTB) of a single 2nd order section (A or B) with respect to VGND = VGNDA = VGNDB, gain = C1, RFIL = R11 = R21 = R31 = R12 = R22 = R32, (see Block Diagram). The q denotes the specifications which apply over the full operating temperature range, otherwise specifications and typical values are at TA = 25C. VS = single 5V, EN pin to logic low, RL = 400Ω connected t...

2S1265

Vendor:F

Parallel configuration control input. This input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive

2S1274-S

Vendor:SANYOPackage Cooled:TO-220FD/C:02+

5-A Maximum Load Switches Voltages 1.8- to 5.5-V Ground Referenced Logic Inputs 1.8- to 5-V Logic Voltage Compatible 25-mW Maximum On-Resistance Level-Shifted Gate Drive Means The Control (Logic) Voltage Is Independent Of Power Voltage

2S129

Vendor:TID/C:07+

2S130

Package Cooled:CAND/C:560

2S131

Package Cooled:CAND/C:689

1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open. 2.ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in random Read/Write and EDO Fast Page Mode. 3.Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to ...

2S132

Package Cooled:CAND/C:667

2S133

Package Cooled:CAND/C:557

Two banks of four outputs each provide low-skew, low-jitter copies of 2S133LKIN x four. All outputs operate at the same frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at 2S133LKIN. The device automatically goes into power-down mode when no input signal is applied to 2S133LKIN and the outputs go into a low state. Unlike many products containing PLLs, the 2S133 does not require...

2S133

Package Cooled:CAND/C:557

Two banks of four outputs each provide low-skew, low-jitter copies of 2S133LKIN x four. All outputs operate at the same frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at 2S133LKIN. The device automatically goes into power-down mode when no input signal is applied to 2S133LKIN and the outputs go into a low state. Unlike many products containing PLLs, the 2S133 does not require...

2S134

Package Cooled:CAND/C:625

EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set LOW and will remain set until the difference between the write pointer and read pointer is less t...

2S134

Package Cooled:CAND/C:625

EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set LOW and will remain set until the difference between the write pointer and read pointer is less t...

2S135

Package Cooled:CAND/C:625

Configurations or a Single Bidirectional Configuration Working Peak Reverse Voltage Range − 3 V to 26 V Standard Zener Breakdown Voltage Range − 5.6 V to 33 V Peak Power − 24 or 40 Watts @ 1.0 ms (Unidirectional), per Figure 5 Waveform ESD Rating of Class N (exceeding 16 kV) per the Human Body Model Maximum Clamping Voltage @ Peak Pulse Current Low Leakage < 5.0 mA Flammability R...

2S136

Package Cooled:CAND/C:560

Measured using analog input circuit in Figure 51 and digital stimulus in Figure 56 and Figure 57 and reference voltage of 4.096 V. Calculated on the first nine harmonics of the input frequency. Can vary +/-30%. This includes only +VA current. With +VBD = 5 V, +VBD current is typically 1 mA with a 10-pF load capacitance on the digital output pins.

2S137

Package Cooled:CAND/C:550

2S138

Package Cooled:CAND/C:540

Electrical characteristics are measured or characterized using a 223 - 1PRBS at 2.7Gbps with input edge speeds 200ps, unless otherwise noted. Dice are tested at TA = +25C only. All AC specifications are guaranteed by design and charac- terization, unless otherwise noted. Supply current measurement is taken with AC-coupled inputs and excludes output currents into 50Ω loads. Minimum gain is defined as VIN ...

2S138

Package Cooled:CAND/C:540

Electrical characteristics are measured or characterized using a 223 - 1PRBS at 2.7Gbps with input edge speeds 200ps, unless otherwise noted. Dice are tested at TA = +25C only. All AC specifications are guaranteed by design and charac- terization, unless otherwise noted. Supply current measurement is taken with AC-coupled inputs and excludes output currents into 50Ω loads. Minimum gain is defined as VIN ...

2S139

Package Cooled:CAND/C:668

4.4 Screening (JANTX and JANTXV levels). Screening shall be in accordance with appendix E, table IV of MIL-PRF-19500, and as specified herein. The following measurements shall be made in accordance with table I herein. Devices that exceed the limits of table I herein shall not be acceptable.

2S140

Package Cooled:CAND/C:560

Provide a well decoupled 5V bias supply for the IC to this pin. This pin also provides the gate bias charge for the lower MOSFET controlled by the PWM section of the IC, as well as the base current drive for the linear regulators external bipolar transistors. The voltage at this pin is monitored for Power-On Reset (POR) purposes.

2S140

Package Cooled:CAND/C:560

Provide a well decoupled 5V bias supply for the IC to this pin. This pin also provides the gate bias charge for the lower MOSFET controlled by the PWM section of the IC, as well as the base current drive for the linear regulators external bipolar transistors. The voltage at this pin is monitored for Power-On Reset (POR) purposes.

2S141

Package Cooled:CAND/C:689

Hynix HYMD232726A(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD232726A(L)8J-J series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD232726A(L)8J-J series provide a high performance 8-byte interface in 5.25" width form fac...

2S142

Package Cooled:CAND/C:667

For more details on UniqueWare and how to set up data files, please refer to the UniqueWare Project Setup Manual, available as Application Note 99 from Dallas Semiconductor. The UniqueWare Project Setup Software is available from the Dallas Semiconductor FTP Site at ftp://ftp.dalsemi.com/pub/auto_id, file name "unwsetup.exe."

2S142

Package Cooled:CAND/C:667

For more details on UniqueWare and how to set up data files, please refer to the UniqueWare Project Setup Manual, available as Application Note 99 from Dallas Semiconductor. The UniqueWare Project Setup Software is available from the Dallas Semiconductor FTP Site at ftp://ftp.dalsemi.com/pub/auto_id, file name "unwsetup.exe."

2S143

Package Cooled:CAND/C:557

IXYS Corporation • 3540 Bassett Street • Santa Clara, CA 95054 • Phone: 408-982-0700 • Fax: 408-496-0670 IXYS Semiconductor GmbH • Edisonstraße 15 • D-68623 Lampertheim • Phone: +49-6206-503-249 • Fax: +49-6206-503627

2S144

Package Cooled:CAND/C:625

The 2S144 Control IC combined with an IR XPhaseTM Phase IC provides a full featured and flexible way to implement a complete VRD 10 power solution. The Control IC provides overall system control and interfaces with any number of Phase ICs which each drive and monitor a single phase of a multiphase converter. The XPhaseTM architecture results in a power supply that is smaller, less expensive, and easier to d...

2S145

Package Cooled:CAND/C:560

The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be held at a valid logic high or low level. To ensure defined ...

2S145

Package Cooled:CAND/C:560

The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be held at a valid logic high or low level. To ensure defined ...

2S146

Package Cooled:CAND/C:689

2S146

Package Cooled:CAND/C:689

2S147

Package Cooled:CAND/C:667

2S148

Package Cooled:CAND/C:557

2S149

Package Cooled:CAND/C:625

2S153

Package Cooled:CAND/C:667

Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2005 Hamamatsu Photonics K.K.

2S159

Package Cooled:CAND/C:668

Very low VCE(sat) 1.5 V (typ.) Maximum Junction Temperature 175 C Short circuit withstand time C 5µsG Designed for : - Variable Speed Drive for washing machines, air conditioners and induction cooking - Uninterrupted Power Supply Trench and Fieldstop technology for 600 V applications offers : - very tight parameter distribution - high ruggedness, temperature stable behavior - very high swi...

2S160

Package Cooled:CAND/C:560

Crystal Frequency(Note TCLK Frequency TCLK Duty Cycle for LEN2/1/0 = 0/0/0(Note ACLKI Frequency(Note RCLK Duty Cycle(Note Rise Time, All Digital Outputs(Note Fall Time, All Digital Outputs(Note TPOS/TNEG (TDATA) to TCLK Falling Setup Time TCLK Falling to TPOS/TNEG (TDATA) Hold Time RPOS/RNEG Valid Before RCLK Falling(Note RDATA Valid Before RCLK Falling(Note RPOS/RNEG Valid Before RCLK Rising(No...

2S168

Package Cooled:CAND/C:557

When executing a jump instruction, conditional skip ex- ecution, loading to the PCL register, performing a sub- routine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from inter- rupts, the PC manipulates the program transfer by load- ing the address corresponding to each instruction.

2S169

Package Cooled:CAND/C:625

Fully self-contained 12 channel GPS receiver Fully EMI shielded SiRFstar™ IIe/LP architecture • GRF2i/LP RF front-end IC • GSP2e/LP GPS Engine with Integrated Processor SBAS(Satellite Based Augmentation System) support Fast time-to-first-fix 8Mbit Flash memory Built-in Low-noise amplifier Advanced low power modes Operating Voltage 3.3V Battery supply pin for internal back...

2S172

Package Cooled:CAND/C:540

the inputs a set-up time preceding the HIGH-to-LOW tran- sition of the Latch Enable. The 3-STATE standard outputs are controlled by the Output Enable (AOE1 or BOE1) input. When Output Enable is LOW, the standard outputs are in the 2-state mode. When Output Enable is HIGH, the stan- dard outputs are in the high impedance mode, but this does not interfere with entering new data into the latches.