Index "3"Vendor:NO
Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive LS TTL inputs Port 3 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally pulled low will source current (IIL on the data sheet) because of the pullups
FEATURES = Programmable hysteresis = 5 bit DAC programmable output (1.1V-1.85V) = On-chip power good and OVP functions = Designed to meet latest Intel specifications = Up to 95% efficiency = +1% voltage tolerance over temperature
Referring to the block diagram is recommended for understanding the operation of the LED current control. The ILED is the constant current programmed by the RLED. When the feedback voltage on the FB terminal reaches above the reference voltage VREF on the REF terminal (i.e., ILED is above the level programmed by RLED), the output capacitor C2 delivers the ILED. Once the feedback voltage drops below the ...
Referring to the block diagram is recommended for understanding the operation of the LED current control. The ILED is the constant current programmed by the RLED. When the feedback voltage on the FB terminal reaches above the reference voltage VREF on the REF terminal (i.e., ILED is above the level programmed by RLED), the output capacitor C2 delivers the ILED. Once the feedback voltage drops below the ...
Vendor:EPSONPackage Cooled:SMDD/C:0537
The device is compatible with the JEDEC single power-supply Flash command set standard. Com- mands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. Device programming is performed a byte at a time by executing the four-cycle Program Command. This initiates an int...
Vendor:EPSONPackage Cooled:SMDD/C:0537
The device is compatible with the JEDEC single power-supply Flash command set standard. Com- mands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. Device programming is performed a byte at a time by executing the four-cycle Program Command. This initiates an int...
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
Vendor:AMIPackage Cooled:01+D/C:PLCC-68
The curve tracer used as an example in this application note is a Tektronix 576, since this instrument is in widespread use. However, the principles involved apply equally well to other makes and models. Figure 1 shows the layout of the controls of the Tektronix 576 curve tracer, with major controls identified by the names used in this application note. Throughout this application note, when controls are r...
Vendor:AMIPackage Cooled:01+D/C:PLCC-68
The curve tracer used as an example in this application note is a Tektronix 576, since this instrument is in widespread use. However, the principles involved apply equally well to other makes and models. Figure 1 shows the layout of the controls of the Tektronix 576 curve tracer, with major controls identified by the names used in this application note. Throughout this application note, when controls are r...
Vendor:NSCD/C:01-04+
GROUND - Is the return for the VBIAS supply. This pin should be connected to the return of the lowside MOSFETs or the bottom of the sense resistor at the bottom of the bridge. The gate drive current must return through this pin, so trace lengths should be kept to a minimum. All grounds should be returned to the bottom of the bridge or sense resistor in a star fashion. This will eliminate ground loops.
D/C:06+
Rail-to-Rail Input and Output Small SOT-23 Package Gain Bandwidth Product: 10MHz C40C to 85C Operation Slew Rate: 2.25V/µs Low Input Offset Voltage: 1.5mV Max High Output Current: 25mA Min Specified on 3V, 5V and 5V Supplies High Voltage Gain: 1000V/mV 10k Load High CMRR: 88dB Min High PSRR: 80dB Min Input Bias Current: 300nA Max Input Offset Current: 25nA Max
250-kHz Sampling Rate 4-V, 5-V, 10 V, 3.33-V, 5-V, and 10-V Input Ranges 2.0 LSB Max INL 1 LSB Max DNL, 16-Bit No Missing Codes SPI Compatible Serial Output with Daisy-Chain (TAG) Feature Single 5-V Supply Pin-Compatible With ADS7809 (Low Speed) and 12-Bit ADS8508/7808 Uses Internal or External Reference 70-mW Typ Power Dissipation at 250 KSPS 20-Pin SO and 28-Pin SSOP Packages Simple DSP Interface
Vendor:TOSHIBAPackage Cooled:23-3.9VD/C:05+
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the CMP04 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid perfor...
Vendor:VartaD/C:07+
Vendor:KDSPackage Cooled:20.6×12.6D/C:DIP 4P
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under DC Electrical Characteristics. 2. Per TTL driven input (VIN = 3.4V). 3. For flip-flops, ICCD is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of device power consumption only and does not include power to drive load capacitance or tester capacitance. ...
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximumCrated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 1. Measured with minimum pad spacing on an FR4 board, using 10 m...
Vendor:TOYOCOMD/C:90
The HYM72V32736T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The HYM72V32736T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
Package Cooled:BGA2727D/C:03+
1. Other frequencies may be available, please contact factory with your special requirements. 2. A 0.1 µF low frequency tantalum bypass capacitor in parallel with a 0.01 µF high frequency ceramic capacitor is recommended. Both should be located as close to the FTU-Type bias pin as is practical 3. Figure 1 defines these parameters. Figure 2 illustrates the equivalent TTL load and operating conditio...
Vendor:INNOVATECPackage Cooled:QFP1010-52D/C:00+
Vendor:INNOVATECPackage Cooled:QFP1010-52D/C:00+
This pin is capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. It is in tri-state mode when the transceiver is in shutdown mode and during digital serial programming operations. RXD is high at initialization.
Vendor:BGAPackage Cooled:THALESD/C:05+
An additional feature of the OPA502 and OPA512 power amplifiers, the optional fold-over circuit, can be connected on the current limit circuit. This can be set to reduce the current limit value when VCE is largeexactly the condition that exists with a short-circuit. While useful in some appli- cations, the foldover limiter can produce unusual behavior especially with reactive loads. See the OPA502 data ...
Vendor:HUGHESPackage Cooled:PLCC68D/C:08+09+
Vendor:HARRSPackage Cooled:DIPD/C:9438
The signal on the current sense input pin is also connected to the input of an over-current comparator. If the amplitude of the current sense signal exceeds 1.25 V, the comparator detects an overload condition and immediately terminates the output pulse. The propagation delay from CSNS to output, in an over-current condition, is typically 170 ns.
Vendor:HARPackage Cooled:CDIP18D/C:84+
D/C:08+
Vendor:N/APackage Cooled:N/AD/C:N/A
Three isolated elements are contained in one package, allowing high-density mounting Forward voltage VF , optimum for low voltage rectification Optimum for high frequency rectification because of its short reverse recovery time trr
D/C:96
An output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system, without need for interface or pullup components. OE does not affect the ...
Vendor:EMPLAPackage Cooled:5000D/C:QFN
Vendor:SIEMENSPackage Cooled:DIP/16
PROTECTION SECTION Peak Current Limit Current Limit Delay Time(3) Thermal Shutdown Temperature(3) Shutdown Feedback Voltage Over Voltage Protection Shutdown Delay Current Leading Edge Blanking Time TOTAL DEVICE SECTION Operating Supply Current (control part only) Start-Up Charging Current Vstr Supply Voltage
Vendor:SIEMENSPackage Cooled:DIP/16
PROTECTION SECTION Peak Current Limit Current Limit Delay Time(3) Thermal Shutdown Temperature(3) Shutdown Feedback Voltage Over Voltage Protection Shutdown Delay Current Leading Edge Blanking Time TOTAL DEVICE SECTION Operating Supply Current (control part only) Start-Up Charging Current Vstr Supply Voltage
Vendor:AMTELPackage Cooled:N/AD/C:98
PCI stop clock control input. When this signal is at a logic low level (0), all PCI clocks (except PCI_F) stop at a logic low level. Using this pin to start and stop PCI clocks insures synchronous (no short or long clocks) transitioning of these clocks. This pin has no effect on the PCI_F clock.
Vendor:QFP-44PPackage Cooled:INFINEOND/C:2004+
The ADSP-TS202S processor has two IALUs that provide pow- erful address generation capabilities and perform many general- purpose integer operations. The IALUs are referred to as J and K in assembly syntax and have the following features:
Vendor:infineonD/C:5000
Vendor:DIBCOMPackage Cooled:QFPD/C:04+
Vendor:DIBCOMPackage Cooled:QFP80D/C:05+
4.75V VDD 5.5V, VSS = 0V; CAGC = 4.7µF, CTH = 0.022µF; fREFOSC = 9.794MHz (equivalent to fRF = 315MHz); data rate = 600 bps (Manchester encoded). TA = 25C, bold values indicate C40C TA +85C; current flow into device pins is positive, unless noted.
Vendor:DIBCOMPackage Cooled:QFP80D/C:05+
4.75V VDD 5.5V, VSS = 0V; CAGC = 4.7µF, CTH = 0.022µF; fREFOSC = 9.794MHz (equivalent to fRF = 315MHz); data rate = 600 bps (Manchester encoded). TA = 25C, bold values indicate C40C TA +85C; current flow into device pins is positive, unless noted.
D/C:6
Specification is not production tested but is supported by characterization data at initial product release. Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V). 3The 3000-M-B/122A-03 can tolerate absolute analog input voltages down to GND − 200 mV but the leakage current will increase. 4FS[2:0] are the three bits used in th...
Package Cooled:05+D/C:800
These devices consist of two independent, high-gain, frequency-compensated operational amplifiers designed to operate from a single supply over a wide range of voltages. Operation from split supplies also is possible if the difference between the two supplies is 3 V to 32 V (3 V to 26 V for the LM2904), and VCC is at least 1.5 V more positive than the input common-mode voltage. The low supply-current d...
Vendor:DIBCOMPackage Cooled:QFP128D/C:04+
Vendor:DIBCOMPackage Cooled:50D/C:N/A
Package Cooled:05+D/C:800
NOTES: 1. Industrial temperature range product for the 25ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Measurements with 0.4 VIN VCC. 3. R VIH, 0.4 VOUT VCC. 4. Tested with outputs open (IOUT = 0). 5. Tested at f = 20 MHz. 6. All Inputs = VCC - 0.2V or GND + 0.2V.
The SRAM is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse up to the transient dose rate upset specification, when applied under recommended operat- ing conditions. To ensure validity of all specified perfor- mance parameters before, during, and after radiation (timing degradation during transient pulse radiation (tim- ing degra...
Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor package must be the correct size to ensure proper solder connection inter- face between the board and the package. With the correct pad geometry, the packages will selfCalign when subjected to
Package Cooled:08+D/C:800
Operating voltage: +5.0V Programming voltage C VPP=12.2V0.2V C VCC=5.8V0.2V High-reliability CMOS technology Latch-up immunity to 100mA from -1.0V to VCC+1.0V CMOS and TTL compatible I/O Low power consumption C Active: 30mA max. C Standby: 1µA typ.
Vendor:SMSCD/C:97+
Vendor:CIDCOPackage Cooled:350D/C:N/A
Hynix HYMD525G726(L)S4M-K/H/L series is Low Profile registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 256Mx72 high-speed memory arrays. Hynix HYMD525G726(L)S4M-K/H/L series consists of eighteen stacked 128Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD525G726(L)S4M-K/H/L series provide a high performance 8-by...
Vendor:CIDCOPackage Cooled:SOPD/C:96+
Singularly suited for very wideband high-gain operation, the CLC425 employs a traditional voltage-feedback topology providing all the benefits of balanced inputs, such as low offsets and drifts, as well as a 96dB open-loop gain, a 100dB CMRR and a 95dB PSRR.
Vendor:CIDCOPackage Cooled:SOPD/C:96+
Singularly suited for very wideband high-gain operation, the CLC425 employs a traditional voltage-feedback topology providing all the benefits of balanced inputs, such as low offsets and drifts, as well as a 96dB open-loop gain, a 100dB CMRR and a 95dB PSRR.
DESCRIPTION The device is a power supply controller specifically designed to provide a high performance DC/DC conversion for high current microprocessors. The device implements a dual-phase step-down con- troller with a 180 phase-shift between each phase. A precise 5-bit digital to analog converter (DAC) allows adjusting the output voltage from 0.800V to 1.550V with 25mV binary steps manag- ing On-...
Package Cooled:SOP10MD/C:2007+
Vendor:CIDCOPackage Cooled:500D/C:N/A
1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than VSS may cause destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7211AM be turn...
Up to 2.25-A Output Current at 85C 4.5-V to 18-V Input Voltage Range Wide-Output Voltage Adjust (0.9 V to 5.5 V) Efficiencies Up To 93% On/Off Inhibit Undervoltage Lockout (UVLO) Output Overcurrent Protection (Nonlatching, Auto-Reset) Overtemperature Protection
Vendor:AMID/C:08+
These power transistors are produced by PPC's DOUBLE DIFFUSED PLANAR process. This technology produces high voltage devices with excellent switching speeds, frequency response, gain linearity, saturation voltages, high current gain, and safe operating areas. They are intended for use in Commercial, Industrial, and Military power switching, amplifier, and regulator applications.
Vendor:AMID/C:08+
These power transistors are produced by PPC's DOUBLE DIFFUSED PLANAR process. This technology produces high voltage devices with excellent switching speeds, frequency response, gain linearity, saturation voltages, high current gain, and safe operating areas. They are intended for use in Commercial, Industrial, and Military power switching, amplifier, and regulator applications.
Vendor:VISHAYPackage Cooled:SOP8D/C:05+
This voltage is made in an external loop filter and sent to VCO's input block. Operation voltage range is about 1 4V, and you can raise immunity against external noise if you want lower the VCO sensitivity by allowing the max operation voltage range possible at 5V power voltage. Refer to 'PLL Control' (30p).