34138

Vendor:AMP/TYCOD/C:0534

Stability The 34138 requires the use of an output capacitor as part of the frequency compensation in order to make the regulator stable. Typical designs for the microprocessor applications use standard electrolytic capacitors with typical ESR in the range of 50 to 100mV and the output capacitance of 500 to 1000mF. Fortunately as the ca- pacitance increases, the ESR decreases resulting in a fixed RC time con...

34141

Vendor:AMP/TYCOD/C:N/A

Notes: 1. The luminous intensity is measured on the mechanical axis of the lamp package. 2. The optical axis is closely aligned with the package mechanical axis. 3. The dominant wavelength, ëd, is derived from the CIE Chromaticity Diagram and represents the color of the lamp. 4. 1/2 is the off-axis angle where the luminous intensity is one half the on-axis intensity. 5. The intensity of narrow viewing ...

34-1410-00

NOTES: 1. Typical values are at VCC = 3.3V, TA = 25C. 2. Not more than one output should be used to test this high power condition. Duration is less than one second. 3. Guaranteed by design but not tested. 4. Output resistance represents the total output impedance of the logic device and includes added series termination resistance.

34143

The Microchip name and logo, the Microchip logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, MPLAB and The Embedded Control Solutions Company are reg- istered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

34145

Vendor:AMP/TYCOD/C:0218

Hynix HYMD264726A(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 64Mx72 high-speed memory arrays. Hynix HYMD264726A(L)8J-Jseries consists of eighteen 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD264726A(L)8J-J series provide a high performance 8-byte interface in 5.25" width form ...

3414-6634

Vendor:3M ELECTRONIC PRODUCT DIVISIOND/C:N/A

34148

Vendor:AMP/TYCOD/C:N/A

Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The DOUT_TXP and DOUT_TXN outputs are held static during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and in...

3414A9AMJRC

Vendor:n/aD/C:06+

cycle, an internal 10-bit counter provides the row ad- dresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.

3414A9AMJRC

Vendor:n/aD/C:06+

cycle, an internal 10-bit counter provides the row ad- dresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.

3414AD

Vendor:JRCPackage Cooled:N/AD/C:800

Note 1: See thermal regulation specification for changes in output voltage due to heating effects. Line and load regulation are measured at a constant junction temperature by low duty cycle pulse testing. Load regulation is measured at the output lead = 1/18 from the package. Note 2: Line and load regulation are guaranteed up to the maximum power dissipation of 15W. Power dissipation is determined by t...

3414D

Vendor:JRCPackage Cooled:N/AD/C:800

Use multilayer PCBs to minimize power and ground inductance Keep clock circuits away from the I/O connector Ground planes should be used whenever possible Minimize the loop area for all high speed signals Provide for adequate power decoupling

34150045-A

Package Cooled:PLCC

34152

Vendor:MOTPackage Cooled:SOP8D/C:06+

The first step in choosing the right product is to select the diode type. All of the products in the HSMS-282x family use the same diode chip, and the same is true of the HSMS-281x and HSMS-280x families. Each family has a different set of characteristics which can be compared most easily by consulting the SPICE parameters in Table 1.

34153001

3415D

Vendor:JRCPackage Cooled:DIP8D/C:00+

The HYM72V12C736B(L)S4 Series are 128Mx72bits ECC Synchronous DRAM Modules. The modules are composed of thirty six 64Mx4bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II stack package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.

34164.00

Package Cooled:SMDD/C:96+

34166T

Vendor:.Package Cooled:2005D/C:500

Current setting resistor (band-gap sense voltage). This terminal is connected to a precision external resistance to set the internal operating currents and the cable-driver output currents. A resistance of 6.04 kΩ, 1% between R0 and R1, is required to meet the 1394b output-voltage limits.

3417-6040

4.4.2 Group B inspection. Group B inspection shall be conducted in accordance with the conditions specified for subgroup testing in table VIb (JAN, JANTX), of MIL-PRF-19500. Electrical measurements (end points) and delta requirements shall be in accordance with the applicable steps of table II herein.

34181

These N-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supply.

34182

Package Cooled:08+D/C:800

The LP358 and LP2904 are dual low-power operational amplifiers especially suited for battery-operated applications. Good input specifications and wide supply-voltage range still are achieved, despite the ultra-low supply current. Single-supply operation is achieved with an input common-mode range that includes GND.

34186701

3418A

Vendor:ROHM

The AT91X40 Series is a subset of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-perfor- mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time co...

3418A

Vendor:ROHM

The AT91X40 Series is a subset of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-perfor- mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time co...

341B/5205

341CJ

The DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library of standard predesigned elements such as memories and peripherals. New modules may be added to the library to meet customer specifications. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configuratio...

341CL

Vendor:TELEDYNED/C:02+

NOTES 1Sample tested at 25C to ensure compliance. All input signals are specified with t R = tF = 5 ns (10% to 90% of AV DD) and timed from a voltage level of 1.6 V. See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3Measured with the load circuit of Figure 1 and defined as the time...

341S00/DHH

Vendor:SAMPackage Cooled:SOP44WD/C:2007+

341S0006-A

Vendor:ADMPackage Cooled:SOPD/C:N/A

• Plastic package has Underwriters Laboratories Flammability Classification 94V-0 • Ideally suited for use in very high frequency switching power supplies, inverters and as free wheeling diodes • Ultrafast recovery time for high efficiency • Excellent high temperature switching • Soft recovery characteristics • Glass passivated junction • High temperature ...

341S0020

Vendor:SECPackage Cooled:SMD-32D/C:03+

Technology: high performance SiGe Bandwidth: 9 GHz Input noise current density: 1.0 µA Optical sensitivity: C19.3 dBm Differential transimpedance: 5000 V/A Power dissipation: 200 mW Input current overload: 2.8 mA p-p Linear input range: 0.15 mA p-p Output resistance: 50 Ω/side Output offset adjustment range: 240 mV Average input power monitor: 1 V/mA Die size: 0.87 mm 1.06 mm

341S0063

Vendor:SHARPPackage Cooled:SMD-40D/C:94+

The TLV320AIC2x integrates all of the critical functions needed for most voice-band applications including MIC preamplifier, handset amplifier headset amplifier, 8-Ω speaker driver, sidetone control, antialiasing filter (AAF), input/output programmable gain amplifier (PGA), and selectable low-pass IIR/FIR filters.

341S0064LO

Vendor:SAMPackage Cooled:SOP44WD/C:2007+

This family is a 64M bit dynamic RAM organized 4,194,304 x 16-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(60 or 70ns) and refresh cycle(8K ref. or 4K ref.) and power consumpt...

341S0085

Package Cooled:TSOP

Notes: 1.Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2.Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed. 3.The package thermal impedance is calculated in accordance with JESD 51.

341S0100

Vendor:MXPackage Cooled:SOP44WD/C:2007+

341S0106

Package Cooled:SOP44WD/C:2007+

Input voltage amplitude at f=1 kHz*1: input to SG1 and SG2 are in phase such that total output harmonic distortion is 1%. However, signals(phase difference 0). Input voltage amplitude at f=1 kHztotal output harmonic*2: input to SG1 and SG2 are oppositesuch that (phase difference 180distortion is 1%. However, signalsin phase). *3: Voltage at which bypass pin (pin 22) is regarded as H bypass pin (pin 22) i...

341S0109

Package Cooled:SOP44WD/C:2007+

Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Single Supply Voltage: C 4.5 to 5.5V for M950x0 C 2.5 to 5.5V for M950x0-W C 1.8 to 5.5V for M950x0-R High Speed C 10MHz Clock Rate, 5ms Write Time Status Register BYTE and PAGE WRITE (up to 16 Bytes) Self-Timed Programming Cycle Adjustable Size Read-Only EEPROM Area Enhanced ESD Protection More than 1 Million Erase/Write C...

341S0110

Vendor:SAMPackage Cooled:SOP44WD/C:2007+

When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω.

341S0111

Vendor:SAMPackage Cooled:SOP44WD/C:2007+

Chip Select is a TTL compatible input which, when set HIGH, allows normal operation of the device. Any time Chip Select is set LOW, it resets the device, terminating all I/O communication, and puts the output in a high impedance state. CS is used to reset the device if an error condition exists or to put the device in a power- down mode to minimize power consumption. It may also be used to frame data...

341S0136

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

The STK12C68-20 requires VCC = 5.0V 5% supply to operate at specified speed. ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 13 ICC and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ) . 4E 2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. ...

341S0137

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

The Current Transfer Ratio (CTR) ranges from 100% to 200%. It also has an outstanding temperature coefficient of 50 ppm/C. It is primarily intended for use as the error amplifier/ reference voltage/optocoupler function in isolated ac to dc power supplies and dc/dc con- verters.

341S0139

Vendor:MXPackage Cooled:50D/C:N/A

Ultralow noise preamplifier Voltage noise = 0.74 nV/Hz Current noise = 2.5 pA/Hz 3 dB bandwidth: 120 MHz Low power: 125 mW/channel Wide gain range with programmable postamp C4.5 dB to +43.5 dB +7.5 dB to +55.5 dB Low output-referred noise: 48 nV/Hz typical Active input impedance matching Optimized for 10-/12-bit ADCs Selectable output clamping level Single 5 V supply operation Available in space...

341S0139

Vendor:MXPackage Cooled:50D/C:N/A

Ultralow noise preamplifier Voltage noise = 0.74 nV/Hz Current noise = 2.5 pA/Hz 3 dB bandwidth: 120 MHz Low power: 125 mW/channel Wide gain range with programmable postamp C4.5 dB to +43.5 dB +7.5 dB to +55.5 dB Low output-referred noise: 48 nV/Hz typical Active input impedance matching Optimized for 10-/12-bit ADCs Selectable output clamping level Single 5 V supply operation Available in space...

341S0145

Vendor:SECPackage Cooled:SOP44WD/C:2007+

The HT9170B/D are Dual Tone Multi Frequency (DTMF) receivers integrated with digital decoder and bandsplit filter functions as well as power-down mode and inhibit mode operations. Such devices use digital counting techniques to detect and decode all the 16 DTMF tone pairs into a 4-bit code output.

341S016

341S0168

Vendor:SECPackage Cooled:N/AD/C:97

341S0168

Vendor:SECPackage Cooled:N/AD/C:97

341S0171-LL

Vendor:INTEL MITELPackage Cooled:44 SOD/C:2006

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the devices ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the...

341S0172

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

The Microwire/SPI (MWSPI) interface module supports syn- chronous serial communications with other devices that conform to Microwire or Serial Peripheral Interface (SPI) specifications. It supports 8-bit and 16-bit data transfers.

341S0172

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

The Microwire/SPI (MWSPI) interface module supports syn- chronous serial communications with other devices that conform to Microwire or Serial Peripheral Interface (SPI) specifications. It supports 8-bit and 16-bit data transfers.

341S0173

Vendor:INTEL MITELPackage Cooled:40 SOD/C:2006

Operating voltage: 2.4V~5.0V Low standby current (1µA Typ.) Voice/sound effect/simple melody output 2.8-second voice capacity 32 tone sections 16 words for each tone section Current type D/A output Mask options C Pull-high resistor: 20kΩ/50kΩ/100kΩ C KEY1: Direct or sequential/random key C Trigger mode: Retriggerable/Non-retrig- gerable C KEY1 play normal mode or twin mode Nor...

341S0174

Vendor:MXPackage Cooled:SOP-44D/C:97

The HYM72V32M656T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The HYM72V32M656T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

341S0174

Vendor:MXPackage Cooled:SOP-44D/C:97

The HYM72V32M656T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The HYM72V32M656T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

341S0175

Vendor:INTEL MITELPackage Cooled:44 SOD/C:2006

The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive.

341S0188

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

because the timing models of competing architectures are very complex and include such things as timing dependen- cies on the number of parallel expanders borrowed, shar- able expanders, varying number of X and Y routing channels used, etc. In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model.

341S0189

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

The XC7336 device undergoes a short internal initializa- tion sequence upon device powerup. During this time (tRE- SET), the outputs remain 3-stated while the device is configured from its internal EPROM array and all registers are initialized. If the MR pin is tied to VCCINT, the initializa- tion sequence is completely transparent to the user and is completed in tRESET after VCCINT has reached 4...

341S0190

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

288 lines are stored in the 50-Hz standard (lines 23-310 of the first field, lines 336-623 of the second field) and 243 lines in the 60-Hz standard (lines 17-259 of the first field, lines 280-522 of the second field), (figure 1). In the 9-image mode a field without a frame consists of 208 pixels per line for luminance and 2 x 52 pixels per line for chrominance, with four pixels being lost for luminance a...

341S0190

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

288 lines are stored in the 50-Hz standard (lines 23-310 of the first field, lines 336-623 of the second field) and 243 lines in the 60-Hz standard (lines 17-259 of the first field, lines 280-522 of the second field), (figure 1). In the 9-image mode a field without a frame consists of 208 pixels per line for luminance and 2 x 52 pixels per line for chrominance, with four pixels being lost for luminance a...

341S0191

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

− 15-kV − Human-Body Model Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU v.28 Standards Operates at 5-V VCC Supply Operates Up To 120 kbit/s External Capacitors . . . 4 0.1 µF Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Applications − Battery-Powered Systems, PDAs, Notebooks, Laptops, Palmtop PCs, and Hand-Held Equipment

341S0193-1

Vendor:MicrochipPackage Cooled:SOP28WD/C:2007+

This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The...

341S0207

Vendor:SHARPPackage Cooled:TSSOP-48

Note 1: At TA = -40C, DC characteristics are guaranteed by design and characterization. Note 2: CML outputs open. Note 3: RL = 50Ω to VCC. Note 4: AC characteristics are guaranteed by design and characterization. Note 5: Relative to the falling edge of SCLKO+. See Figure 2. Note 6: Measured with 223 - 1 PRBS. Note 7: Jitter BW = 12kHz to 20MHz.

341S0255

Package Cooled:PLCC-20D/C:99

10 bits x (8 + 2) channels 8 bits x 2 2 channels (trigger: 24 sources) CRC-CCITT 15 bits x 1 (with prescaler) 25 internal and 8 external sources, 4 software sources, 7 levels 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) 4.2V to 5.5V (f(XIN)=16MHZ, without software wait) : Mask ROM, flash memory 5V version 2.7V to 5.5V (f(XIN)=10MHZ w...

341S0259

Vendor:APPLED/C:99+

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

341S0260

Vendor:APPLED/C:99+

Transmit Clock Tri-statable. This signal is used in synchronous DPSK/QAM transmission to latch serial input data on the TXD pin. Data must be provided so that valid data is available on the rising edge of the TXCLK. The transmit clock is derived from different sources depending upon the Synchronization mode selection. In Internal Mode the clock is generated internally (2400 Hz for QAM, 1200 Hz for DPSK or 6...

341S0260

Vendor:APPLED/C:99+

Transmit Clock Tri-statable. This signal is used in synchronous DPSK/QAM transmission to latch serial input data on the TXD pin. Data must be provided so that valid data is available on the rising edge of the TXCLK. The transmit clock is derived from different sources depending upon the Synchronization mode selection. In Internal Mode the clock is generated internally (2400 Hz for QAM, 1200 Hz for DPSK or 6...

341S0280

Package Cooled:SOP44WD/C:2007+

Self-discharge of NiMH and NiCd batteries is estimated based on an internal timer and temperature sen- sor. Compensations for battery tem- perature and rate of charge or dis- charge are applied to the charge, dis- charge, and self-discharge calcula- tions to provide available charge in- formation across a wide range of op- erating conditions. Battery capacity is automatically recalibrated, or learned, in...

341S0281

Package Cooled:SOP44WD/C:2007+

Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion High speed propagation delay < 2.5ns. (max) Up to 250MHz operation Very low CMOS power levels 1.5V VDDQ for HSTL interface Hot insertable and over-voltage tolerant inputs 3-level inputs for selectable interface Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface • Selectable differential or single-e...

341S0282

Package Cooled:SOP44WD/C:2007+

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input; all other inputs at Vcc or GND.

341S0282

Package Cooled:SOP44WD/C:2007+

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input; all other inputs at Vcc or GND.

341S0283

Package Cooled:SOP44WD/C:2007+

*Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the opera tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute max...

341S0285

In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon the baseband energy integrated over a specific time interval. The digital back end performs Differential Chip Detection (DCD), the correlator de-spreads the Direct Sequence Spread Spectrum (DSSS) Offset...

341S0327

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

341S0342

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

(3) Reset L level input over than 3ms to the RST terminal is initialization signal to initialize the internal circuit. This initialization signal is synchronized with internal clock and executes logical OR with the internal power on reset signal. This Reset signal initializes the internal function setting registers also. During initialization, the output-drivers output GND level. The reset equivalent...

341S0344

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

The new package that consists of OSAs and ESA with the combination of integrated EMI shield utilizes existing in-house high-volume assembly processes to ensure high quality and high volume supply. The integrated EMI shield helps to ensure low EMI emission and high immunity to EMI field, thus enhancing reliable performance.

341S0365

Vendor:SHARPPackage Cooled:SOP-44D/C:2007+

Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. 4. Power down has controlled clock c...

341S0367

+s ELECTRICAL CHARACTERISTICS (V =3.0V,RL=8Ω,f=1kHz,1pin=2V,Ta=25C,unless otherwise specified) PARAMETERSYMBOLTEST CONDITIONMIN.TYP. MAX. UNIT Operating Voltage Range V+2.0-4.5V Operating CurrentICCRL=,no signal-2.04.0mA Power Down CurrentICCDRL= 1pin=0.8V,no signal-0.11.0µA Open Loop GainA V18085-dBAmp#A, f<100Hz Closed Loop GainAV2-0.350+0.35dBAmp#B Output PowerPO1THD=10%110250-mW +...

341S0368

Vendor:MXPackage Cooled:SOP44WD/C:2007+

341S0370

Vendor:SECPackage Cooled:SOP44WD/C:2007+

341S0373

Vendor:SECPackage Cooled:SOP44WD/C:2007+

341S0374

Vendor:SECPackage Cooled:SOP44WD/C:2007+

341S0380-HH

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

341S0382-LH

Vendor:SHARPPackage Cooled:SOP44WD/C:2007+

341S0440-B

Vendor:IMPD/C:O9+

341S0490-A

Vendor:PLCC-20Package Cooled:AMDD/C:04+

The ASH receivers unique feature set is made possible by its sys- tem architecture. The heart of the receiver is the amplifier- sequenced receiver section, which provides more than 100 dB of stable RF and detector gain without any special shielding or de- coupling provisions. Stability is achieved by distributing the total RF gain over time. This is in contrast to a superheterodyne receiver, which achieves s...

341S0490-A

Vendor:PLCC-20Package Cooled:AMDD/C:04+

The ASH receivers unique feature set is made possible by its sys- tem architecture. The heart of the receiver is the amplifier- sequenced receiver section, which provides more than 100 dB of stable RF and detector gain without any special shielding or de- coupling provisions. Stability is achieved by distributing the total RF gain over time. This is in contrast to a superheterodyne receiver, which achieves s...

341S0514-01

Vendor:SECPackage Cooled:TSOPD/C:2007+

is described in the AT&T publication TR 54016 (Re- quirements for Interfacing DTE to Services Employing ESF C 1986/89). In addition it provides a number of im- portant performance parameters involved in monitoring T1 lines such as Errored Seconds, Severely Errored Seconds, and Unavailable Seconds.

341S0514-01

Vendor:SECPackage Cooled:TSOPD/C:2007+

is described in the AT&T publication TR 54016 (Re- quirements for Interfacing DTE to Services Employing ESF C 1986/89). In addition it provides a number of im- portant performance parameters involved in monitoring T1 lines such as Errored Seconds, Severely Errored Seconds, and Unavailable Seconds.

341S0532

Vendor:FSCPackage Cooled:N/AD/C:04+

341S0664-A

Vendor:PLCC-20Package Cooled:MMID/C:04+

The OPA694 is an ultra-wideband, low-power, current feedback operational amplifier featuring high slew rate and low differential gain/phase errors. An improved output stage provides 80mA output drive with < 1.5V output voltage headroom. Low supply current with > 500MHz bandwidth meets the requirements of high density video routers. Being a current feedback design, the OPA694 holds its bandwidt...

341S0664-A

Vendor:PLCC-20Package Cooled:MMID/C:04+

The OPA694 is an ultra-wideband, low-power, current feedback operational amplifier featuring high slew rate and low differential gain/phase errors. An improved output stage provides 80mA output drive with < 1.5V output voltage headroom. Low supply current with > 500MHz bandwidth meets the requirements of high density video routers. Being a current feedback design, the OPA694 holds its bandwidt...

341S0765-A

341S0783

Vendor:HITPackage Cooled:SOP32WD/C:2007+

341S0784

Vendor:HITPackage Cooled:SOP32WD/C:2007+

This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz and 1 MHz).

341S0788

NOTES: (1) LSB means Least Significant Bit. One LSB for the 10V input range is 4.88mV. (2) Typical rms noise at worst case transition. (3) As measured with fixed resistors shown in Figure 7b. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of CFull Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (no...

341S0815-A

Vendor:PLCC-20Package Cooled:MMID/C:04+

The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data in put set up and hold timing should be referenced to the rising edge of the signal that terminates the write.

341S0816-A

Vendor:AMPackage Cooled:08+D/C:800

Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of electrical characteristics provide conditions for actual device operation. Note 2: Unless otherwise specified, all voltage are referenced to ground.

341S0816-A

Vendor:AMPackage Cooled:08+D/C:800

Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of electrical characteristics provide conditions for actual device operation. Note 2: Unless otherwise specified, all voltage are referenced to ground.

341S0817-A

Vendor:AMDPackage Cooled:PLCC28

The TLV2262/4 also makes great upgrades to the TLV2332/4 in standard designs. They offer increased output dynamic range, lower noise voltage and lower input offset voltage. This enhanced feature set allows them to be used in a wider range of applications. For applications that require higher output drive and wider input voltage range, see the TLV2432 and TLV2442 devices. If your design requires single amp...

341S0828-A

The CD4014B and CD4021b series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

341S0833-A

Vendor:AMDPackage Cooled:PLCC20D/C:03+

341S0851

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures...

341S0855-A