301AN

301BL072

301CJ111

Package Cooled:DIP16D/C:2007+

301CL

Vendor:360

+5V main power supply Back-up power supply (back-up capacitor connected) Pulse width setting pin for pulse shaver (capacitor and resistor connected) Reset output Switches 1-chip microcomputer mode with pulse shaver output signal Chip enable signal output (power outage detection signal) GND

301CMQ045

D/C:N/A

This Digital Audio MOSFET is specifically designed for Class-D audio amplifier applications. This MOSFET utilizes the latest processing techniques to achieve low on-resistance per silicon area. Furthermore, gate charge, body-diode reverse recovery and internal gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD, and EMI.

301CMQ045

D/C:N/A

This Digital Audio MOSFET is specifically designed for Class-D audio amplifier applications. This MOSFET utilizes the latest processing techniques to achieve low on-resistance per silicon area. Furthermore, gate charge, body-diode reverse recovery and internal gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD, and EMI.

301CNQ035

D/C:N/A

301CNQ045 D/C01 1

Vendor:IRD/C:1

301CNQ050

D/C:N/A

A B C D (Pins 7 1 2 6) BCD data inputs A (pin 7) is the least-significant data bit and D (pin 6) is the most significant bit Hexadecimal data ACF at these inputs will cause the outputs to assume a logic low offering an alternate method of blanking the display

301CNQ100

D/C:N/A

301DH

Package Cooled:N/AD/C:800

* UL is a registered trademark of Underwriters Laboratories, Inc. † CSA is a registered trademark of Canadian Standards Association. ‡ This product is intended for integration into end-use equipment. All the required procedures for CE marking of end-use equipment should be followed. (The CE mark is placed on selected products.)

301DH

Package Cooled:N/AD/C:800

* UL is a registered trademark of Underwriters Laboratories, Inc. † CSA is a registered trademark of Canadian Standards Association. ‡ This product is intended for integration into end-use equipment. All the required procedures for CE marking of end-use equipment should be followed. (The CE mark is placed on selected products.)

301E-D35

Vendor:n/aD/C:06+

An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

301E-DF2

Vendor:n/aD/C:06+

High-speed ADC Family Companion Chip Selectable 1:2 or 1:4 DMUX Ratio Power Consumption: 2.6W LVDS Compatible Differential Data and Clock Inputs (100Ω Terminated) LVDS Compatible Differential Data and Data Ready Outputs Staggered or Simultaneous Data Outputs C 11th Bit = Ports A, B, C and D Clock in Staggered Mode Selectable Active Edge for Input and Output Clocks: C Only Rising: CLK and DR Mode C...

301HYUIN

Vendor:IRPackage Cooled:SMD-8D/C:9644+

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

301HYUIN

Vendor:IRPackage Cooled:SMD-8D/C:9644+

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

301LV

DIGITAL OUTPUTS(6) Logic Family Logic Coding Low Output Voltage (IOL = 50µA to 0.5mA) High Output Voltage (IOH = 50µA to 0.5mA) Low Output Voltage (IOL = 50µA to 1.6mA) High Output Voltage (IOH = 50µA to 1.6mA) 3-State Enable Time 3-State Disable Time Output Capacitance

301MV VB0 100TQFP

301R102U040HJ2E

301R18W223MV4E

301SAF-ET

Vendor:SPIPackage Cooled:03+D/C:1340

Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123 so that the 221 or LS221 devices can be substituted for those products in systems not using the retrigger by merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.

301U120

Vendor:IRPackage Cooled:DO-205AB (DO-9)D/C:00+

Mounting a high resolution or three channel encoder with Module Side A as the mounting plane requires alignment pins in the motor base. These alignment pins provide the necessary centering of the module with respect to the center of the motor shaft. In addition to centering, the codewheel gap is also important. Please refer to the respective encoder data sheet for necessary mounting informa...

301U120

Vendor:IRPackage Cooled:DO-205AB (DO-9)D/C:00+

Mounting a high resolution or three channel encoder with Module Side A as the mounting plane requires alignment pins in the motor base. These alignment pins provide the necessary centering of the module with respect to the center of the motor shaft. In addition to centering, the codewheel gap is also important. Please refer to the respective encoder data sheet for necessary mounting informa...

301U250

Vendor:IRPackage Cooled:DO-205AB (DO-9)D/C:00+

Single Chip With Easy Interface Between UART and Serial-Port Connector of IBM™ PC/AT ™ and Compatibles Meets or Exceeds the Requirements of ANSI Standard TIA/EIA-232-F and ITU Recommendation V.28 Designed to Support Data Rates up to 120 kbit/s Pinout Compatible With SN75C185 and SN75185 ESD Protection to 2 kV on Bus Terminals Package Options Include Plastic Small-Outline (DW), Shrink Small-Ou...

301U250

Vendor:IRPackage Cooled:DO-205AB (DO-9)D/C:00+

Single Chip With Easy Interface Between UART and Serial-Port Connector of IBM™ PC/AT ™ and Compatibles Meets or Exceeds the Requirements of ANSI Standard TIA/EIA-232-F and ITU Recommendation V.28 Designed to Support Data Rates up to 120 kbit/s Pinout Compatible With SN75C185 and SN75185 ESD Protection to 2 kV on Bus Terminals Package Options Include Plastic Small-Outline (DW), Shrink Small-Ou...

301XX-B9-9

Vendor:NSCD/C:2006

3020-125M84

Vendor:LUCENTPackage Cooled:PLCC84D/C:97+

302-016-NA1

302019

3.1 The END USER shall have the right to transfer the AMBE-2000™ Vocoder Chip and all rights under this Agreement to a third party by either (i) providing the third party with a copy of this Agreement or (ii) providing the third party with an agreement written by the END USER ( hereinafter END USER Agreement) so long as the END USER Agreement is approved in writing by DVSI prior to transfer of the AM...

3020687-1

3020-70

nal pull-up resistor should be connected between SDA and V CC . The value of this resistor and the system capacitance loading the SDA bus will determine the rise time of SDA. This rise time will determine the maximum frequency during read operations. Low value pull-up resistors will allow higher frequency operations while drawing higher aver- age power supply current.

3020-70M68

Vendor:LUCENTD/C:06+

The upper ESD diodes for the R, G and B channels are connected to a separate supply rail (VRGB) to facilitate interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5V rail (VCC). The lower diodes for the R, G and B channels are also connected to a dedicated ground pin (GNDA) to minimize crosstalk due to common ground impedance.

3020-70M68

Vendor:LUCENTD/C:06+

The upper ESD diodes for the R, G and B channels are connected to a separate supply rail (VRGB) to facilitate interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5V rail (VCC). The lower diodes for the R, G and B channels are also connected to a dedicated ground pin (GNDA) to minimize crosstalk due to common ground impedance.

30209 BOSCH ZIP N/A

30210

NOTE: H = Input Voltage High Level, h = Input voltage high one set-up timer prior clock transition; L = Input Voltage Low Level; l = Input voltage low one set-up time prior clock transition; qn = Lower case letter indicates the state of the reference output one set-up time prior to clock transition; X - Voltage level on logic status dont care; Z = Output in high impedance state, = Low to High Clock Transit...

302115

302118

Vendor:.Package Cooled:LTD/C:2005+

The transmitter accepts CMOS level logical clock, positive data and negative data and converts them to the AMI signal to drive a 75Ω coaxial cable. Programmable internal Line Buildout (LBO) circuitry eliminates the need for external LBO networks. When the option pins are properly selected, the shape of the transmitted signal through any cable length of 0 to 450 feet complies with the published templat...

302128A

302128-A

Vendor:BayNetworksD/C:O9+

HN58X24xxxFPIAG series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also have a 64-byte page programming function to make their write operation faster.

302128-B

Vendor:20000Package Cooled:05+

The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible levels. The output driver can source 4mA and sink 8mA in 3.3V mode. The output drivers have a separate VCCIO reference input which is independent of the main VCC supply for the device. This feature allows individual output drivers to drive either 3.3V (from the device VCC) or 2.5V (from the VCCIO pin) output levels while the device...

302128C

30215

Vendor:N/AD/C:DIP-16

30215

Vendor:N/AD/C:DIP-16

30215-01/4897

30217401

30217402

Package Cooled:01D/C:800

3021L1T

Vendor:N/APackage Cooled:N/AD/C:08+09+

Most high-speed ADCs that sample more than several hundred megahertz have input bandwidths that are limited to no more than their maximum sampling frequency to improve noise performance. One example is the signal-to-noise ratio (SNR). This limited input bandwidth may rule out use in applications where bandwidths of interest in the input spectrum are higher, and an undersampling approach is needed. Also, i...

3021W1SBR76F40X

Vendor:CONECPackage Cooled:05+D/C:19

The MPX5500 series piezoresistive transducer is a stateCofCtheCart monolithic silicon pressure sensor designed for a wide range of applications, but particularly those employing a microcontroller or microprocessor with A/D inputs. This patented, single element transducer combines advanced micromachining techniques, thinCfilm metalliza- tion, and bipolar processing to provide an accurate, high level analog...

3021W1SBT78P20X

Vendor:CONECPackage Cooled:502D/C:73

NOTES 1Temperature range is as follows: B Version, C40C to +85C. 2All typical values are at VCC1 = VCC2, TA = 25C, unless otherwise stated. 3VIL and VIH levels are specified with respect to VCC1; VOH and VOL levels are with respect to VCC2. 4Guaranteed by design, not subject to production test. 5See Test Circuits and Waveforms.

3021W1SBT78P20X

Vendor:CONECPackage Cooled:502D/C:73

NOTES 1Temperature range is as follows: B Version, C40C to +85C. 2All typical values are at VCC1 = VCC2, TA = 25C, unless otherwise stated. 3VIL and VIH levels are specified with respect to VCC1; VOH and VOL levels are with respect to VCC2. 4Guaranteed by design, not subject to production test. 5See Test Circuits and Waveforms.

302-20201

Vendor:NECPackage Cooled:DIPD/C:1995+

NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage rating...

30223

Vendor:HHPackage Cooled:00+D/C:DIP-16

There are two methods for reading out the signal from an NMOS linear image sensor. One is a current detection method using the load resistance and the other is a current integration method using a charge amplifier. In either readout method, a positive bias must be applied to the video line because photodiode anodes of NMOS linear image sensors are set at 0 V (Vss). Figure 8 shows a typical video bias v...

30223

Vendor:HHPackage Cooled:00+D/C:DIP-16

There are two methods for reading out the signal from an NMOS linear image sensor. One is a current detection method using the load resistance and the other is a current integration method using a charge amplifier. In either readout method, a positive bias must be applied to the video line because photodiode anodes of NMOS linear image sensors are set at 0 V (Vss). Figure 8 shows a typical video bias v...

30228

Package Cooled:05+D/C:SMD

Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical 1. The entire memory can be erased by using the Chip Erase command or individual planes or sectors can be erased by using the Plane Erase or Sector Erase commands.

3022S5VPULLS

ITU-T recommendations specify limits on the tolerance, transfer, and generation of jitter. Signal quality at the LA output (as represented by the eye opening) is usually low, mostly as a consequence of nonideal components in the optical transmission system. Because the CDR must accept a certain amount of input data jitter to achieve normal error-free operation, all receiver units in line-termination and reg...

3023366

3023418

Vendor:STPackage Cooled:QFP

Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power pin for the 48MHz output.3.3V 48.00MHz USB clock Ground pin. No Connection. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Frequency select pin. Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Output enable fo...

30235

Package Cooled:PLCC28D/C:07/08+

The I/O cell also includes a programmable flow-through latch or register that can be placed in the input or output path and bypassed for combinatorial outputs. As shown in Figure 1, when the input control MUX of the register/ latch selects the A path, the register/latch gets its inputs from the 4:1 MUX and drives the I/O output. When selecting the B path, the register/latch is directly driven by the I...

3024/2C

Vendor:ERICSSONPackage Cooled:BGAD/C:07+

International Rectifier does not recommend the use of this product in aerospace, avionics, military or life support applications. Users of this International Rectifier product in such applications assume all risks of such use and indemnify International Rectifier against all damages resulting from such use.

3024/CRIA

D/C:98+

When expander logic is used in the data path, add the appro- priate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data-path frequency for the synchronous configuration.

30250

Vendor:(H)Package Cooled:N/AD/C:800

The FCT573Tis an octal transparent latch built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE is low, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OE is high, the bu...

30250

Vendor:(H)Package Cooled:N/AD/C:800

The FCT573Tis an octal transparent latch built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE is low, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OE is high, the bu...

3025216206CATR

Hynix HYMD264646(L)8-K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Mem- ory Modules (DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix HYMD264646(L)8-K/H/L series consists of sixteen 32Mx8 DDR SDRAM in 400mil TSOPII packages on a184pin glass-epoxy substrate. Hynix HYMD-264646(L)8-K/H/L series provide a high performance 8-byte interface in 5.25" widt...

30259PLCC

Package Cooled:PLCC

• Space Saving SIP Package • +5V input • 5-bit Programmable: 1.3V to 3.5V@13A • High Efficiency • Input Voltage Range: 4.5V to 5.5V • Differential Remote Sense • Short Circuit Protection • Over-Voltage Drive • Power Good Signal

3025KS

Vendor:SKPackage Cooled:04D/C:800

• Thyristor for frequencies up to 400Hz • International standard package • Epoxy meets UL 94V-0 • High performance glass passivated chip • Long-term stability of leakage current and blocking voltage • Plasitc overmolded tab for electrical isolation

3025L1T

General description Quad channel Low-Side Switch in Smart Power Technology (SPT) with four separate inputs and four open drain DMOS output stages. The TLE 6225 G is protected by embedded protec- tion functions and designed for automotive and industrial applications, to drive lines, lamps and relays.

3025LS

Package Cooled:01+D/C:800

For more information refer to Xilinx XC4000E and XC4000X series Field Programmable Gate Arrays product specifica- tion. This data sheet contains pinout tables for XQ4010E only. Refer to Xilinx web site for pinout tables for other devices. (Pinouts for XQ4000E/EX are identical to XC4000E/EX.) (http://www.xilinx.com/partinfo/databook.htm)

3025LSA

30262-18-A18

30268

Vendor:ＢＯＳＣＨ

Notes: 1. For bestCpractices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3 is for A version of TQFP (3 Chip Enable Option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.

30268

Vendor:ＢＯＳＣＨ

Notes: 1. For bestCpractices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3 is for A version of TQFP (3 Chip Enable Option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.

30277 BOSCH SOP N/A

30279

Vendor:PHILIPSPackage Cooled:PLCC-44D/C:00

Minimum Quiet Time Required between CS Rising Edge and Start of Next Conversion CS to SCLK Setup Time Delay from CS until DOUT Three-State Disabled Data Access Time after SCLK Falling Edge SCLK Low Pulsewidth SCLK High Pulsewidth SCLK to DOUT Valid Hold Time SCLK Falling Edge to DOUT High Impedance DIN Setup Time Prior to SCLK Falling Edge DIN Hold Time after SCLK Falling Edge Sixteenth SCLK Falling E...

30280

Vendor:BOSHPackage Cooled:SOP20D/C:N/A

The bq2085 uses an integrating converter with continuous sampling for the measurement of battery charge and discharge currents. Optimized for coulomb counting in portable applications, the self-calibrating integrating converter has a resolution better than 3-nVh and an offset measurement error of less than 1-µV (typical). For voltage and temperature reporting, the bq2085 uses a 16-bit A-to-D co...

30281

Package Cooled:SOP-8D/C:07+

Normally the input signal will be as follows: (nC1, ânC1) (n, ân) (n+1, ân+1) with n and ân virtually constant. Figures 15, 16, 17, 18 and 19 show the sequence obtained for output signal VS2 when using one of the three operating modes.

30283

Package Cooled:08+D/C:800

The TFDU6108 is an infrared transceiver module compliant to the latest IrDA standard for fast infrared data communication, supporting IrDA speeds up to 4.0 Mbit/s (FIR), and carrier based remote control modes up to 2 MHz. Integrated within the transceiver module are a PIN photodiode, an infrared emitter (IRED), and a low-power CMOS control IC to provide a total front-end solution in a single package....

30286

Package Cooled:08+D/C:800

system under rapidly changing current load conditions, designers generally use several output capacitors connected in parallel. Such an arrangement serves to minimize the effects of the parasitic resistance (ESR) and inductance (ESL) that are present in all capacitors. Cost-effective solutions that sufficiently limit ESR and ESL effects generally result in total capacitance values in the range of hundre...

30287

Vendor:100

TAOperating free-air temperature070C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

30287 BOSCH ZIP N/A

30288DC14-3

3028A

This manual describes the hardware of the H8S/2149 and H8S/2169 F-ZTAT™. Although the H8S/2169 is not explicitly mentioned in Section 2 to 7 or Section 9 to 22, the descriptions in these Sections apply to both the H8S/2149 and H8S/2169.

3028I

3029001

Vendor:N/APackage Cooled:00+D/C:SOP-8

Unless specifically noted all references to the 80C186EB apply to the 80C188EB 80L186EB and 80L188EB References to pins that differ between the 80C186EB 80L186EB and the 80C188EB 80L188EB are given in parentheses The L in the part number denotes low voltage operation Physi- cally and functionally the C and L devices are identical

3029001

Vendor:N/APackage Cooled:00+D/C:SOP-8

Unless specifically noted all references to the 80C186EB apply to the 80C188EB 80L186EB and 80L188EB References to pins that differ between the 80C186EB 80L186EB and the 80C188EB 80L188EB are given in parentheses The L in the part number denotes low voltage operation Physi- cally and functionally the C and L devices are identical

3029003

Vendor:STPackage Cooled:99+D/C:SOP-3.9-8P

(2) The technical information described in this book is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license.

3029003

Vendor:STPackage Cooled:99+D/C:SOP-3.9-8P

(2) The technical information described in this book is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license.

3029007

Vendor:SIPackage Cooled:SOP8D/C:08+

I2C Interface General Device Address I2C Registers and Subaddresses Naming Convention Direct Configuration Registers Write Direct Configuration Registers Read Direct Configuration Register DSP Core Access Protocol Run and Freeze Read Register (Code Ahex) Write Register (Code Bhex) Read D0 Memory (Code Chex) Short Read D0 Memory (Code C4hex) Read D1 Memory (Code Dhex) Short Read D1 Memory (...

3029007

Vendor:SIPackage Cooled:SOP8D/C:08+

I2C Interface General Device Address I2C Registers and Subaddresses Naming Convention Direct Configuration Registers Write Direct Configuration Registers Read Direct Configuration Register DSP Core Access Protocol Run and Freeze Read Register (Code Ahex) Write Register (Code Bhex) Read D0 Memory (Code Chex) Short Read D0 Memory (Code C4hex) Read D1 Memory (Code Dhex) Short Read D1 Memory (...

3029008

Single rectifier suited for switchmode power supply and high frequency DC to DC converters. Packaged in a surface mount packageD2PAK, this device is intended for use in high frequency in- verters, free wheeling and polarity protection appli- cations.

3029010

Vendor:SIPackage Cooled:SOP8D/C:08+

Switching Characteristics: • PEAK - PEAK jitter (66MHz): <120ps • PEAK - PEAK jitter (>100MHz): <75ps • CYCLE - CYCLE jitter (66MHz):<110ps • CYCLE - CYCLE jitter (>100MHz):<65ps • OUTPUT - OUTPUT skew: <100ps • Output Rise and Fall Time: 650ps - 950ps • DUTY CYCLE: 49.5% - 50.5%

3029015

Vendor:STPackage Cooled:SOPD/C:03+

n 3 IEEE 1149.1-compatible configurable local scan ports n Mode Register0 allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three n Transparent Mode can be enabled with a single instruction to conveniently buffer the backplane IEEE 1149.1 pins to those on a single local scan port n LSP ACTIVE outputs provide local port enable...

3029016

Vendor:SIPackage Cooled:SOP8D/C:08+

24421-009-DTS Rev ADQ# 2009 All technical information is believed to be accurate, but no responsibility is assumed for errors or omissions. Interpoint reserves the right to make changes in products or specifications without notice. HR300 Series is a trademark of Interpoint. Copyright © 1991 - 1999 Interpoint. All rights reserved.

3029017

Package Cooled:SO-8

This document contains advance information for the 3029017 microprocessor,includingelectrical characteristics and package pinout information. Detailed functional descriptions other than parametric performance are published in the i960® Jx Microprocessor Users Guide (272483).

3029018

Vendor:STPackage Cooled:SOP

NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement.

3029018

Vendor:STPackage Cooled:SOP

NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement.

3029019

Vendor:STPackage Cooled:SOPD/C:03+

As judged from expression (1), the turn-off time toff is affected by collector-base capacitance CC-B, D.C. current amplification factor hFE, and load resistance LR. In actual circuit design, CC-B and hFE are fixed. Accordingly, the turn-off time is significantly affected by the resistance of load RL.

3029020

Vendor:SIPackage Cooled:SOP8D/C:08+

If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the output port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low impedance paths that exist between the pin and either VDD or VSS.

3029021

Vendor:SIPackage Cooled:SOP8D/C:08+

‡ Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500 µs. All voltages are with respect to ground unless otherwise stated. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Power Suppl...

3029023

Vendor:STPackage Cooled:SOPD/C:03+

HIGH SPEED : fMAX = 70 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4020

3029023

Vendor:STPackage Cooled:SOPD/C:03+

HIGH SPEED : fMAX = 70 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4020