380HS004B1920A5

380HS109M1120TA6

380HS109M1512TA6

380HS109M1520TA6

380HS109M1720TA6

380HS109M1916TA6

380HW

Vendor:PHIPackage Cooled:QFN

380LB-1R2K

Vendor:TOKOPackage Cooled:3225-1R2KD/C:08+

High and low band filters are included to shape the amplitude and phase response of the transmit and receive signals and to provide compromise delay equalization as well as rejection of out-of-band signals. The transmit signal filtering corresponds to a &%%raisedcosinefrequencyresponse characteristic.

380LB-1R2K

Vendor:TOKOPackage Cooled:3225-1R2KD/C:08+

High and low band filters are included to shape the amplitude and phase response of the transmit and receive signals and to provide compromise delay equalization as well as rejection of out-of-band signals. The transmit signal filtering corresponds to a &%%raisedcosinefrequencyresponse characteristic.

380LB-1R5K

380LB-1R8K

Vendor:TOKOPackage Cooled:3225-1R8KD/C:08+

The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques.

380LB-1R8K

Vendor:TOKOPackage Cooled:3225-1R8KD/C:08+

The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques.

380LX103M035K022

380LX821M200K032

380NB-12NM

D/C:07+

The CD54AC112/3A and CD54ACT112/3A are dual J-K flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. These flip-flops have independent J, K, Set, Reset and Clock inputs and Q and Q outputs. The CD54AC112/3A and CD54ACT112/3A changes state on the negative-going transition of the clock. Set and Reset are accomplished asynchronously by low-level inp...

380NB-R47MP3

D/C:07+

OSC1 & OSC2: Oscillator programming pins. A resistor connects each pin to a timing capacitor. The resistor connected to OSC1 sets maximum on time. The resistor connected to OSC2 controls guaranteed off time. The combined total sets frequency with the timing capacitor. Frequency and maximum duty cycle are approximately given by:

38-1000/73220

38-1073

38112M

Package Cooled:SOP20D/C:05环保

3812N-7.0

Vendor:NSPackage Cooled:SMD-8

38133

D/C:08+/09+

The ISP1521 has seven downstream facing ports. If not used, ports 3 to 7 can be disabled. The vendor ID, product ID and string descriptors on the hub are supplied by the internal ROM; they can also be supplied by an external I2C-bus™ EEPROM or a microcontroller.

38134

D/C:08+/09+

3813A

Package Cooled:SOP-8D/C:N/A

The HCMOS MC68SEC000s static architecture is a direct replacement for the MC68EC000, which offers the lowest cost entry point to 32-bit processing. The internal 32-bit architecture provides fast and efficient processing that satisfies the requirements of sophisticated applications based on high-level languages.

3813D-1

Vendor:TIPackage Cooled:SOP-8

3813M-1.0

Vendor:NSPackage Cooled:SMDD/C:08+

Secondary-side control assumes that output voltage and current measurements are interfaced directly to an output ground-referenced PWM stage that develops the power switch command for the supply. This digital PWM command can then be transmitted to the primary-side power switch through a simple and low-cost isolating pulse transformer. With secondary-side control, it is much easier to monitor and control t...

3814-470

3814V

Vendor:N/APackage Cooled:150D/C:N/A

Test conditions unless otherwise noted. 1. T = 25ºC, Vsupply = +5 V, Frequency = 2650 MHz, in tuned application circuit. 2. 3OIP measured with two tones at an output power of +11 dBm/tone separated by 1 MHz. The suppression on the largest IM3 product is used to calculate the 3OIP using a 2:1 rule. 3. This corresponds to the quiescent current or operating current under small-signal conditions into pin...

381-54I

Package Cooled:99+

Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation.

381550-1

381-600

38172M4-067FG

Vendor:MITSUBISHIPackage Cooled:QFPD/C:95+

381740

3818PW

Package Cooled:SOP16D/C:06+

3819A

Package Cooled:SOP16D/C:06+

3819S33

This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. The transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable ...

3819S33

This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. The transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable ...

381AL

381BL

381CJ111

Figure 4 shows the sensor output signal relative to pres- sure input. Typical minimum and maximum output curves are shown for operation over 0 to 85C temperature range. The output will saturate outside of the rated pressure range. A fluorosilicone gel isolates the die surface and wire bonds from the environment, while allowing the pressure signal to be transmitted to the silicon diaphragm. The

381-N-50K-S

381NS100K

3820-0003-1A

(•) Pulse width limited by max. junction temperature (r) Include recovery losses on the STTA2006 freewheeling diode (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (**)Losses Include Also The Tail (Jedec Standardization)

3820-0013-1A

Inhibit*: This is an open-collector (open-drain) negative logic input that is referenced to GND. Pulling this pin to GND disables the modules output voltage. If Inhibit* is left open-circuit, the output will be active whenever a valid input source is applied.

3820-0018-00

Package Cooled:N/AD/C:08+

3820002100

3820-0021-00

Vendor:AFCPackage Cooled:03+D/C:PQFP-160P

From Detect Command or Application of PD to Port to Detect Complete Time to Measure PD Signature Resistance (Figure 2) From Successful Detect in Auto or Semiauto Mode to Class Complete From Classify Command in Manual (Figure 2) From Valid Detect to Port On in Auto Mode (Figure 2) From Port On Command to GATE Pin Current = IGON (Note 8)

3820-0021-00

Vendor:AFCPackage Cooled:03+D/C:PQFP-160P

From Detect Command or Application of PD to Port to Detect Complete Time to Measure PD Signature Resistance (Figure 2) From Successful Detect in Auto or Semiauto Mode to Class Complete From Classify Command in Manual (Figure 2) From Valid Detect to Port On in Auto Mode (Figure 2) From Port On Command to GATE Pin Current = IGON (Note 8)

3820-0029

Vendor:AFCPackage Cooled:BGAD/C:N/A

3820217120530

38215000000

Vendor:LittelfuseD/C:08+

38215000000

Vendor:LittelfuseD/C:08+

3-821665-1

Vendor:AMP/TYCOD/C:N/A

3-822269-1

Vendor:AMP/TYCOD/C:0019+

TypeDescription P3.3 volt input supply voltage. P5.0 volt reference for 5.0 volt signaling environments and 3.3 volt reference for 3.3 volt signaling environments. PGround Pin I/OThe PCI address and data lines are multiplexed on the same PCI pins. During the first clock cycle of a transaction, the 32 bits contain an address and during subsequent clock cycles, they contain data. Both read and write burs...

3-822270-1

3-822273-1

Vendor:AMPD/C:96+

The DTMF generator controls the sending of the sixteen standard DTMF tone pairs. The tone pair sent is determined by selecting transmit DTMF (bit D4) and the 4 DTMF bits (D0-D3) of the Tone Register. Transmission of DTMF tones from TXA is gated by the transmit enable bit of CR0 (bit D1) as with all other analog signals.

3-822275-1

Vendor:AMP/TYCOD/C:9701

The KS8721BL/SL automatically configures itself for 100Mbps or 10Mbps and full- or half-duplex operation, using an on-chip auto-negotiation algorithm. Combined with Auto MDI/MDIX for automatic correction and detec- tion of crossover and straight-through cables, the KS8721BL/SL provides an easy-to-use, high performance solution for 10BASE-T, 100BASE-TX, and 100BASE-FX applications.

3-822279-1

The circuit accommodates any type of LBO output (active high or active low). Supply current drawn by IC1 is typically 35µA when active and only 0.05µA while in shutdown. The circuit's small size, low power consumption, and low cost are ideal for battery-powered systems.

3-822279-1

The circuit accommodates any type of LBO output (active high or active low). Supply current drawn by IC1 is typically 35µA when active and only 0.05µA while in shutdown. The circuit's small size, low power consumption, and low cost are ideal for battery-powered systems.

3-822472-1

Vendor:AMP/TYCOD/C:00+

3-822472-3

Vendor:AMPPackage Cooled:N/AD/C:3290

The Programmable Interconnect Matrix (PIM) connects the two logic blocks on the CY7C371i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM.

38224724

Note 2: The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. Note 3: SC70-packaged parts are 100% tested at +25C. Limits across the full temperature range are guaranteed by design and correlation. Note 4: Flatness is defined as the difference between the maximum and minimum values of on-resistance as measured over the spe...

3-822472-4

Vendor:AMPPackage Cooled:418D/C:2662

• Generation 4 IGBT technology • Standard: Optimized for minimum saturation voltage and operating frequencies up to 10kHz • Very low conduction and switching losses • HEXFRED™ antiparallel diodes with ultra- soft recovery • Industry standard package • UL approved

3-822498-1

Vendor:TYCO(AMP)D/C:1186

Format to Freescale look-and-feel; Clarified RTI clock sources and other changes in Chapter 5; updated ICG initialization examples; expanded descriptions of LOLS and LOCS bits in ICGS1; updated ICG electricals Table A-9 and added a figure

3-822498-1

Vendor:TYCO(AMP)D/C:1186

Format to Freescale look-and-feel; Clarified RTI clock sources and other changes in Chapter 5; updated ICG initialization examples; expanded descriptions of LOLS and LOCS bits in ICGS1; updated ICG electricals Table A-9 and added a figure

3-822499-3

Vendor:AMPD/C:08+

Generates clocks for OC-3, STM-1, DS3, E3, DS2, DS1, E1, 19.44 MHz and ST-BUS Meets jitter generation requirements for STM-1, OC-3, DS3, E3, J2 (DS2), E1 and DS1 interfaces Compatible with GR-253-CORE SONET stratum 3 and G.813 SEC timing compliant clocks Provides hit-less reference switching Detects frequency of both reference clocks and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz and 19...

3-822516-1

Vendor:AMPD/C:07+

The output voltage of the PT6520 series of integrated switching regulators (ISRs) may be adjusted higher or lower than the factory trimmed pre-set voltage with the addition of a single external resistor. 1 Table 1 gives the allowable adjustment range for each model in the series as Va (min) and Va (max).

3-822516-7

Vendor:AMPD/C:05+

The CY7C245A is a CMOS electrically programmable read only memory organized as 2048 words x 8 bits and is a pin-for-pin replacement for bipolar TTL fusible link PROMs. The CY7C245A incorporates a D-type, master-slave register on chip, reducing the cost and size of pipelined micropro- grammed systems and applications where accessed PROM data is stored temporarily in a register. Additional flexibility is...

3-822516-7

Vendor:AMPD/C:05+

The CY7C245A is a CMOS electrically programmable read only memory organized as 2048 words x 8 bits and is a pin-for-pin replacement for bipolar TTL fusible link PROMs. The CY7C245A incorporates a D-type, master-slave register on chip, reducing the cost and size of pipelined micropro- grammed systems and applications where accessed PROM data is stored temporarily in a register. Additional flexibility is...

3823150-2

3824454-2

38250 (1159J)

382575-2

Package Cooled:07+D/C:6082

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

3826C

Vendor:TD/C:08+

38279(9P-50594B)

Vendor:HARPackage Cooled:03+D/C:QFP

Signal Operation tpd = 3.6 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) ESD Protection Exceeds 5000 V With Human-Body Model

38279-9P-50594B

Vendor:INTERSILPackage Cooled:QFP1420-80D/C:03+/04+

The ML9266 is a small, high efficiency, and low voltage step-up DC/DC converter with an Adaptive Current Mode PWM control loop, includes an error amplifier, ramp generator, comparator, switch pass element and driver in which providing a stable and high efficient operation over a wide range of load currents. It operates in stable waveforms without external compensation. The low start-up input voltage...

382799P-50594B

Package Cooled:QFP

This device is ideal for applications requiring level translation. When operated from a 3.3 V supply, level translation from 3.3 V inputs to 2.5 V outputs occurs. Similarly, if the device is operated from a 2.5 V supply and 2.5 V inputs are applied, the device will translate the outputs to 1.8 V. In addition to this, the 382799P-50594B has a level translating select pin (SEL). When SEL is low, VCC is re...

382811-5

Vendor:AMP/TYCOD/C:N/A

RESET is asserted and the condition is latched until VHTH > VTH. Reset (Output): Push-pull output. This output is asserted and latched when VLTH <VTH, indicating a low voltage condition. This state remains latched until VHTH > VTH. The polarity of this signal (active-high or low) is determined by the part number suffix. See ordering information. Power Supply (Input): Independent supply input for inte...

382823-6

Vendor:AMP/TYCOD/C:99+

382881-1

38293

382AL/CL

Vendor:TELEDYD/C:O9+

Function DAC1 Lch Negative Analog Output Pin DAC1 Lch Positive Analog Output Pin Zero Input Detect 3 Pin Zero Input Detect 2 Pin Zero Input Detect 1 Pin Chip Address 0 Pin Auto Setting Mode Disable Pin (Pull-down Pin) L: Auto Setting Mode, H: Manual Setting Mode Power-Down Mode Pin When at L, the 382AL/CL is in the power-down mode and is held in reset. The 382AL/CL should always be reset upo...

382CL

Vendor:634Package Cooled:TELEDYNE

38304

Vendor:PARADISEPackage Cooled:08+D/C:800

The GRP has as its inputs the outputs from all of the Twin GLBs and all of the inputs from the bidirectional I/O cells. All of these signals are made available to the inputs of the Twin GLBs. Delays through the GRP have been equal- ized to minimize timing skew and logic glitching.

38304

Vendor:PARADISEPackage Cooled:08+D/C:800

The GRP has as its inputs the outputs from all of the Twin GLBs and all of the inputs from the bidirectional I/O cells. All of these signals are made available to the inputs of the Twin GLBs. Delays through the GRP have been equal- ized to minimize timing skew and logic glitching.

38305

Vendor:PARADISEPackage Cooled:08+D/C:800

38315B

Vendor:PARADISEPackage Cooled:08+D/C:800

These devices consist of two independent voltage comparators that are designed to operate from a NC − No internal connectionsingle power supply over a wide range of voltages. Operation from dual supplies also is possible as long as the difference between the two supplies is 2 V to 36 V, and VCC is at least 1.5 V more positive than the input common-mode voltage. Current drain is independent of ...

383-2SUBC/C470/S400-A5

383-2SUBC/C470/S400-A6

383-2SURC/S530-A3

383-2SURC/S530-A5

383-2UBGC/S400-A5

383-2USOC/S400-A7

383-2USOC/S530-A4

3832USOCS530A4

383-2UYC/S400-A6

383-2UYC/S400-A8

3832UYCS400A6

3832UYCS530A3

3832UYCS530A5

38331-8204