4116R-001-821

The OPA681 sets a new level of performance for broadband current feedback op amps. Operating on a very low 6mA supply current, the OPA681 offers a slew rate and output power normally associated with a much higher supply cur- rent. A new output stage architecture delivers a high output current with minimal voltage headroom and crossover distortion. This gives exceptional single-supply operation. Using ...

4116R002

The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switch- ing network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up opera...

4116R-002

Vendor:N/APackage Cooled:50D/C:N/A

SYSTEM ERROR is used for reporting address parity errors data parity errors on the Special Cycle command or any other system error where the result will be castrophic When reporting address parity errors SERR is an output When reporting data parity errors for the Special Cycle command SERR is an output during writes and an input during needs

4116R002102

4116R-002-103

Vendor:BOURNSPackage Cooled:06+D/C:500

The AD5382 is a complete, single-supply, 32-channel, 14-bit DAC available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operation. The AD5382 includes an internal software-selectable 1.25 V/ 2.5 V, 10 ppm/C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output am...

4116R002104

4116R-002-104

(a full wave circuit has twice these efficiencies) As the frequency of the input signal is increased, the reverse recovery time of the diode (Figure 9) becomes significant, resulting in an increase ac voltage component across RL which is opposite in polarity to the forward current, thereby reducing the value of the efficiency factor ∂, as shown on Figure 10. It should be emphasized that Figure ...

4116R002153

4116R-002-203

4116R-002-271

4116R-002-331

4116R-002-472

Vendor:BOURNS NETWORKSPackage Cooled:DIP-16D/C:9309

11CPDPower Dissipation Capacitance (Note 6)pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the noCload dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.

4116R-002-620

4116R-003

Vendor:N/APackage Cooled:30D/C:N/A

The ispLSI 2096VL is a High Density Programmable Logic Device containing 96 Registers, six Dedicated Input pins, three Dedicated Clock Input pins, two dedi- cated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096VL fea- tures in-system programmability through the Boundary Scan Test Access Port (TAP) and is ...

4116R-003

Vendor:N/APackage Cooled:30D/C:N/A

The ispLSI 2096VL is a High Density Programmable Logic Device containing 96 Registers, six Dedicated Input pins, three Dedicated Clock Input pins, two dedi- cated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096VL fea- tures in-system programmability through the Boundary Scan Test Access Port (TAP) and is ...

4116R-003/221/331

Vendor:BOURNS NETWORKSPackage Cooled:DIP-16D/C:88

4116R-003-221/331

4116R1102

4116R-1-220

Vendor:BOURNSD/C:07+

4116R-1-221

Vendor:BOURNSD/C:07+

4116R-2-103

Vendor:DALEPackage Cooled:PDIP16D/C:00+

This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparator...

4116R-2-391

4116R-2-472

4116R-2-473

Vendor:DALEPackage Cooled:PDIP16D/C:03+

4116R-47K

4116R-58K

4116R-7L1-330

4116RBF1680

4116R-BY1-000

D/C:3567

4116R-F69-104

4116R-F69-330

Vendor:BOURNSPackage Cooled:DIP-16D/C:9808

The CY7B9950 RoboClock is a low-voltage, low-power, eight-output, 200-MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high-performance computer and communication systems.

4116R-F70-102

Vendor:BOURNSPackage Cooled:41D/C:4000

3.3-V power. I/O 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended.

41-170361-01

4118847-30

4119400-36

4119-50

4119N

Package Cooled:QFND/C:06+

Many products that connect to phone lines (modems, for instance) incorporate a "call- progress monitoring" function known as CPM. CPM circuits "listen" to the lines as a human would, and respond according to what they "hear." You shouldn't dial a number unless you first hear a dial tone, for example. Neither should your computer.

4119N

Package Cooled:QFND/C:06+

Many products that connect to phone lines (modems, for instance) incorporate a "call- progress monitoring" function known as CPM. CPM circuits "listen" to the lines as a human would, and respond according to what they "hear." You shouldn't dial a number unless you first hear a dial tone, for example. Neither should your computer.

411D-26PL

Vendor:TELEDYNEPackage Cooled:CAND/C:203

411D-26WL

Vendor:TELEDYNEPackage Cooled:CAND/C:256

411D-5

411D-5L

Vendor:TELEDYNEPackage Cooled:CAND/C:245

411D-6PL

Vendor:TELEDYNEPackage Cooled:CAND/C:203

411DD-26WL

Vendor:TELEDYNEPackage Cooled:CAND/C:256

411DD-26WM

Vendor:TELEDYNEPackage Cooled:CAND/C:245

411DM3-26P

Vendor:TELEDYNEPackage Cooled:CAND/C:245

411DOTQFI-06

Vendor:SCMPackage Cooled:06+D/C:800

411GR-001-100

Package Cooled:20D/C:DIP-16

411M-01L

Vendor:ICSPackage Cooled:SOP-3.9-8PD/C:6+

The electrical characteristic data has been developed from actual products tested at 25C. This data is considered typical for the converter. Applies to Figure 1, Figure 2, and Figure 3. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 100 mm x 100 ...

411PP0410A

• High performance ferrite core is used in this epoxy conformally coated choke which allows for inductance values to 1000µH. • Axial lead type, small lightweight design. • Special magnetic core structure contributes to high Q and self-resonant frequencies. • Treated with epoxy resin coating for humidity resistance to ensure long life. • Heat resistant adhesives and ...

411T-26PP

Vendor:TELEDYNEPackage Cooled:CAND/C:245

411T-26WL

Vendor:TELEDYNEPackage Cooled:CAND/C:236

411T-5PP

Vendor:TELEDYNEPackage Cooled:CAND/C:245

412-020

41203

41203

41205-901

Vendor:ICCPackage Cooled:08+D/C:800

This is both the power and analog ground for the IC. Note that both pin three and the tab of the TO-220 and TO-263 packages are at ground potential. Pin three and the tab should be tied together using the PC board copper trace material and connected to circuit ground.

41205-901

Vendor:ICCPackage Cooled:08+D/C:800

This is both the power and analog ground for the IC. Note that both pin three and the tab of the TO-220 and TO-263 packages are at ground potential. Pin three and the tab should be tied together using the PC board copper trace material and connected to circuit ground.

41205-901YL

Package Cooled:9850D/C:861

412077ISSB

Transmitter Underrun: TxU is asserted during a transmit sequence when the service of TxBE has been delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line fill depends on PCSAR11. TxU is reset by RESET or setting of TSOM (TDSR8), synchronized by the falling edge of TxC.

412077Q16TC

Vendor:ZETEXPackage Cooled:SSOP16D/C:9817

Octal Framer supporting T1, E1 and J1 Formats Provides programmable system interface to support Mitel® ST- bus, AT&T® CHI and MVIP bus, supporting data rates of 1.544 / 2.048 / 8.192Mb/s; up to four links can be byte interleaved on one system bus without external logic Provides up to three internal floating HDLC controllers for each framer to support ISDN PRI and V5.X interface. Each HDLC co...

412077Q16TC

Vendor:ZETEXPackage Cooled:SSOP16D/C:9817

Octal Framer supporting T1, E1 and J1 Formats Provides programmable system interface to support Mitel® ST- bus, AT&T® CHI and MVIP bus, supporting data rates of 1.544 / 2.048 / 8.192Mb/s; up to four links can be byte interleaved on one system bus without external logic Provides up to three internal floating HDLC controllers for each framer to support ISDN PRI and V5.X interface. Each HDLC co...

412078

Vendor:ISSPackage Cooled:SSOP20

Byte Write Following the start signal from the master, the slave address is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle.

412078

Vendor:ISSPackage Cooled:SSOP20

Byte Write Following the start signal from the master, the slave address is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle.

412078ISS

Package Cooled:SSOP24

412090

Package Cooled:08+D/C:15000

This protection function is splitted in 2 stages. As shown in Figure A3, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Vout level.

412090

Package Cooled:08+D/C:15000

This protection function is splitted in 2 stages. As shown in Figure A3, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Vout level.

412090ISS

Package Cooled:SMD

n 5 Volt Read, Program, and Erase C Minimizes system-level power requirements n High Performance C Access times as fast as 70 ns n Low Power Consumption C 15 mA typical active read current C 30 mA typical program/erase current C 5 µA maximum CMOS standby current n Compatible with JEDEC Standards C Package, pinout and command-set compatible with the single-supply Flash device standa...

412090ISSB

Package Cooled:SSOP20

412090ISSB

Package Cooled:SSOP20

4120I

Vendor:TIPackage Cooled:SOP8D/C:06+

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or writ...

4120N

Vendor:ONSPackage Cooled:QFN8

• Floating High Side Driver with boot-strap Power supply along with a Low Side Driver. • Fully operational to 650V • 50V/ns dV/dt immunity • Gate drive power supply range: 10 - 35V • Undervoltage lockout for both output drivers • Separate Logic power supply range: 3.3V to VCL • Built using the advantages and compatibility of CMOS and IXYS HDMOSTM processes R...

4120R-001-682

Vendor:PANASONICPackage Cooled:DIPD/C:08+

This device is another member of Broadcom's 0.13µ Gigabit copper PHY family, joining the BCM5404, BCM5414, BCM5421, BCM5421S, BCM5424, BCM5434, BCM5464, and BCM5464S. The 0.13µm process is the optimal process that offers the best performance, lowest cost, and lowest power for Gigabit copper solutions. Further, devices based on the 0.13µ process offer an excellent long-term cost curve, ...

4120R-003

Vendor:N/APackage Cooled:30D/C:N/A

4120R-601-250/500

412-1

412-12L

Vendor:TELEDYNEPackage Cooled:CAND/C:203

412-12W

Vendor:TELEDYNEPackage Cooled:TO8D/C:74+

412-18L

Vendor:TELEDYNEPackage Cooled:CAND/C:1002

4121C

Vendor:9000D/C:SMD8

RSENSE A - Is the connection for the bottom of the A half bridge. This can have a sense resistor connection to the V+ return ground for current limit sensing, or can be connected directly to ground. The maximum voltage on this pin is 2 volts with respect to GND.

4121I

Vendor:TIPackage Cooled:SMD8D/C:01+

Dynamic-VID technology allows on-the-fly VID changes with controlled, glitch-less output. Additionally, short-circuit protection, adjustable current limiting, over-voltage protec- tion and power-good circuitry combine to ensure reliable and safe operation. The operating temperature range is 0oC to +85oC and the operating voltage is a single +12V supply, simplifying design. The FAN53168 is availab...

4121I

Vendor:TIPackage Cooled:SMD8D/C:01+

Dynamic-VID technology allows on-the-fly VID changes with controlled, glitch-less output. Additionally, short-circuit protection, adjustable current limiting, over-voltage protec- tion and power-good circuitry combine to ensure reliable and safe operation. The operating temperature range is 0oC to +85oC and the operating voltage is a single +12V supply, simplifying design. The FAN53168 is availab...

412-26L

Vendor:TELEDYNEPackage Cooled:CAND/C:1002

41235-1

During power-on, RESET is asserted when VDD reaches 1 V. After minimum VDD ( 2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE)) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time, td, is determined by an external capacitor: ...

412-430

Package Cooled:模块

412460

Vendor:IRPackage Cooled:DIP-4D/C:n/a

41-25

Vendor:'TIPackage Cooled:07+D/C:'SOP8

Members of the Texas Instruments Widebus™ Family Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacin...

41-25

Vendor:'TIPackage Cooled:07+D/C:'SOP8

Members of the Texas Instruments Widebus™ Family Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacin...

41254

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property o...

41256

Package Cooled:DIP

The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage.

41256-12

Vendor:DIP-16Package Cooled:SIENENSD/C:04+

Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Q0−8) go LOW tRSF after the rising edge of RS. In order for the FIFO to reset to its default state, the user must not read or write while RS is LOW. All flags are guaranteed to be valid tRSF after RS is taken LOW.

41256-12PSZ

Test Condition: 1.0KHz / 1V. Electrical specifications at 25C. Temperature Rise: 40C. Operating temperature: -20C TO +105C. Insulation Resistance: 100M OHMS at 500VDC. Rated Voltage: 100V to 270V / 50-60 Hz. Hi-Pot Voltage: 1500VAC for one minute.

41256-15

The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM which is configured as 64/128/256 registers by 16 bits. Each register can be written (or read) serially by using the DI (or DO) pin. The CAT64LC10/20/40 is manufactured using Catalysts advanced CMOS

41256-212141302

Vendor:NECPackage Cooled:DIPD/C:87+

-48V/-24V Input Active ORing for carrier class communication equipment Reverse input polarity protection for DC-DC power supplies 24V/48V output active ORing for redundant AC-DC rectifiers Low output voltage (12V, 5V, 3.3V...) active ORing for redundant DC-DC and AC-DC power supplies Active ORing of multiple voltage regulators for redundant processor power

41256A

41256A-12JS

41256AJ-08

41256AJ-12

41257AL-08

412-5L

Vendor:TELEDYNEPackage Cooled:CAND/C:1235