4.9152M

Vendor:KDSPackage Cooled:20.6×12.6D/C:DIP 4P

The SM5009 series are crystal oscillator module ICs that incorporate low crystal current type oscillating circuit to limit oscillator-stage current, so that they can reduce crystal current lower than the existing products. Since the oscillating circuit has oscillator capacitors with excellent frequency response and feedback resistor built-in, just connecting crystal realizes stable fundamental oscillation re...

4.9152MHZ

Vendor:1200

When used as a position Auto Shut-Off module, several timing options are available. All timings are derived from the on chip oscillator and have thus the same tolerance. Three different time delays can be defined: the horizontal shut-off (TH), the vertical shut-off (TV) and the down shut-off (TD).

4.9152MHZ/1AV4V10B5980G

4.96E08

4/4AT613324JFEMELLE

4/555/

Vendor:ANS

4/555/900/01C

Vendor:ESZPackage Cooled:DIP

4/555/920/02A

Vendor:AMSPackage Cooled:96D/C:DIP-28

4/555/950/01A

Vendor:AMISPackage Cooled:02+D/C:PLCC-68P

4/555/970/01A

Vendor:AMISPackage Cooled:04+D/C:PLCC-44P

4/555/970/02A

40.000000MHZ

Vendor:——Package Cooled:DIP14晶振D/C:9106+

For M74HC4020 twelve kind of divided output are provided; 1st and 4th stage to 14th stage. The maximum division available at last stage is 1/16384 x fIN at clock. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

40.000000MHZ

Vendor:——Package Cooled:DIP14晶振D/C:9106+

For M74HC4020 twelve kind of divided output are provided; 1st and 4th stage to 14th stage. The maximum division available at last stage is 1/16384 x fIN at clock. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

40.0000C

40.0000MHZ

Vendor:n/aD/C:2000

To obtain the lowest jitter clock drive, a low-phase-noise sine-wave source can be AC- or DC-coupled into a single clock input. The MAX104 can accommodate clock amplitudes up to 1V (2V peak-to-peak) with the clock-termination return connected to ground. The dynamic performance of the ADC is essentially unaffected by clock signal amplitudes from 100mV to 1V.

40.000M

Vendor:/Package Cooled:/D/C:/

NOTES: (1) LSB means Least Significant Bit. One LSB for the 10V input range is 4.88mV. (2) Typical rms noise at worst case transition. (3) As measured with fixed resistors shown in Figure 7b. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of CFull Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (no...

40.000M

Vendor:/Package Cooled:/D/C:/

NOTES: (1) LSB means Least Significant Bit. One LSB for the 10V input range is 4.88mV. (2) Typical rms noise at worst case transition. (3) As measured with fixed resistors shown in Figure 7b. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of CFull Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (no...

40.000MHZ

Vendor:OCOPackage Cooled:9905D/C:251

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

40.00MHZ

The CS61880 makes use of ultra low power matched im- pedance transmitters and receivers to reduce power beyond that achieved by traditional driver designs. By achieving a more precise line match, this technique also provides superior return loss characteristics. Additional- ly, the internal line matching circuitry reduces the external component count. All transmitters have controls for independent po...

40.016000MHZ-VF155

40.0400MHZ

40.040MHZ

40.052

40.209

40.31-9024-0001

Vendor:finderPackage Cooled:原装D/C:08+

40.500M

Vendor:KDSPackage Cooled:20.6×12.6D/C:DIP 4P

40.512

Vendor:ALTECH CORP.D/C:N/A

40.5504MHZHC-18

40.5504MHZHC-49

40.61-24V

Vendor:finderPackage Cooled:原装D/C:08+

400 CFX 10M(10X20)

400 LOOP

400 PCB CABLE

400 PD

4000-0002

400-00009-00

400000C

Package Cooled:93D/C:DIP

The DS2250(T) Soft Microcontroller Module is a fully 8051-compatible 8-bit CMOS microcontroller that offers softness in all aspects of its application. This is accomplished through the comprehensive use of nonvolatile technology to preserve all information in the absence of system VCC. The internal program/data memory space is implemented using 8, 32, or 64 kbytes of nonvolatile CMOS SRAM. Furthermore, ...

400-00211

40000MHZ

Vendor:N/APackage Cooled:9804D/C:25

DC Tests TC = +250C, 1 Cycle, t = 1.0 s Test 1 VCE = 7.8 Vdc, IC = 15 Adc Test 2 VCE = 70 Vdc, IC = 1.67 Adc Switching Tests TA = +250C; duty cycle 10%; RS 0.1 Ω Test 1 tP = 5.0 ms; RBB1 = 2.0 Ω; VBB1 10 Vdc; RBB2 = 100 Ω; VCC 10 Vdc; VBB2 = 1.5 Vdc; IC = 15 Adc Test 2 tP = 20 ms; RBB1 = 30 Ω; VBB1 10 Vdc; RBB2 = 100 Ω; VCC 10 Vdc; VBB2 = 1.5 Vdc; IC = 3.8 Adc

40003

Vendor:N/APackage Cooled:MSOP8D/C:06+

sGENERAL DESCRIPTION The 40003 series is a serial I/O real time clock suitable for 4 bits microprocessor. It contains quartz crystal oscillator, counter, shift register, voltage regulator, voltage detector and interface controller. The 40003 series required only 4-port of microprocessor for data transfer, and the microprocessor can receive the data at any time when the microprocessor requires. The op...

4000309

4000319

4000341

400040

400-062BGVREVF

40-0083-001

4000L0YBQO

Package Cooled:N/AD/C:08+

4000L8YTQ8

Vendor:intelPackage Cooled:BGA

4000LOYTQ0

Vendor:intelPackage Cooled:BGAD/C:05+

Clock from I2C bus. Depending on the value set for OM bit this pin enable/disable the internal 22KHz tone generator (OM=0) or switch the output voltage from 13V to 18V and vice versa (OM=1) 22kHz Tone Detector Input. Must be AC coupled to the DiSEqC 2.0 bus. Open drain output of the tone Detector to the main µcontroller for DiSEqC 2.0 data decoding. It is set LOW when a 22 KHz tone is detected....

4000LOZBQ0

Vendor:intelPackage Cooled:BGAD/C:05+

4001006

4001010

4001025

4001049

4001056

4001058

4001068

4001072

4001076

4001077

4001082

4001090

4001100

4001102

4001112

4001113

4001115

4001146

4001223

400125

40-0130-002

Vendor:3COMPackage Cooled:30D/C:N/A

This document describes part-number-specific changes to recommended operating conditions and revised electrical specifications, as applicable, from those described in the general MPC7455 RISC Microprocessor Hardware Specifications (Order No. MPC7455EC). The MPC7455 is a PowerPC™ microprocessor.

40-0130-003

Vendor:PARALLELTASKINGPackage Cooled:30D/C:N/A

A four-wire (SCLK, MOSI, MISO, SS) SPI interface is provided for ISD5008 control, addressing func- tions, and sample rate selection. The ISD5008 is configured to operate as a peripheral slave de- vice with a microcontroller-based SPI bus inter- face. Read/Write access to all the internal registers occurs through this SPI interface. An interrupt sig- nal (INT) and internal read-only Status Register ar...

40-0130-004

Vendor:SCOMPackage Cooled:30D/C:N/A

A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit eliminates the prop delay that would be added by the STA111 LSPN logic between TDIn and TDO(n+1) or TDOB by buffering and synchronizing the LSP TDI inputs to the falling edge of TCKB, thus allowing data to be scanned at higher frequencies without violating set-up and hold times.

40-0130-004

Vendor:SCOMPackage Cooled:30D/C:N/A

A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit eliminates the prop delay that would be added by the STA111 LSPN logic between TDIn and TDO(n+1) or TDOB by buffering and synchronizing the LSP TDI inputs to the falling edge of TCKB, thus allowing data to be scanned at higher frequencies without violating set-up and hold times.

40014

40-0148-002

40014BDC

Vendor:FPackage Cooled:CDIP

40014BDM

Vendor:FPackage Cooled:DIP14陶瓷D/C:83+

40014PC

40016KFB-SS

Package Cooled:BGA

The ST70138 is supplied in two packages, TQFP144 and LBGA80. The ST70138T packaged in TQ144 is a pin-to-pin compatible version of the ST70137 enabling manufacturers to benefit direct- ly from the cost and performance advantages that the ST70138 brings. The TQ144 flavor brings out both the USB and PCI interfaces. Supplied in a compact USB-only LBGA80 package, the ST70138B brings addition- al cost a...

400180A

Vendor:12Package Cooled:MICROCHIPD/C:N/A

NOTES: 1. See Test Conditions under TEST CIRCUITS AND WAVEFORMS. 2. This parameter is guaranteed but not production tested. 3. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.2ns at CL = 50pF. Since this time constant is much smaller than the rise and fall times ...

400180A

Vendor:12Package Cooled:MICROCHIPD/C:N/A

NOTES: 1. See Test Conditions under TEST CIRCUITS AND WAVEFORMS. 2. This parameter is guaranteed but not production tested. 3. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.2ns at CL = 50pF. Since this time constant is much smaller than the rise and fall times ...

40-0196

Vendor:3COMPackage Cooled:50D/C:N/A

Max. UnitsConditions CCCVVGS = 0V, ID = 250µA CCC V/C Reference to 25C, ID = 1mA 0.065VGS = 10V, ID = 3.1A R mΩ 0.080VGS = 5.0V, ID = 2.5A R 2.0VVDS = VGS, ID = 250µA CCCSVDS = 25V, ID = 1.9A 25VDS = 55V, VGS = 0V µA 250VDS = 44V, VGS = 0V, TJ = 125C 100VGS = 16V nA -100VGS = -16V 17ID = 1.9A CCCnC VDS = 44V CCCVGS = 10V CCCVDD = 28V R CCCID = 1.9A ns CCCRG = 24Ω...

4001AEF

(1) Lead Forming When forming leads, the leads should be bent at a point at least 3mm from the base of the epoxy bulb. Do not use the base of the leadframe as a fulcrum during lead forming. Lead forming should be done before soldering. Do not apply any bending stress to the base of the lead. The stress to the base may damage the LEDs characteristics or it may break the LEDs. When mounting the LEDs ...

4001B

Vendor:ROHMPackage Cooled:DIPD/C:1991

Register oriented 8/16 bit CORE with RUN, WFI, SLOW, HALT and STOP modes 0 - 24 MHz Operation (internal Clock), 4.5 - 5.5 Volt voltage range PLL Clock Generator (3-5 MHz crystal) -40oC to 105oC or -40oC to 85oC temperature range Minimum instruction time: 83 ns (24 MHz internal clock) Internal Memory: Single Voltage FLASH up to 128 Kbytes, RAM 1.5 to 4 Kbytes, EEPROM 512 to 1K bytes 224 general...

4001BC

Vendor:NECPackage Cooled:DIPD/C:1987

The 50% point of sync is determined by using two identical resistors to divide the voltage between sync tip and back porch. The importance of precision sync tip clamping may be appreciated here, since the sync tip voltage is used in deriving the 50% slicing level. The back porch voltage is derived through an internal integrate and hold circuit that is gated by the Back Porch output signal. By integrating over...

4001BC/883

Package Cooled:DIP

Undervoltage lockout monitors supply voltage (VDD), the precision reference (REF), input line voltage (LINE), and the shutdown comparator (SHTDWN). If after any of these four have sensed a fault condition, recovery to full operation is initiated with a soft start. VDD thresholds, on and off, are 15V and 8.5V for the -2 and -4 versions, 9V and 8.5V for the -1 and -3 versions.

4001BCA

4001BCL

For applications that require no external memory or temporarily no external memory: the ALE output signal (pulses at a frequency of 1⁄6 fOSC) can be disabled under software control (bit RFI; SFR: PCON.5); if disabled, no ALE pulse will occur. ALE pin will be pulled down internally, switching an external address latch to a quiet state. The MOVX instruction will still toggle ALE (external Data M...

4001BCN

Output pins OUTH and OUTL are connected to input pins VH and VL respectively, depending on the status of the IN pin. One of the output pins is always in tri-state, except when the OE pin is active low, in which case both outputs are in tri-state mode. The isolation of the out- put FETs from the power supplies enables VH and VL to be set independently, enabling level-shifting to be implemented.

4001BDC

Vendor:FPackage Cooled:05+D/C:2035

4001BDM

Vendor:FPackage Cooled:DIP14陶瓷D/C:83+

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. If Military/ Aerospace specified devices are required, please contact the National semiconductor Sales/Office/Distributors for availability and specifications.

4001BDMQB

Vendor:NS

4001BF

Receive Data Valid: This indicates that the external PMD is presenting recovered and decoded nibbles on the RXD signals, and that RX_CLK is synchronous to the recovered data in 100 Mb/s operation. This signal will encompass the frame, starting with the Start-of-Frame delimiter (JK) and excluding any End-of-Frame delimiter (TR).

4001BK

Specifications 20 Watts 2.25 Watts 5.9 C/W 0.1-9.1 Ω E12 100 ppm/C 5% (J) -55C to+155C 500V or P.R 2000 Volts AC ∆R +/-(1.0 %+0.05 Ω) ∆R +/- (1.0 %+0.05 Ω) ∆R +/- (0.25 %+0.05 Ω) ∆R +/- (0.1 %+0.05 Ω) Over 95% of surface Over 1,000 MΩ ∆R +/- (0.25 %+0.05 Ω)

4001BPC

terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal.

4001BS

Vendor:PanasonicPackage Cooled:SOP14SD/C:2007+

• Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential...

4001K-2C

Vendor:FUJD/C:07/08+

The amplitude of start pulse öst is the same as the ö1 and ö2 pulses. The shift register starts the scanning at the High level of öst, so the start pulse interval determines the length of signal accumulation time. The öst pulse must be held High at least 200 ns and overlap with ö2 at least for 200 ns. To operate the shift register correctly, ö2 must change from the H...

4001P

Vendor:HARRISPackage Cooled:DIP-8

4001P-2

Vendor:N/APackage Cooled:30D/C:N/A

The BS62LV1024 is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 words by 8 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.02uA and maximum access time of 70ns in 3V operation. Easy memory expansion is provided by...