Index "4"Vendor:FAIRCHILDPackage Cooled:SOP-8
D/C:22500
The signal-detect output is positive LVTTL logic. A logic low at this output indicates that the optical signal into the receiver has been interrupted or that the light level has fallen below the minimum signal detect threshold. This output should not be used as an error rate indica- tor since its switching threshold is determined only by the magnitude of the incoming optical signal.
3. Always set IOCC PAGE1 bit 0 = 1 otherwise partial ADC function cannot be used. 4. Please do not switch MCU operation mode from normal mode to sleep mode directly. Before into sleep mode, please switch MCU to green mode. 5. While switching main clock (regardless of high freq to low freq or on the other hand), adding 6 instructions delay (NOP) is required. 6. Offset voltage will effect ADCs result, ple...
The TLE 4476 is a monolithic integrated voltage regulator providing two output voltages, Q1 is a 3.3 V output for loads up to 350 mA and Q2 is a 5 V output providing 430 mA. The device is available in the P-TO252-5-1 (D-PAK) package. Output 2 can be switched ON/OFF via the Enable input EN.
The AD8029/AD8030/AD8040 provide excellent signal quality with minimal power dissipation. At G = +1, SFDR is C72 dBc at 1 MHz and settling time to 0.1% is only 80 ns. Low distortion and fast settling performance make these amplifiers suitable drivers for single-supply A/D converters.
D/C:32000
NOTES: 1. Dimensions are in inches. Metric equivalents are given for general information only. 2. Beyond radius (r) maximum, j shall be held for a minimum length of 0.011 (0.028 mm). 3. Dimension k measured from maximum HD. 4. Outline in this zone is not controlled. 5. Dimension CD shall not vary more than 0.010 (0.25 mm) in zone P. This zone is controlled for automatic handling. 6. Leads at gauge plane ...
Vendor:SI
functions for complete SOC solution • Complete chip simulation of user-defined programmable-logic IP functions with the processor, caches, memory, and all hardwired functions on-chip • Synthesis of IP functions into the programmable fabric • Place-and-Route tool for efficient implementation of IP functions in the programmable fabric • Extensive timing analysis of IP functions wit...
Vendor:PHIPackage Cooled:SOP8SD/C:07+
For K = 1 the transfer function is H(z) = 1, that means no filtering is performed and the input data remains unchanged. For K < 1 noise reduction filtering is activated. The input data and the delayed data from the memory are combined according H(z).
Vendor:TID/C:07+
Package Cooled:SMDD/C:00+
Package Cooled:08+D/C:800
1. Small size and light weight For space saving, the outside dimensions of the main body are reduced to be 21.5 mm (length) 14.4 mm (width) 37 mm (height) (.846 .567 1.457 inch). and the weight is also reduced to be approx. 19 g .67 oz (Direct coupling 1 Form A, 1 Form B type) 2. Water tightness Since the relays comply with the water tightness standards, JIS D 0203, water and dust will not en...
Vendor:HITACHIPackage Cooled:SOP16D/C:2007+
18 keys can be connected by key input K1~K6 and 6 3 matrix by means of timing signal T1~T3 . Multiple keying is possible for the keys connected to T1 line up to sextet , and all key inputs are output . (Output becomes continuous pulses .) Between the timing signal lines , priority has been decided in order of T1, T2 , T3 . The keys connected to T2 and T3 lines have priority and input is made through mo...
Vendor:NSPackage Cooled:DIPD/C:1989
TypeDescription P3.3 volt input supply voltage. P5.0 volt reference for 5.0 volt signaling environments and 3.3 volt reference for 3.3 volt signaling environments. PGround Pin I/OThe PCI address and data lines are multiplexed on the same PCI pins. During the first clock cycle of a transaction, the 32 bits contain an address and during subsequent clock cycles, they contain data. Both read and write burs...
DESCRIPTION The 4538BD is a quad differential line receiver designed to meet the RS-422, RS-423 standards for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS. The 4538BD has an input sensitivity of 200mV over the common mode input voltage range of 7V. The 4538BD features internal pull-up and pull-down resistors which prevent output oscillat...
Vendor:N/APackage Cooled:SOP16MD/C:03+
The HY64UD16322M is a 32Mbit 1T/1C SRAM featured by high-speed operation and super low power consumption. The HY64UD16322M adopts one transistor memory cell and is organized as 2,097,152 words by 16bits. The HY64UD16322M operates in the extended range of temperature and supports a wide operating voltage range. The HY64UD16322M also supports the deep power down mode for a super low standby current. The HY64...
NOTES: 1. See Test Conditions under TEST CIRCUITS AND WAVEFORMS. 2. This parameter is guaranteed but not production tested. 3. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.2ns at CL = 50pF. Since this time constant is much smaller than the rise and fall times ...
Vendor:PHILIPSD/C:06+
Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de- coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc- tion to effectively execute within one cycle. If an instruc- tion changes the program counter, two cycles are required to complete the instruction.
Vendor:TOSHIBAPackage Cooled:SOP16
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following t...
Vendor:TOSHIBAPackage Cooled:SOP16
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following t...
Vendor:STPackage Cooled:99+D/C:15
Vendor:LITTELFSEPackage Cooled:1808-4AD/C:05+NOPB
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, OGND and AGND wired together unless otherwise noted. Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD wit...
SMDI will provide the detailed layout (AutoCad format) to users wishing to use the exact same layout and PCB material shown in the following circuits. The circuits recommended within this application note were designed using the following PCB stack up:
Experimental Results The operating characteristics of the pulsed LED oscillator circuit were compared to the DC circuit shown in Figure 10. The DC circuits current limiting resistor R5 was selected so the current through the LED was equal to the average (RMS) current of the oscillator circuits LED. A high efficiency green GaP/GaP LED from Chicago Miniature Lamp (part number CMD64531) was used to evalu...
Because the IXDP610 is a digital IC, and is programmable, it is possible to tailor the dead-time period (defined as tDT in Fig. 2). IXDP610s programmable dead-time feature is difficult to duplicate in the equivalent analog system. The control of a switching bridge usually involves a process of alternating the on-time of two power switches connected in series between a high-voltage and a low-voltage. For ...
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
Package Cooled:SOP8
NOTES: JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for PDIP package. CAUTION: (1) Do not apply voltages higher than VDD or less than GND potential on any terminal except VREFA, B (pins 4 and 18) and RFBA, B (pins 3 and 19). (2) The digital control inputs are zener-protected: however, permanent damage may occur on unprotected units from high-energy electrost...
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as co...
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as co...
Vendor:MAXIMPackage Cooled:TSSOP8D/C:07+
Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.9 ns at 3.3 V Low Power Consumption, 10-µA Max ICC 24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Unbuffered Outputs Latch-U...
Vendor:NEC
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBZ/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
Vendor:TIPackage Cooled:N/AD/C:07/08+
8-bit A/D Converter (ADC) with 8 channels Fully static operation 63 basic instructions 17 main addressing modes 8x8 unsigned multiply instruction True bit manipulation Versatile Development Tools (under Windows) including assembler, linker, C-compiler, archiver, source level debugger, software library, hardware emulator, programming boards and gang programmers
Vendor:TOSPackage Cooled:06+D/C:500
The BUF12800 programmable voltage reference allows fast and easy adjustment of 12 programmable reference outputs, each with 10-bit resolution. It allows very simple, time-efficient adjustment of the gamma reference voltages. The BUF12800 is programmed through a high-speed standard two-wire interface. The BUF12800 features a double-register structure for each DAC channel to simplify the implementation...
Vendor:MOTD/C:08+
Operating Temperature, -55C to 100C Storage Temperature, -55C to 100C * For all states of absorptive switch, and for reflective switch in "ON" condition; for reflective switch "OFF" port, 5:1 VSWR typ. ** Video leakage or break through is defined as leakage of TTL switching signal to RF output ports. 1. Absolute maximum power and voltage ratings: RF input power, 250 mW, Supply ...
Vendor:FREESCALEPackage Cooled:MLPD/C:05+
Vendor:ICSPackage Cooled:05+D/C:TSSOP-3.9-16P
Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended tempera...
Vendor:NECPackage Cooled:CAND/C:06+
During a Read or Write command cycle, Address input defines the colum address, In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a precharge command cycle, AP is used in conjunction with BA0, BA1 to ...
Vendor:NECPackage Cooled:铁帽子
Pin Description Address 0-2. These pins are used to select one of up to 8 devices of the same type on the same two-wire bus. To select the device, the address value on the three pins must match the corresponding bits contained in the device address. The address pins are pulled down internally. Ground Serial Data Address. This is a bi-directional line for the two-wire interface. It is open-drain and is ...
Vendor:MOT
500Msps Conversion Rate 7.0 Effective Bits Typical at 250MHz 1.2GHz Analog Input Bandwidth Less than 1/2LSB INL 50Ω Differential or Single-Ended Inputs 250mV Input Signal Range Ratiometric Reference Inputs Dual Latched Output Data Paths Low Error Rate, Less than 10-15 Metastable States 84-Pin Ceramic Flat Pack
Vendor:PHIPackage Cooled:SOP14D/C:96+
Agilent Technologiess ATF-521P8 is a single-voltage high linearity, low noise E-pHEMT housed in an 8-lead JEDEC- standard leadless plastic chip carrier (LPCC[3]) package. The device is ideal as a medium-power, high-linearity am- plifier. Its operating frequency range is from 50 MHz to 6 GHz.
Vendor:MOLEX
The state of the OUT pin is driven by a voltage comparator whose output state depends on the level of the input voltage on the sample capacitor and the level of an adjustable 8-bit threshold voltage. The threshold is adjusted by shifting data bits into the D/A Register (DAR) via the DATA pin while clocking the CLK pin. The timing of this data is shown in Figure 5. Data is
Stress in excess of Absolute Maximum Rat- ings may cause permanent damage. Absolute Maximum Ratings, sometimes referred to as no destruction limits, are normally tested with one parameter at a time exceeding the limits of Output data or Electrical Charac- teristics. If exposed to stress above these limits, function and performance may de- grade in an unspecified manner.
Package Cooled:0424+D/C:QFP
nominal at +25C and VIN = +5V. The value of the -2VIN output and is approximately 140Ω nominal at +25C and VIN = +5V. In this particular case, -VIN is approximately C 5V and C2VIN is approximately C10V at very light loads, and each stage will droop according to the equation below:
Vendor:MOTPackage Cooled:30D/C:N/A
Vendor:MolexD/C:08+
Vendor:STD/C:DIP8/SOP8
Vendor:RPackage Cooled:DIP
Package Cooled:SMDD/C:03
The KS8721BL/SL is a 10BASE-T, 100BASE-TX, and 100BASE-FX physical layer transceiver providing MII/ RMII interfaces to MACs and switches. Using a unique mixed-signal design that extends signaling distance while reducing power consumption, the KS8721BL/SL repre- sents Micrels fourth generation single-port Fast Ethernet PHY. Micrels architecture dissipates an ultra-low 275mW in power, including transm...
Vendor:ALPHA POPackage Cooled:08+D/C:15000