54FCT373ALB

Vendor:IDT

The AD5399 is the industry-first dual 12-bit digital-to-analog converter that accepts twos complement digital coding with 2 V dc offset for single-supply operation. Augmented with a built-in precision reference and a solid buffer amplifier, the AD5399 is the smallest self-contained 12-bit precision DAC that fits many general-purpose as well as DSP specific applications. The twos complement programming f...

54FCT373DB

Vendor:105D/C:N/A

Stability The IRU1015-33 requires the use of an output capacitor as part of the frequency compensation in order to make the regulator stable. Typical designs for microprocessor applications use standard electrolytic capacitors with a typi- cal ESR in the range of 50 to 100mΩ and an output capacitance of 500 to 1000µF. Fortunately as the capacitance increases, the ESR decreases resulting in a fixe...

54FCT373DMQB

Vendor:NSCD/C:2005

54FCT373DMQB/QS

The Rambus RIMM modules are offered in a 184-pad 1 mm edge connector pad pitch form factor suitable for 184 contact RIMM connectors. The RIMM module is suitable for desktop and other system applications. The next figure shows an eight device Rambus RIMM module without heat spreader.

54FCT373DMQB/QS

The Rambus RIMM modules are offered in a 184-pad 1 mm edge connector pad pitch form factor suitable for 184 contact RIMM connectors. The RIMM module is suitable for desktop and other system applications. The next figure shows an eight device Rambus RIMM module without heat spreader.

54FCT373LMQB

54FCT373LMQB

54FCT373LMQB/C 5962-87644012A

Vendor:NSPackage Cooled:LCC20

54FCT374AEB

Vendor:IDTPackage Cooled:SOP20D/C:90/92+

54FCT374DMQB

Vendor:NSCPackage Cooled:DIPD/C:0428+

The 64-bit ID identifies each bq2022. The 48-bit serial number is unique and programmed by Texas Instruments. The default 8-bit family code is 09h; however, a different value can be reserved on an individual customer basis. Contact your Texas Instruments sales representative for more information.

54FCT374DMQB/QS

Vendor:NSPackage Cooled:DIPD/C:9428+

tively near distance as shown in Fig. 1, a spot is produced at (a). When the tar- get is at a position B that is far, a spot is produced at (b). Accordingly, if any spot position on the position sensitive device is detected, the distance to the target can be determined. This is the principle of optical triangulation range measurement.

54FCT374DMQB/QS

Vendor:NSPackage Cooled:DIPD/C:9428+

tively near distance as shown in Fig. 1, a spot is produced at (a). When the tar- get is at a position B that is far, a spot is produced at (b). Accordingly, if any spot position on the position sensitive device is detected, the distance to the target can be determined. This is the principle of optical triangulation range measurement.

54FCT374FMQB

54FCT377ATDB

Vendor:dtPackage Cooled:30D/C:N/A

The micro-controller system of commands complies with the system of commands of the MCS-51 family. The microchip is initialized (reset) automatically when turning power on, when the guard timer is overflowed or effected by the RST signal (voltage active low level) if the external synchronization signal is applied or during the quartz connection.

54FCT377DB

Vendor:IDTPackage Cooled:DIPD/C:9225+

Input Specifications Voltage range Filter Isolation Specifications Rated voltage Resistance Output Specifications Voltage accuracy Ripple and noise (at 20 MHz BW) Short circuit protection Line voltage regulation Load voltage regulation Temperature coefficient General Specifications Efficiency Switching frequency Environmental Specifications Operating temperature (ambient) Storage temperature Dera...

54FCT399DB

Vendor:35D/C:N/A

The Fairchild Switch FST3125 provides four high-speed CMOS TTL-compatible bus switches. The low on resis- tance of the switch allows inputs to be connected to out- puts without adding propagation delay or generating additional ground bounce noise.

54FCT399DB

Vendor:35D/C:N/A

The Fairchild Switch FST3125 provides four high-speed CMOS TTL-compatible bus switches. The low on resis- tance of the switch allows inputs to be connected to out- puts without adding propagation delay or generating additional ground bounce noise.

54FCT521DB

Vendor:105D/C:N/A

3.1.1 SPI bus While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission should be starting from pulling SSB to "low" level, enabling MTV038 to receiving mode, and retain "low" level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

54FCT521DMQB

Vendor:NSCD/C:2005

54FCT533DB

Vendor:35D/C:N/A

Analog Outputs Full Scale Output Current COMP_VID/Y/C Full Scale Output Current COMP_VID/Y/C LSB Current COMP_VID/Y/C LSB Current COMP_VID/Y/C DAC-to DAC Matching Output Compliance Output Impedance Output Capacitance DAC Output Delay DAC Rise/Fall Time

54FCT540ADB-5962

Vendor:IDTPackage Cooled:DIP20陶瓷D/C:90+

54FCT541LMQB

Vendor:NSCPackage Cooled:LCCD/C:99+

54FCT543ADB 5962-8973002LA

Vendor:IDTPackage Cooled:CDIP24D/C:9205

54FCT543DB

Vendor:105D/C:N/A

54FCT573ADB

Vendor:IDTPackage Cooled:DIP

54FCT573DB

Vendor:IDTPackage Cooled:CDIP20

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

54FCT573DMQB/QS

Vendor:NSPackage Cooled:30D/C:N/A

54FCT573LMQB

Vendor:TI

54FCT573LMQB

Vendor:TI

54FCT573LMQB/QS

The MK3725 is a low cost, high-performance, two output 3.3 Volt VCXO and PLL clock synthesizer designed to replace expensive VCXOs and crystals. The patented on-chip Voltage Controlled Crystal Oscillator accepts a 0 to 3.3 V input voltage to cause the output clocks to vary by 115 ppm minimum. Using our analog Phase Locked Loop (PLL) techniques, the device uses an external, fundamental mode pullable ...

54FCT574ADTB

Vendor:dtPackage Cooled:30D/C:N/A

54FCT574ATDB

Vendor:IDTPackage Cooled:CDIP20D/C:——

54FCT574DMQB

Vendor:NSD/C:5962-8951301RA

Other features of the 54FCT574DMQB include two independent end-of-charge indications, including a digital indication that is programmable with a resistor-to-ground and an analog cur- rent output that is proportional to the output current, allowing for monitoring of the actual charging current. Additional features include very low dropout (500mV over the tempera- ture range), thermal shutdown, and rever...

54FCT640DB

Vendor:105D/C:N/A

If the CPE is a telephone, one way to achieve good CAS speech immunity is to put CAS detection on the telephone hybrid or speech IC receive pair instead of on Tip and Ring. Talkdown immunity improves because the near end speech has been attenuated while the CAS level is the same as on Tip/Ring, resulting in improved signal to speech ratio. Talkoff immunity is also improved because the near end speech has be...

54FCT645ADB

Vendor:IDTPackage Cooled:DIPD/C:98

54FCT646BBA

Vendor:TIPackage Cooled:DIP24D/C:N/A

54FCT646BBA

Vendor:TIPackage Cooled:DIP24D/C:N/A

54FCT652ATDB5962-9224602MLA

Vendor:IDTPackage Cooled:DIP陶瓷条子24脚D/C:94

54FCT821ATDB

Package Cooled:DIPD/C:9545

The hardware RESET# terminates any operation in progress and resets the internal state machine to reading array data. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device.

54FCT823ADB

Vendor:105D/C:N/A

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843031AGwww.icst.com/products/hiperclocks.htmlREV. A NOVEMBER 29, 2004

54FCT823ATDB

Vendor:IDT

Notes: 1. Failure criterion ; IR > 100 nA at VR = 30 V 2. Please do not use the soldering iron due to avoid high stress to the EFP package. 3. The material of lead is exposed for cutting plane. Therefor, soldering nature of lead tip part is considered as unquestioned. Please kindly consider soldering nature.

54FCT823BLB5962

5 V Tolerant Inputs TTL Compatible Outputs High Bandwidth Burst Bus 32-Bit Multiplexed Address/Data Programmable Memory Configuration Selectable 8-, 16-, 32-Bit Bus Widths Supports Unaligned Accesses Big or Little Endian Byte Ordering High-Speed Interrupt Controller 31 Programmable Priorities Eight Maskable Pins plus NMI Up to 240 Vectors in Expanded Mode Two On-Chip Timers Independent 32-Bit...

54FCT825ATDMB

Vendor:NSD/C:DIP

54FCT827ADB

D/C:CDIP

54FCT827ADB

D/C:CDIP

54FCT833ADB

Vendor:105D/C:N/A

The 312 series of decoders are capable of decod- ing 12 bits of information that consists of N bits of address and 12-N bits of data. To meet vari- ous applications they are arranged to provide a number of data pins ranging from 0 to 4 and an address pin ranging from 8 to 12. Thus, various combinations of address/data number are available in different packages.

54FCT841ADB

Vendor:105D/C:N/A

The QS5919T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure < 350ps skew between the Q0-Q4, and Q/2 outputs. The QS5919T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various...

54FCT853ADB

Vendor:IDTD/C:DIP

54FCT861ADB

Vendor:IDTPackage Cooled:86D/C:DIP-24

The Harris CD74HC32, CD74HCT32 contain four 2-input OR gates in one package. Logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally pin compatible with the standard 74LS logic family.

54H00/BCBJC

Vendor:TIPackage Cooled:DIP陶瓷

54H00DM

Vendor:FPackage Cooled:30D/C:N/A

The BTW 69 (N) Family of Silicon Controlled Recti- fiers uses a high performance glass passivated technology. This general purpose Family of Silicon Controlled Rectifiers is designed for power supplies up to 400Hz on resistive or inductive load.

54H04

54H04BCA

54H04DMQB

Vendor:FPackage Cooled:DIPD/C:81#

54H04DMQB

Vendor:FPackage Cooled:DIPD/C:81#

54H08BCBJC

54H10

54H101/BCAJC

54H102/BCAJC

Vendor:TIPackage Cooled:DIP陶瓷

54H102/BCBJC

Vendor:TIPackage Cooled:DIP陶瓷

54H103

Vendor:105D/C:N/A

54H103BABJC

54H106DM

Vendor:NS

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. VDRM and VRRM for all types can be applied on a continuous basis. Rati...

54H10DM

Vendor:NS

perform serial to parallel conversion, SONET/SDH overhead processing and ATM cell processing and then pass ATM cells to an ATM packet reassembly engine. On the Transmit side, a segmentation engine will divide long packets of data such as Ethernet packets into 53 byte cells and pass them to the SUNI. The SUNI device will then perform ATM cell processing, such as header generation, SONET/SDH overhead pro...

54H11

The clock input is differential and TTL/CMOS-compatible. The 10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V) supplies. Two output buses support demultiplexed data up to 105 MSPS rates, and binary or twos complement output coding format is available. A data sync function is provided for timing- dependent applications. An output clock simplifies interfacing to external logic. The output...

54H11DM

Vendor:FPackage Cooled:30D/C:N/A

The DTMF generator will output one of 16 standard tone pairs determined by a 4-bit binary value and TX DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode is selected using the tone register and the transmit enable (CR0 bit D1) is changed from 0 to 1.

54H11J

54H14DMQB

Vendor:N/APackage Cooled:410D/C:N/A

On-chip peripheral functions include a 16-bit free-running timer (FRT), 8-bit timer (TMR), watchdog timer (WDT), two PWM timers (PWM and PWMX), a serial communication interface (SCI, IrDA), I 2C bus interface (IIC), PS/2-compatible keyboard buffer controller, host interface (HIF:XBS and LPC), D/A converter (DAC), A/D converter (ADC), and I/O ports.

54H183DMQB

Vendor:FPackage Cooled:30D/C:N/A

The 82091AA Advanced Integrated Peripheral (AIP) is an integrated I O solution containing a floppy disk controller 2 serial ports a multi-function parallel port an IDE interface and a game port on a single chip The integration of these I O devices results in a minimization of form factor cost and power consumption The

54H21DM

54H40BCB

54H40BCBJC

Vendor:105D/C:N/A

54H51DM

Vendor:FPackage Cooled:DIP14陶瓷D/C:80+

The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals.

54H55

54H61J

Vendor:TIPackage Cooled:CDIP14D/C:81

54H64DM

Vendor:105D/C:N/A

54H64DM

Vendor:105D/C:N/A

54H7071

Package Cooled:SOP-8D/C:98+

Software design support and automatic place-and-route provided by Alteras development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Caden...

54H72

Vendor:N/APackage Cooled:30D/C:N/A

Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disabled Low) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent ...

54H72

Vendor:N/APackage Cooled:30D/C:N/A

Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disabled Low) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent ...

54H73

Vendor:NSPackage Cooled:30D/C:N/A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved1

54H73

Vendor:NSPackage Cooled:30D/C:N/A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved1

54H73DM

Vendor:TIPackage Cooled:DIP14陶瓷D/C:82+

The LM89 is an 11-bit digital temperature sensor with a 2-wire System Management Bus (SMBus) serial interface. The LM89 accurately measures its own temperature as well as the temperature of an external device, such as processor thermal diode or diode-connected transistor such as the 2N3904. The temperature of any ASIC can be accurately determined using the LM89 as long as a dedicated diode (semiconduc...

54HC00

Package Cooled:DIP-14

54HC00

Package Cooled:DIP-14

54HC00F3A

Vendor:TID/C:O9+

The HS I2C™-compatible module is a reference solution for implementing an interface that is compatible with the high-speed (HS) mode (3.4MHz, 1.7MHz), fast mode (400kHz), and standard mode (100kHz) of the I2C stan- dard. The module consists primarily of an Altera EPM3256AQC208-10 programmable logic device (PLD) containing the DI2CM core available from Digital Core Design. The module allows microcontrol...

54HC00M/B2AJC

Vendor:MOT

C Squelch on receive and collision pairs • TPI module (10BASE-T) transceiver C Transmitter and receiver functions C Collision detect, heartbeat and jabber C Selectable link integrity test or link disable C Polarity detection/correction • Provides more powerful functions than NS DP83905 C Supports 15 I/O bases instead of 7 C Direct ID PROM access through I/O port instead of through r...

54HC02

Vendor:-D/C:O9+

also be used independent of the HALT or IDLE modes Each I O pin has software selectable configurations The device operates over a voltage range of 2 5V to 6V High throughput is achieved with an efficient regular instruction set operating at a maximum rate of 1 ms per instruction

54HC02/BCAJC

Vendor:TIPackage Cooled:DIP陶瓷

DNL: 1 LSB Max SINAD = 81.5 dB, SFDR = 95 dB THD = 94 dB at 15 kHz fin, 200 KSPS SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz Single 5-V Supply Rail-to-Rail Analog Input With 500 kHz BW Two Input Options Available: − TLC3541 − Single Channel Input − TLC3545 − Single Channel, Pseudo-Differential Input (TLC3541) Optimized DSP Interface − Requires FS Inp...

54HC02BCAJC

Vendor:MOTOROLAPackage Cooled:CDIP-14

Turn-On Time Turning Q1 in Figure 1 off, removes the low-voltage signal at pin 8. After a 10-15ms delay the regulator output rises and reaches full output voltage within 30ms. Fig. 2 shows the typical waveforms of a PT6701 following the prompt turn-off of Q1 at time t =0 secs. The output volt- age was set to 2.5V, and the waveforms were measured with a 5V input source, and 10A resistive load.

54HC02BCAJC

Vendor:MOTOROLAPackage Cooled:CDIP-14

Turn-On Time Turning Q1 in Figure 1 off, removes the low-voltage signal at pin 8. After a 10-15ms delay the regulator output rises and reaches full output voltage within 30ms. Fig. 2 shows the typical waveforms of a PT6701 following the prompt turn-off of Q1 at time t =0 secs. The output volt- age was set to 2.5V, and the waveforms were measured with a 5V input source, and 10A resistive load.

54HC02F3A

Vendor:TID/C:O9+

The MAX2654 operates in the GPS frequency of 1575MHz with 15.1dB of gain, 1.5dB noise figure, and only consumes 5.8mA. The MAX2655 is designed with high-input IP3 to improve operation in cellular applica- tions where the cellular power amplifier leaks into the GPS receiver. The MAX2656 is designed for PCS phone applications with 13.5dB of gain in high-gain mode and 0.8dB of gain in low-gain mode (selected by...

54HC02M/B2AJC

Vendor:MOTOROLAPackage Cooled:LLCCD/C:2005+

54HC03

Vendor:——Package Cooled:CLCC20D/C:89+

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

54HC03/BCAJC

Vendor:105D/C:N/A

The TC55NEM216AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V 10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in lo...

54HC03J

Arbitrary trigger levels for receiver and transmitter FIFO interrupts and automatic in-band and out-of- band flow control Infra-red (IrDA) receiver and transmitter operation 9-bit data framing as well as 5,6,7 and 8 12 multi-purpose IO pins which can be configured as interrupt input pins Can be reconfigured using optional non-volatile configuration memory (EEPROM) Global Interrupt Status and readable...

54HC04

Vendor:600

I2C interface select / I2C RESET (active low, asynchronous). If ISEL is high, then the I2C interface is active. Default values for the I2C registers can be found in the I2C register descriptions section. If ISEL is low, then I2C is disabled and the chip configuration is specified by the configuration pins (BSEL, DSEL, EDGE, VREF) and state pin (PD). If ISEL is brought low and then back high, the I2C sta...

54HC04

Vendor:600

I2C interface select / I2C RESET (active low, asynchronous). If ISEL is high, then the I2C interface is active. Default values for the I2C registers can be found in the I2C register descriptions section. If ISEL is low, then I2C is disabled and the chip configuration is specified by the configuration pins (BSEL, DSEL, EDGE, VREF) and state pin (PD). If ISEL is brought low and then back high, the I2C sta...

54HC04BCA

54HC04F

Vendor:HARRISPackage Cooled:DIP-14D/C:9810

The interrupt controller lets the DSP respond to 13 interrupts with minimum overhead. The controller implements an interrupt priority scheme as shown in Table 2. Applications can use the unassigned slots for software and peripheral interrupts. The DSPs Interrupt Control (ICNTL) register (shown in Table 3) provides controls for global interrupt enable, stack interrupt con- figuration, and interrupt nesting.