Index "6"Package Cooled:SOP32WD/C:2007+
D/C:06+
Vendor:SPRAGUE
Vendor:KEMET
After the Master sends a START condition and the slave address byte, the CAT24FC02 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24FC02 then performs a Read or a Write operation depending on the state of the R/W bit.
Vendor:AVX
Vendor:168
Vendor:168
The Memory management unit controls the virtual memory system page mapping. It consists of an instruction address translation buffer (the ITLB), a data address translation buffer (the DTLB), a Joint TLB (the JTLB), and co-processor registers used for the virtual memory mapping sub-system.
The Memory management unit controls the virtual memory system page mapping. It consists of an instruction address translation buffer (the ITLB), a data address translation buffer (the DTLB), a Joint TLB (the JTLB), and co-processor registers used for the virtual memory mapping sub-system.
Vendor:TOSHIBAPackage Cooled:23-6.8VD/C:08+
The DS1554 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1554P af...
Vendor:KDSPackage Cooled:20.6×12.6D/C:DIP 4P
Vendor:KDSPackage Cooled:3.2×5D/C:SMD 2P
D/C:袋装
Vendor:SIEMENSPackage Cooled:SOP-16D/C:06+
Vendor:SIEMENSPackage Cooled:SOP-16D/C:06+
Package Cooled:DIP-18D/C:02+
When the result is rounded to fewer than 16 bits, the unneeded lowest positions of the output bus are tristated and become supplementary control bits, which enable the x/sin(x) filter, bypass/delay, double-latency, dual-channel,
Vendor:ZILOGPackage Cooled:SMD18D/C:00+
Momentary action pushbuttons are used as control inputs in this case. This allows the user to experiment with the operation of the motor. An ELM410 is used to debounce the switches, so that the mechanical bouncing of the switches does not cause multiple steps of the motor armature.
Vendor:ZILOGPackage Cooled:SMD18D/C:00+
An internal power-on reset (POR) and an enable input (EN) control the operation of the SN65LVDS151. When VCC is below 1.5 V, or when EN is low, the device is in a low-power disabled state, and the DO and LCO differential outputs are in a high-impedance state. When VCC is above 3 V and EN is high, the device and the two differential outputs are enabled and operating to specifications. The link clock output...
Vendor:ZILOGPackage Cooled:SMD18D/C:00+
An internal power-on reset (POR) and an enable input (EN) control the operation of the SN65LVDS151. When VCC is below 1.5 V, or when EN is low, the device is in a low-power disabled state, and the DO and LCO differential outputs are in a high-impedance state. When VCC is above 3 V and EN is high, the device and the two differential outputs are enabled and operating to specifications. The link clock output...
Vendor:AMISPackage Cooled:30D/C:N/A
Note: 1. Commercial Product : TA=0 to 70C, unless otherwise specified Extended Product : TA=-25 to 85C, unless otherwise specified Industrial Product : TA=-40 to 85C, unless otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width30ns 3. Undershoot : -3.0V in case of pulse width30ns 4. Overshoot and undershoot are sampled, not 100% tested
Vendor:ZILOGPackage Cooled:SMD18D/C:00+
2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL ULTRA FAST LOAD TRANSIENT RESPONSE INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT TTL-COMPATIBLE 5 BIT PROGRAMMABLE OUTPUT FROM 0.800V TO 1.550V WITH 25mV STEPS DYNAMIC VID MANAGEMENT 0.6% OUTPUT VOLTAGE ACCURACY 10% ACTIVE CURRENT SHARING ACCURACY DIGITAL 2048 STEP SOFT-START OVERVOLTAGE PROTECTION OVERCURRENT PROTECTION RE...
Vendor:ZILOGPackage Cooled:SMD18D/C:00+
DESCRIPTION M62352A is a CMOS structured semiconductor integrated ciruict integrating 12 channels of built-in D-A converters with high performance buffer operational amplifierf or each channel output. 3-wire serial interface (DI,CLK,LD) method is used for the taransfer format of digital data to allow connection with microcomputer with minimum wiring Do terminal is provided to allow cascading serial use. Bui...
Vendor:ZILOGD/C:07+
The Timing and Watchdog Module (TWM) contains a Real- Time timer and a Watchdog unit. The Real-Time Clock Tim- ing function can be used to generate periodic real-time based system interrupts. The timer output is one of 16 in- puts to the Multi-Input-Wake-Up module which can be used to exit from a power-saving mode. The Watchdog unit is de- signed to detect the application program getting stuck in an i...
Vendor:ZILOGPackage Cooled:SMD18D/C:00+
Notes: 1. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC. 2. C75/+75 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less board capacitance.
Vendor:ZILOGPackage Cooled:SMD18D/C:00+
Input Channel A No Internal Connection Internal Reference Supply Bias Voltage Common-Mode Voltage Internal Reference Ground No Internal Connection Input Channel B No Internal Connection Do Not Connect Coupling Capacitor Channel B Coupling Capacitor Channel B +5V Supply Channel B Ground Channel B Positive Output Channel B Negative Output Channel B
Vendor:ZILOGPackage Cooled:PLCC44D/C:00+
Address, active High. In Word mode, these 18 inputs select one of 262,144 (256K) words within the array for read or write operations. In Byte mode, these inputs are combined with the DQ15/A-1 input (LSB) to select one of 524,288 (512K) bytes within the array for read or write operations.
Vendor:ZILOGPackage Cooled:PLCC44D/C:00+
The VP5313/VP5513 converts digital Y Cr Cb data into analog PAL or NTSC composite video, and also provides simultaneous RGB outputs. These additional converters can optionally provide separate luma and chroma outputs plus a further composite video channel. All outputs are capable of driving doubly terminated 75Ω loads with standard video levels. All D/A converters are to 9 bit accuracy, and are...
Junction Temperature Calculation: TJ = TA + (PD x JA). JA assume device is mounted on a 0.5 inch2 copper pad. The JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow.
Vendor:STARCONNPackage Cooled:04+D/C:3595
The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a pro- grammable register/latch and the necessary clocks and control logic to allow combinatorial or registered opera- tion. The macrocells each have two outputs, combinatorial and registered. This dual output capability from the macrocell allows effi...
Vendor:STARCONNPackage Cooled:04+D/C:3595
The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a pro- grammable register/latch and the necessary clocks and control logic to allow combinatorial or registered opera- tion. The macrocells each have two outputs, combinatorial and registered. This dual output capability from the macrocell allows effi...
Vendor:东芝D/C:袋装
Vendor:AMIPackage Cooled:QFPD/C:95+
Vendor:TEMICPackage Cooled:30D/C:N/A
These switches are fully specified with +5V, and +3.3V supplies. With +5V, they guarantee <10Ω On-Resistance. On-Resistance matching between channels is within 2Ω. On-Resistance flatness is less than 55Ω over the specified range. These switches also guarantee fast switching speeds (tON <20ns).
Vendor:N/APackage Cooled:30D/C:N/A
* Specifications will vary with foreign standards certification ratings. *1 Measurement at same location as "Initial breakdown voltage" section. *2 By resistive method, nominal voltage applied to the coil; contact carrying current: 2 A. *3 Nominal voltage applied to the coil, excluding contact bounce time. *4 Nominal voltage applied to the coil, excluding contact bounce time without...
Vendor:AMSPackage Cooled:30D/C:N/A
The MCP1701 is capable of delivering 250 mA with an input-to-output voltage differential (dropout voltage) of 650 mV. The low dropout voltage extends the battery operating lifetime. It also permits high currents in small packages when operated with minimum VIN C VOUT differentials.
Vendor:3500
1A, 1B, 1C = SPST N.O., SPST N.C., SPDT 2A, 2B, 2C = DPST N.O., DPST N.C., DPDT 3A, 3B, 3C = 3PST N.O., 3PST N.C., 3PDT 4A, 4B, 4C = 4PST N.O., 4PST N.C., 4PDT 1 Pole: 20A @ 277VAC & 28VDC 2 Pole: 12A @ 250VAC & 28VDC; 10A @ 277VAC; ½ hp @ 125VAC 3 Pole: 12A @ 250VAC & 28VDC; 10A @ 277VAC; ½ hp @ 125VAC 4 Pole: 12A @ 250VAC & 28VDC; 10A @ 277VAC; ½ hp @ 125VAC < 50 mi...
System timing is simplified in that the on-chip edge triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers available in the market.
Vendor:STARCONNPackage Cooled:04+D/C:890
All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA = 25C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V. 3Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge. 4Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, mul...
Vendor:OND/C:3
Can Be Used in Three Combinations: C OR-AND Gate C OR Gate C AND Gate Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 C 2000-V Human-Body Model (A114-A) C 200-V Machine Model (A115-A) C 1000-V Charged-Device Model (C101)
Vendor:SIEMENSPackage Cooled:SMD16D/C:06+
Xilinx thoroughly benchmarked the Virtex family. While per- formance is design-dependent, many designs operated internally at speeds in excess of 100 MHz and can achieve 200 MHz. Table 2 shows performance data for representa- tive circuits, using worst-case timing parameters.
Vendor:SIEMENSPackage Cooled:SMD16D/C:06+
Xilinx thoroughly benchmarked the Virtex family. While per- formance is design-dependent, many designs operated internally at speeds in excess of 100 MHz and can achieve 200 MHz. Table 2 shows performance data for representa- tive circuits, using worst-case timing parameters.
across RS that equals RS • ILOAD /1200. This sense voltage (VSENSE) is compared to a ref- erence voltage (VREF ) and an error voltage is developed that is gated in by the sequential control logic to drive the gate of the appropri- ate output sink transistor. A transconductance control function is thus re- alized where IOUT = V REF • 1200/R S. External components C1, C2, R1, R2, and R3 a...
across RS that equals RS • ILOAD /1200. This sense voltage (VSENSE) is compared to a ref- erence voltage (VREF ) and an error voltage is developed that is gated in by the sequential control logic to drive the gate of the appropri- ate output sink transistor. A transconductance control function is thus re- alized where IOUT = V REF • 1200/R S. External components C1, C2, R1, R2, and R3 a...
Medium-power voltage regulator diodes in hermetically sealed leaded glass SOD66 (DO-41) packages. The diodes are available in the normalized E24 approx. 5% tolerance range. The series consists of 33 types with nominal working voltages from 3.6 to 75 V (BZV85-C3V6 to BZV85-C75).
Vendor:东芝D/C:袋装
Note 1: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently...
Vendor:.Package Cooled:2005D/C:500
Vendor:AMEPackage Cooled:SOP7.2mmD/C:1998
1. Device mounted on 1" x 1", FR-4 PCB; 2 oz. Cu pad layout as shown on Diodes Inc. suggested pad layout document AP02001.pdf. 2. RoHS revision 13.2.2003. Glass and High Temperature Solder Exemptions Applied, see EU Directive Annex Notes 5 and 7. 3. Theoretical RqJS calculated from the top center of the die straight down to the PCB/cathode tab solder junction.
Vendor:AMEPackage Cooled:SOP7.2mmD/C:1998
1. Device mounted on 1" x 1", FR-4 PCB; 2 oz. Cu pad layout as shown on Diodes Inc. suggested pad layout document AP02001.pdf. 2. RoHS revision 13.2.2003. Glass and High Temperature Solder Exemptions Applied, see EU Directive Annex Notes 5 and 7. 3. Theoretical RqJS calculated from the top center of the die straight down to the PCB/cathode tab solder junction.
Vendor:SIEMENSPackage Cooled:SMD16D/C:06+
As an example lets find the total power consumption for an MM74C00 operating at f = 100 kHz, VCC = 10V and CL = 50 pF. From the curve, normalized power per gate equals 10 µW/pF. From the data sheet CPD = 12 pF; therefore, actual power per gate is:
Package Cooled:CDIP28D/C:2007+
Package Cooled:PLCC
Package Cooled:PLCC
The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporates multiplexed clock inputs to allow for distribution of a lower-speed, single-ended clock or a high-speed system clock. When LOWthe SEL pin will select the differential clock input.
The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporates multiplexed clock inputs to allow for distribution of a lower-speed, single-ended clock or a high-speed system clock. When LOWthe SEL pin will select the differential clock input.
Vendor:HPackage Cooled:SOP8SD/C:2007+
where ITH is the value of current set by the external RSET resistor. If fault signals are present at the input of A1 (which is held at virtual ground, +10V), one of the two current mirrors in the feedback path of A1 (Q4 and Q5) will become active, depending on which half-cycle the fault occurs. This action will raise the voltage at VS, switching I1 to a value equal to ITH, and reducing the discharge rat...
Vendor:ICPackage Cooled:SOPD/C:0544+
Vendor:ICPackage Cooled:SOPD/C:0544+
Vendor:N/APackage Cooled:SOP-8D/C:N/A
Negative Input Terminal Positive Input Terminal Positive Remote sense Negative Remote sense Positive Output Terminal Negative Output Terminal Inverter Good Signal Output adjustment trim pin On/Off Control Terminal Current Monitor Signal
Vendor:INFINEONPackage Cooled:SMD16D/C:03
The heart of the ADM is the ATA controller which translates standard ATA signals into Flash Media data and controls. SSTs ADM contains a proprietary ATA controller specifi- cally designed to attain high data throughput from host to Flash. The following components contribute to the ATA con- trollers performance.
Vendor:NSPackage Cooled:TSSOPD/C:06+
The sensor consists of 64 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to t...
Vendor:NSPackage Cooled:TSSOPD/C:06+
The sensor consists of 64 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to t...
Vendor:WPackage Cooled:0805-8.2P 250V
In addition to the column address, A10 (= AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (= AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high...
In addition to the column address, A10 (= AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (= AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high...
The TMP86FM29 is the high-speed, high-performance and low power consumption 8-bit microcomputer, including FLASH, RAM, LCD driver, multi-function timer/counter, serial interface (UART/SIO), a 10-bit AD converter and two clock generators on chip.
Vendor:HINODED/C:35A/600V/快熔
D/C:N/A
F2MC-8L family CPU core Dual-clock control system Maximum memory size: 8-Kbyte ROM, 256-byte RAM (max.) Minimum execution time: 0.95 µs/4.2 MHz I/O ports: max. 47 channels (max. 13 high-current type) 21-bit time-base counter 8/16-bit timer/counter: 8bit x 2 channels or 16-bit x 1 channels External interrupts (wake-up function): Four channels with edge selection plus eight level-interrupt chann...
D/C:N/A
5-mm-LED-Gehäuse (T 13/4), schwarz eingefärbt, Anschluß im 2.54-mm-Raster (1/10), Anodenkennzeichnung: krzerer Anschluß 5 mm LED package (T 13/4), black-colored epoxy resin lens, solder tabs lead spacing 2.54 mm (1/10), anode marking: short lead
Vendor:LTPackage Cooled:SMD
Internal circuitry includes a trimmed band-gap reference, oscillator, zener diode, charge pump, comparator, and control logic. The TPS2400 is designed for use with an external N-channel MOSFET which are readily available in a wide variety of voltages.
Vendor:3Package Cooled:FUJITSUD/C:N/A
♦ Four ADC Channels with Serial LVDS/SLVS Outputs ♦ Excellent Dynamic Performance 69.6dB SNR at fIN = 19.3MHz 92dBc SFDR at fIN = 19.3MHz -87dB Channel Isolation ♦ Ultra-Low Power 135mW per Channel (Normal Operation) 1.2mW Total (Shutdown Mode) ♦ Accepts 20% to 80% Clock Duty Cycle
Vendor:AMERICAN TECHNICAL CERAMICSD/C:N/A
Vendor:AMERICAN TECHNICAL CERAMICSD/C:N/A
Vendor:JATPackage Cooled:603D/C:05+
The ÉlanSC300 microcontrollers true static design and low operating voltage enable battery-powered op- eration and lower weight for embedded PC applica- tions. The internal core of the ÉlanSC300 microcontroller operates at 3.3 V and the I/O pads allow either 3.3 V or 5 V operation. Lowering typical op- erating voltage from 5 V to 3.3 V can dramatically re- duce power consumption.
Vendor:ATCD/C:8000
The EBD10RD4ADFA is 128M words 72 bits, 1 rank Double Data Rate (DDR) SDRAM registered module, mounting 18 pieces of 512M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and re...
D/C:7800
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditionsis not implied. Exposure to absoluteCmaximum-rated conditions for extended periods may affect device reliability.