63ZL820MGC18X25

63ZL820MKC16X31.5

63ZL820MKC18X25

64 MACROCELL CPLD (PLCC)

Vendor:367Package Cooled:EPM3064ALC44-10ND/C:IC PAL

64.000M

Vendor:KDSPackage Cooled:5×7D/C:SMD 4P

6400-0003-901

Vendor:EPSONPackage Cooled:30D/C:N/A

Continuous Drain Current, V GS @ 5.0V Continuous Drain Current, V GS @ 5.0V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw.

6400-0005-901

The potentiometer is implemented by a resistor array composed of 127 resistive elements and a wiper switching network. The wiper terminal can be connected to either end of the resistor array or at any one of the Tap Positions in between, providing 128 steps of resolution between RL and RH. The position of the wiper is determined by the value assigned to the volatile Wiper Register (WR). This register has an...

6400-0006-901

Package Cooled:N/AD/C:08+

The SSM2275 and SSM2475 are ideal for application in high performance audio amplifiers, recording equipment, synthesiz- ers, MIDI instruments and computer sound cards. Where cas- caded stages demand low noise and predictable performance, SSM2275 and SSM2475 are a cost effective solution. Both are stable even when driving capacitive loads.

6400-0011-901

Vendor:N/APackage Cooled:N/AD/C:08+09+

Control Signal Output. This signal indicates the ODD/EVEN field of the video signal. Refer to Fig. 2 for timing information of F relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA respectively. When locked and the input signal is of a progressive scan nature, F stays low at all times.

6400-0012-902

Package Cooled:N/AD/C:08+

6400-010-901

Loss of Lock Indicator (LOL) Output Pin Under normal device operation, when the PLL is locked, the LOL Phase Detector drives LOL to logic 0. Under circumstances when the VCSO cannot fully phase lock to the input (as measured by a greater than 4 ns discrepancy between the feedback and reference clock rising edges at the LOL Phase Detector) the LOL output goes to logic 1. The LOL pin will return back to...

640-030

Vendor:SANKENPackage Cooled:03+D/C:ZIP

64008J3120

Vendor:INTELPackage Cooled:BGA0814D/C:03+

64008J3120

Vendor:INTELPackage Cooled:BGA0814D/C:03+

640098-3

640098-8

640104411

640136-5

6401F

Package Cooled:QFND/C:07+

6401H

Package Cooled:QFND/C:07+

6401P

Notes: 5. LL disables outputs if TEST = MID and sOE# = HIGH. 6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE = HIGH or MID, sOE# disables them LOW when PE = LOW. 7. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given reference frequency (FREF) and div...

640204-1

(The following conditions apply to all the following parameters, unless otherwise specified.) AC: CL=50pf, RL=500 OHMS, TRISE=3.0ns, TFALL=3.0ns, Temp Range: -55C to 125C. NOTE: -55C TEMPERATURE, SUBGROUP 11 IS GUARANTEED BUT NOT TESTED.

640250-4

Vendor:AMPD/C:07+

Screen tested 100% on each device at -55C, +25C & +125C temperature, subgroups A1, 2, 3, 7 & 8. Screen tested 100% on each device at +25C temperature only, subgroup A9. Sample tested (Method 5005, Table 1) on each MFG. lot at +25C, +125C & -55C temperature, subgroups A1, 2, 3, 7 & 8. Sample tested (Method 5005, Table 1) on each MFG. lot at +25C, subgroup A9. Subgroups 10 & 11 are guar...

640250-4

Vendor:AMPD/C:07+

Screen tested 100% on each device at -55C, +25C & +125C temperature, subgroups A1, 2, 3, 7 & 8. Screen tested 100% on each device at +25C temperature only, subgroup A9. Sample tested (Method 5005, Table 1) on each MFG. lot at +25C, +125C & -55C temperature, subgroups A1, 2, 3, 7 & 8. Sample tested (Method 5005, Table 1) on each MFG. lot at +25C, subgroup A9. Subgroups 10 & 11 are guar...

640251-7

Vendor:AMPD/C:07+

Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical.

6402A

Write (WRITE) The WRITE instruction is followed by 16 bits of data to be written into the specified address After the last bit of data is put on the data-in (DI) pin CS must be brought low before the next rising edge of the SK clock This falling edge of the CS initiates the self-timed programming cycle The PE pin MUST be held high while loading the WRITE instruction however after loading the WRITE instr...

640310-3

Manages Total Power Between a USB Peripheral and Battery Charger Minimal Voltage Drop (100mV at 500mA) Ultralow Battery Drain: 1µA Reverse Current Blocking Diode Not Required Undervoltage Lockout Very Few External Components Compatible with Several LTC Linear Battery Chargers Overtemperature Protected Dual Battery Charge Priority Management Low Profile (1mm) SOT-23 Package

640310-6

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, TA = 25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Measured by the voltage drop between I and Y pin at indicated current through the swi...

640383-9

Vendor:AMPD/C:07+

This will result in an input to the crystal of 50% of the rail to rail output of X2. Usually this keeps the drive level into the crystal within the drive specifications of the crystal but the designer should verify this. Overdriving the crystal can cause damage.

640386-4

6403-T00-S-00

640401-1-P

64040V20S

• Generation 4 IGBT technology • Standard: Optimized for minimum saturation voltage and operating frequencies up to 10kHz • Very low conduction and switching losses • HEXFRED™ antiparallel diodes with ultra- soft recovery • Industry standard package • UL approved

640434-5

640443-7

PULSED OPERATION Some applications must handle pulses of current or varying current waveforms with a low duty-cycle. The SOA plot sometimes shows an ability to supply larger currents for short duration pulses. In Figure 2, the SOA limits are labeled for 5ms, 1ms and 0.5ms pulses. The duty-cycle must be low (approximately 5% or less), so that heating in the output transistor is given time to dissipate.

640445-2

Vendor:AMPD/C:07+

DESCRIPTION The 74LCX05 is a low voltage CMOS OPEN DRAIN HEX INVERTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications. It can be interfaced to 5V signal environment for inputs.

640445-2

Vendor:AMPD/C:07+

DESCRIPTION The 74LCX05 is a low voltage CMOS OPEN DRAIN HEX INVERTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications. It can be interfaced to 5V signal environment for inputs.

640445-3

Vendor:AMPD/C:07+

TELEFILTERGmbH Potsdamer Straße 18 D 14 513 TELTOW / Germany Tel: (+49) 3328 4784-0 / Fax: (+49) 3328 4784-30 E-Mail: tft@telefilter.com VI TELEFILTER reserves the right to make changes to the product(s) and/or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or informat...

640445-4

Vendor:AMPD/C:07+

Ground planes for the low power circuitry and high power circuitry should be kept separate. The two sections of the hybrid are completely isolated, and can float relative to each other without referencing one to the other. An RC filter will filter out the current spikes and keep the detected noise for that circuit down to a minimum.

640445-7

Vendor:AMPD/C:07+

NOTES : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

640452-6

Vendor:TYCO(AMP)D/C:500

VOUT = adj (.7V min), 1.2, 1.5, 1.6, 1.8, 1.875, 2.5, 3.3V 2.5V VIN 5.5V 15 µA typical quiescent current 350 mA maximum load capability 1 MHz PWM fixed switching frequency (typ.) Automatic PFM/PWM mode switching Available in fixed output voltages as well as an adjustable version SOT23-5 package Low drop out operation - 100% duty cycle mode Internal synchronous rectification for high effi...

640454-9

Vendor:AMPD/C:07+

Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.

640455-4

Vendor:AMPD/C:07+

Supply voltages of +5.0V 5% for VCC and -5.0V 5% for VEE are applied to the board through banana jacks. Both power sources should be well-regulated, and each must be capable of supplying 250mA minimum. During normal operation jumper E-1 must be installed, and nothing is connected to the banana jack labeled OFFSET.

640456-2

Vendor:AMPD/C:07+

The EP111 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gateC toCgate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device.

640456-3

Vendor:AMPD/C:07+

640456-3

Vendor:AMPD/C:07+

640456-8

Vendor:AMPD/C:07+

Often, an SOA curve provides information showing how the safe output current varies with case temperature. This ac- counts for the affect of case temperature on junction tem- perature. Additional lines may show the maximum safe current for pulses of various durations according to the thermal time constants of a device.

640456-9

Vendor:AMPD/C:07+

Precanceller Disable. When held to Logic 1, the internal path from LOUT to the precanceller is forced to VBias thus bypassing the precanceller section. When logic 0, the LOUT to the precanceller path is enabled and functions normally. An internal pulldown (50 kΩ) is provided on this pin.

640457-2

Vendor:AMPD/C:07+

This family of fully featured hot swap power controllers targets applications in the +2.5V to +12V range. The ISL6115 is for +12V control, the ISL6116 for +5V, the ISL6117 for +3.3V and the ISL6120 for +2.5V control applications. Each has a hard wired undervoltage (UV) monitoring and reporting threshold level approximately 80% of the aforementioned voltage.

640457-2

Vendor:AMPD/C:07+

This family of fully featured hot swap power controllers targets applications in the +2.5V to +12V range. The ISL6115 is for +12V control, the ISL6116 for +5V, the ISL6117 for +3.3V and the ISL6120 for +2.5V control applications. Each has a hard wired undervoltage (UV) monitoring and reporting threshold level approximately 80% of the aforementioned voltage.

640457-4

Vendor:AMPD/C:07+

The PCI bus is the main data communication link to the STPC Atlas chip. The STPC Atlas translates appropriate host bus I/O and Memory cycles onto the PCI bus. It also supports the generation of Configuration cycles on the PCI bus. The STPC Atlas, as a PCI bus agent (host bridge class), is compatible with PCI specification 2.1. The chip- set also implements the PCI mandatory header registers in Type...

640457-4

Vendor:AMPD/C:07+

The PCI bus is the main data communication link to the STPC Atlas chip. The STPC Atlas translates appropriate host bus I/O and Memory cycles onto the PCI bus. It also supports the generation of Configuration cycles on the PCI bus. The STPC Atlas, as a PCI bus agent (host bridge class), is compatible with PCI specification 2.1. The chip- set also implements the PCI mandatory header registers in Type...

640457-5

Vendor:AMPD/C:07+

Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disable Low) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Single-Supply Operating Voltage Max Single-Supply Operating Voltage...

640457-7

Vendor:AMPD/C:07+

1. Unless otherwise noted: TC=25C, compensation CC=100pF, DC input specifications are value given, power supply voltage is typical rating. 2. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to achieve high MTBF. 3. Doubles for every 10C of case temperature increase. 4. +VS and -VS denote the positive and negative supply vo...

640457-7

Vendor:AMPD/C:07+

1. Unless otherwise noted: TC=25C, compensation CC=100pF, DC input specifications are value given, power supply voltage is typical rating. 2. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to achieve high MTBF. 3. Doubles for every 10C of case temperature increase. 4. +VS and -VS denote the positive and negative supply vo...

6404SB

Vendor:N/APackage Cooled:SSOP

A block erase operation erases one of the devices 32 k-word blocks typically within 0.39 second (5 V VCC, 12 V VPP), 4 k-word blocks typically within 0.25 second (5 V VCC, 12 V VPP) independent of other blocks. Each block can be independently erased 100 000 times. Block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block.

640500-3

Vendor:AMPD/C:07+

The output of the variable gain amplifier is compared to a threshold value, which is a fixed percentage of the signal peak. In this way, even though the input signal amplitude may fall below the minimum value that can be regulated by the variable gain circuit, the proper detection threshold is maintained.

6405200201

640550-5

Vendor:AMPD/C:07+

Programmable ground control is useful for internal chip signal management. The output buffers of the Fast Func- tion Blocks have an impedance of around 7 Ω when switching high to low, where the High Density Function Blocks impedance is around 14 Ω. Since this low imped- ance is negligible compared to the impedance of the pin inductance when output current transients occur, a rea- sonable ...

640550-8

Vendor:AMPD/C:07+

SDLVL and deasserts low otherwise. SD can be fed back to the enable (EN) input to maintain output stability under a loss of signal condition. EN deasserts the true output signal without removing the input signals. Typically 4.6dB SD hysteresis is provided to prevent chattering.

640551-2

Vendor:AMPD/C:07+

The KBE00S003M is a Multi Chip Package Memory which combines 2Gbit Nand Flash Memory(organized with two pieces of 1G bit Nand Flash Memory) and 512Mbit synchronous high data rate Dynamic RAM.(organized with two pieces of 256Mbit Mobile SDRAM) 2Gbit NAND Flash memory is organized as 256M x8 bits and 512Mbit SDRAM is organized as 8M x16 bits x4 banks. In 2Gbit NAND Flash, Its NAND cell provides the most cost-ef...

640579-2

Vendor:AMPD/C:07+

• Operating temperature from - 55 C to + 110 C • No Base Terminal Connection for Improved Com- mon Mode Interface Immunity • Long Term Stability • Industry Standard Dual-in-Line Package • Lead-free component • Component in accordance to RoHS 2002/95/EC and WEEE 2002/96/EC

640581-1

Vendor:AMPD/C:07+

HY57V56820 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

640584-2

Vendor:AMP/TYCOD/C:07+

You can, however, measure the V-I demand of a motor (or any other load) under actual load conditions. Figure 8 shows a current sense resistor placed in series with the load. With load voltage and current displayed on separate oscilloscope traces, you can find the conditions of maximum stress. Be sure to consider the voltage across the conducting transistor, (VCE), not the amplifier output voltage. The m...

640586-1

Vendor:AMPD/C:07+

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute−maximum−rated conditions for extended periods may affect device reliability. All voltages ...

640621-5

Packaged in the new innovative 3mm x 2mm MLP this combination dual comprises an ultra low saturation PNP transistor and a 1A Schottky barrier diode. This excellent combination provides users with highly efficient performance in applications including DC-DC and charging circuits.

6406273

Vendor:IBMPackage Cooled:模块

(VDD = +4.5V to +5.5V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1µF capacitor at REF, external +4.096V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.)

64063

TEST CONDITION Io=10mA,Tj=25!C Io=10mA Io=10mA, 4.75V<Vin<7V 10mA<Io<800mA Io=1A Io=800mA dVo=100mV 30ms Pulse, Io=800mA f=120Hz, Co=25µF Tantalum, Io=0.5A Io=10mA Tj=125!C, 1000Hrs Tj=25!C, 10Hz<f<10KHz

6406A

Vendor:FAIPackage Cooled:SOIC-8D/C:05+

CASE: Hermetically sealed axial-lead glass DO-35 (DO-204AH) package TERMINALS: Leads, tin-lead plated solderable per MIL-STD-750, method 2026 POLARITY: Cathode indicated by band. Diode to be operated with the banded end positive with respect to the opposite end for Zener regulation MARKING: Part number TAPE & REEL option: Standard per EIA-296 (add TR suffix to part number) WEIGHT: 0.2 grams See packa...

6406-AA

Vendor:FAIRCHILDPackage Cooled:SOP8D/C:97+/99+

A 8051 standard pin is a pseudo open drain pin. It can sink at least 4mA current when output low level, and drive at least 4mA current for 160nS when output transit from low to high, then keep drive 100uA to maintain the pin at a high level. It can be used as input or output function. It needs an external pull up resistor when driving heavy load device.

6406-AB

Vendor:FAIRCHILDPackage Cooled:SOP8D/C:97+/99+

SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C010-12DK. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010-12DK is shipped from Atmel with SDP disabled.

6406-AC

Vendor:FAIRCHILDPackage Cooled:SOP8D/C:97+/99+

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI...

6406FG

Vendor:安普生Package Cooled:SMDD/C:03

Controlled slew rate reduces EMI Over temperature protection with auto-restart Linear current-limit protection Active drain-to-source clamp ESD protection Lead compatible with standard Power MOSFET Low operating input current Monolithic construction

6406IB

The page read operation of the device is controlled by CE and OE inputs. The page size is four words. The first word access of the page read is the same as the asynchronous read. The first word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads within the page being output at a speed of 20 ns. The Page Read Cycle Waveform is shown on ...

6406IVZ

Vendor:HARRICPackage Cooled:07+D/C:800

Logic 0 disables transmission. Logic 1 enables transmission. Low Power Sleep Mode. Logic 0 enables Sleep mode, where ZOUT goes to 400 Ω and supply current is reduced to 4 mA. Logic 1 enables normal operation. Negative Output Signal. Positive Output Signal. Internal Bypass. This pin must be externally ac-coupled (0.1 µF cap). Noninverting Input. DC-biased to approximately VCC/2. Should be ac-c...

6406RD

Vendor:APPackage Cooled:SMD-8D/C:05+

The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew.

640714-1

Vendor:AMP/TYCOD/C:07+

These EMI filters are hermetically packaged in a seam welded enclosure utilizing axially oriented copper-core pins which minimize resistive DC losses. This package has been configured to complement the ART and ARH package as a convenience in system installation and is fabricated with Advanced Analogs rugged ceramic lead-to-package seal assuring long term hermetic seal integrity in harsh environments.

6407A

Vendor:ROHMPackage Cooled:SOP-8

• Plastic package has Underwriters Laboratory Flammability Classification 94V-0 • Low power loss, high efficiency • For use in low voltage high frequency inverters, free-wheeling, and polarity protection applications • Guardring for overvoltage protection

6407SH

Vendor:SSOP-24Package Cooled:PAND/C:2005+

64082

Vendor:MITSUBISHIPackage Cooled:TSSOPD/C:2007+

6408-216-13273

6408-57

Vendor:SANYOPackage Cooled:PQFP44D/C:2007+

640859-4

6408CFS

Package Cooled:SSOP-16

Stability The IRU1261 requires the use of an output capacitor as part of the frequency compensation in order to make the regulator stable. Typical designs for the microprocessor applications use standard electrolytic capacitors with typical ESR in the range of 50 to 100mΩ and the output capacitance of 500 to 1000µF. Fortunately as the ca- pacitance increases, the ESR decreases resulting in a fix...

6408W18B

Vendor:INTELPackage Cooled:BGA0814D/C:02+

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method.

6408W18B

Vendor:INTELPackage Cooled:BGA0814D/C:02+

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method.

6408W30B

Vendor:INTELPackage Cooled:BGA0814D/C:03+

Systems calibrations Electronics level settings Mechanical potentiometers and trimmers® replacements Automotive electronics adjustments Gain control and offset adjustments Transducer circuits adjustments Programmable filters up to 1.5 MHz BW

6408W30T

Vendor:INTELPackage Cooled:BGA0814D/C:03+

640900-1

Vendor:AMPD/C:00+

The Default Disable command resets all conditions to the power on default states. The HT82K628A will re- spond with ACK, clears its output buffer, sets the default key types (scan code set 3 operation only) and typematic rate/delay, and clears the last typematic key. The HT82K628A then stops scanning and awaits further command.

640900-1

Vendor:AMPD/C:00+

The Default Disable command resets all conditions to the power on default states. The HT82K628A will re- spond with ACK, clears its output buffer, sets the default key types (scan code set 3 operation only) and typematic rate/delay, and clears the last typematic key. The HT82K628A then stops scanning and awaits further command.

640917-2

These full reels are individually barcode labeled and placed inside a pizza box (illustrated in figure 1.0) made of recyclable corrugated brown paper with a Fairchild logo printing. One pizza box contains three reels maximum. And these pizza boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped.

640923-1

The actual implementation of this technique produces a waveform that has a slightly slower rise time than the ESD pulse but can be correlated to deliver approximately the same surge current and energy. This controlled impedance pulse provides a more accurate depiction of the trigger voltage of the device because of the reduced voltage overshoot caused by a fast-rising transient and the reactive components ...

640929-1

640941-1

640941-2-F

6409-T00-S-00

640BK

640W18BD

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640W30BD

Vendor:BGA8*9Package Cooled:46D/C:INTEL

Multistandard satellite sound IF device consisting of a mixer and a voltage controlled oscillator (VCO) as a fre- quency converter that can be continuously tuned in 10 kHz increments with crystal accuracy by means of a PLL, two FM limiter amplifiers with PLL FM demodulators followed by two Wegener PANDA1TM expanders. The AF signal passes through two switches. Each switch can select the AF sources and...

64102B02-90U

Vendor:STPackage Cooled:QFP-64D/C:1

Hynix HYMD216M646A(L)6-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden- tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.