Current position: Home > SiteMap Index > Index 6 > Page 36
Index "6"

67643-2910

Vendor:MolexPackage Cooled:connectorD/C:06+

676450002

67645-0002

Vendor:MOLEXD/C:126000

6764-65

Vendor:CXPackage Cooled:N/AD/C:08+

6765P

67665-0010

Vendor:MolexPackage Cooled:connectorD/C:06+

67665-0015

Vendor:MOLEXD/C:07+

67-6777A

Vendor:TOSPackage Cooled:QFPD/C:06+

operation instruction. To utilize this function, the system asserts a read instruction specifying a start location address. Once the 8-bit or 16-bit of the addressed word have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continuously with CS high until the chip select (CS) control pin is brought low. This allows for single instruction data dumps...

67-6777A

Vendor:TOSPackage Cooled:QFPD/C:06+

operation instruction. To utilize this function, the system asserts a read instruction specifying a start location address. Once the 8-bit or 16-bit of the addressed word have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continuously with CS high until the chip select (CS) control pin is brought low. This allows for single instruction data dumps...

67687-2501

Vendor:MOLEXD/C:10100

67687-2950

Vendor:YAGEOD/C:O9+

677-0042-5(51)

Vendor:HRSPackage Cooled:08+D/C:14000

677-0202-0(51)

Vendor:HRSPackage Cooled:08+D/C:1000

677440800

Vendor:MOLEXD/C:06+

The HPR2XX Series is designed for multiple channel applications that require small size and could benefit from a complete one- package solution. The HPR2XX Series offers four isolated channels of output power in a footprint less than the size of many singular devices. This unregulated series of DC/DC converters provides three watts of total output power. Each isolated channel can supply up to 750mW.

67744-0800

The architecture of the Direct RDRAM allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's sixteen banks support up to four simultaneous transactions.

6774463-01

Package Cooled:(LX)high-frequency

Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions.

67746-001

677478-001

• Integrated Gate Drivers and Bootstrap Diodes. • Temperature Monitor • Temperature and Overcurrent shutdown • Fully Isolated Package. • Low VCE (on) Non Punch Through IGBT Technology. • Undervoltage lockout for all channels • Matched propagation delay for all channels • Low side IGBT emitter pins for current control • Schmitt-triggered input logic R...

677478-001

• Integrated Gate Drivers and Bootstrap Diodes. • Temperature Monitor • Temperature and Overcurrent shutdown • Fully Isolated Package. • Low VCE (on) Non Punch Through IGBT Technology. • Undervoltage lockout for all channels • Matched propagation delay for all channels • Low side IGBT emitter pins for current control • Schmitt-triggered input logic R...

677479-001

The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.

677479-001

The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.

67764010

67767003

67791

GENERAL USAGE RS-232 Operation The SP304 is a fully compliant RS-232 device. Its outputs are fully protected against shorts to 20V with no external circuitry. If the potential exists for momentary shorts to voltages greater than 20V, it is recommended that a 220Ω resistor be wired in series with each driver output. This will limit any damage from the higher short-circuit current from these hig...

677G6-014V R02

Vendor:GCE

677G6-028D R03

Vendor:GCE

677G6-041C

Vendor:GCE

677-G6-047C R00

Vendor:GCE

678.156

Vendor:STPackage Cooled:QFP

!Features 1) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see equivalent circuit). 2) The bias resistors consist of thin-film resistors with complete isolation to allow negative biasing of the input. They also have the advantage of almost completely eliminating parasitic effects. 3) Only the on/off conditions need to be set fo...

678.156

Vendor:STPackage Cooled:QFP

!Features 1) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see equivalent circuit). 2) The bias resistors consist of thin-film resistors with complete isolation to allow negative biasing of the input. They also have the advantage of almost completely eliminating parasitic effects. 3) Only the on/off conditions need to be set fo...

67803-0020

Vendor:MolexPackage Cooled:connectorD/C:06+

67803-0030

Vendor:MOLEX

67803-8020

Vendor:MOLEX

6780AS

678205002

678205-002

2. Force IDL Transmit This enhancement is an additional SCP control bit which allows a TE configured MC145474/75 to continue transmission onto the IDL interface regardless of the state of its transmitter. The TEs receiver, though, must be synchronized to INFO 4 incoming from the NT. The following sections of the MC145474/75 data sheet have been changed or added to support this enhancement: Section 7...

678-40-0002

Vendor:MOLEXPackage Cooled:03+D/C:220

67864-0001

Vendor:MolexPackage Cooled:connectorD/C:06+

67865-0001

Vendor:MOLEX

67865-0001

Vendor:MOLEX

67865-0003

Vendor:MolexPackage Cooled:connectorD/C:06+

67865-0003

Vendor:MolexPackage Cooled:connectorD/C:06+

678806-PSAPA

Rail-To-Rail operation Pin-compatible with 3125 Bus Switch & 74 series 125 Single-Supply operation: 2V to 6V Low On-Resistance: 8Ω typical @ 5V Tight match between channels: 0.9Ω typical RON flatness: 3Ω typical Low power consumption: 0.5µ-ohm typical High Speed, TON = 8ns typical High-current channel capability: >100mA Wide bandwidth: >200 MHz Packaging (Pb...

678806-PSAPA

Rail-To-Rail operation Pin-compatible with 3125 Bus Switch & 74 series 125 Single-Supply operation: 2V to 6V Low On-Resistance: 8Ω typical @ 5V Tight match between channels: 0.9Ω typical RON flatness: 3Ω typical Low power consumption: 0.5µ-ohm typical High Speed, TON = 8ns typical High-current channel capability: >100mA Wide bandwidth: >200 MHz Packaging (Pb...

6789-37

D/C:99

The output port is controlled in a similar manner by a free- running read clock (CKR) and a read enable pin (ENR ). In addition, the three FIFOs have an output enable pin (OE ) and a master reset pin (MR ). The read (CKR) and write (CKW) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 30...

67898-032

678D158M025DT5J

678KMP-000

Vendor:CMDPackage Cooled:DIP/42

Disable mode places the device in a sleep state, where quiescent current typically 375µA. When disabled, all outputs are in a high impedance state. Sleep mode can be used for power conservation or to remove the terminator from the SCSI chain.

678KMP-000-KAD0

678KMP-003

Vendor:CMDPackage Cooled:DIPD/C:98

679110001

Vendor:MOLEXD/C:06+

The HC138, HC238, HCT138, and HCT238 are high-speed silicon-gate CMOS decoders well suited to memory address decoding or data-routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low-power Schottky TTL logic. Both circuits have three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine ...

67913-0007

Vendor:MOLEXD/C:577

67926-0011

Vendor:MolexD/C:08+

67926-0040

Vendor:MOLEX

Includes RxPGA, ADC pipeline, and ADIO bus delay relative to fADC. fIN = 5 MHz, AIN = −1.0 dBFS , LPF cut-off frequency set to 15.5 MHz with Reg. 0x08 = 0x80. 3fIN = 5 MHz, AIN = −1.0 dBFS , LPF cut-off frequency set to 26 MHz with Reg. 0x08 = 0x80.

67926-0041

Vendor:MolexD/C:08+

The IRU1011-33 is a fixed linear regulator and it is ca- pable of supplying 1.3A of continuous current over line and temperature range. The IRU1011-33 is stable with low value ceramic capacitors, allowing designers flex- ibility in external component selection. The output is pro- tected by both current limit and thermal shutdown.

67930

Vendor:NSCPackage Cooled:94+D/C:SOP14

monitors the RXK and TX. When the two mirror each other there is no fault. In the event of over temperature, or short circuit to VBAT, the Si9243AEY will turn off the K output to protect the IC. The K pin will stay in high impedance and RXK will follow the K pin. The fault will be reset when TX is toggled high. RXK, RXL and TX pins have internal pull up resistor to VDD while K and L pins have internal ...

67940-3200

67940-3210

Vendor:molexD/C:08+

Applications • Digital fieldbus isolation: DeviceNet, SDS, Profibus • AC plasma display panel level shifting • Multiplexed data transmission • Computer peripheral interface • Microprocessor system interface

67955-0001

Vendor:MolexPackage Cooled:connectorD/C:06+

67955-0001

Vendor:MolexPackage Cooled:connectorD/C:06+

67968

D/C:08+/09+

The M68HC11 K-series microcontroller units (MCUs) are high-performance derivatives of the MC68HC11F1 and have several additional features. The MC68HC11K0, MC68HC11K1, MC68HC11K3, MC68HC11K4 and MC68HC711K4 comprise the series. These MCUs, with a nonmul- tiplexed expanded bus, are characterized by high speed and low power consumption. Their fully static design allows operation at frequencies from 4 MHz to dc.

67968

D/C:08+/09+

The M68HC11 K-series microcontroller units (MCUs) are high-performance derivatives of the MC68HC11F1 and have several additional features. The MC68HC11K0, MC68HC11K1, MC68HC11K3, MC68HC11K4 and MC68HC711K4 comprise the series. These MCUs, with a nonmul- tiplexed expanded bus, are characterized by high speed and low power consumption. Their fully static design allows operation at frequencies from 4 MHz to dc.

67969-0001

Vendor:MolexPackage Cooled:connectorD/C:06+

67972-7

679730001

Vendor:MLXPackage Cooled:9,750

6798-0001

67996-104HLF

67996-104HLF

67996-126

Input used to enable page download mode. When PAGE_EN is high the configuration download address space is partitioned into 4 equal pages. This gives users the ability to easily store and retrieve multiple configuration bitstreams from a single configuration device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired. When SER_EN is Low (ISP mode) t...

67996-128

67996-216

67997-110

67997-210

67997-440

Hynix HYMD264646B(L)8J-J series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

67997-512

67997-602

67997-616

Vendor:FCIPackage Cooled:00+D/C:205

Vo(n) Rem Sense: An external remote sense input is provided for the two lowest voltage outputs, +Vo2 and +Vo3. Connecting the remote sense pins im- proves the load regulation of the applicable output by allowing the regulation circuit to compensate for voltage drop between the converter and load. If desired these inputs may be left disconnected.

67997-616

Vendor:FCIPackage Cooled:00+D/C:205

Vo(n) Rem Sense: An external remote sense input is provided for the two lowest voltage outputs, +Vo2 and +Vo3. Connecting the remote sense pins im- proves the load regulation of the applicable output by allowing the regulation circuit to compensate for voltage drop between the converter and load. If desired these inputs may be left disconnected.

67998-172

67A07

Vendor:MOTD/C:99

Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy state. The user can continuously poll bit 7 of the status register by stopping SCK at a low level once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and once the device i...

67A07

Vendor:MOTD/C:99

Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy state. The user can continuously poll bit 7 of the status register by stopping SCK at a low level once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and once the device i...

67-B304A

Vendor:n/aPackage Cooled:QFPD/C:06+

DESCRIPTION The M28LV16 is a 2K x 8 low power Parallel EEPROM fabricatedwith SGS-THOMSON proprie- tary single polysilicon CMOS technology. The de- vice offers fast access time with low power dissipation and requires a 2.7V to 3.6V power supply. The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshaking with Data Polling and Toggle B...

67B366A

Vendor:MITSUMIPackage Cooled:QFPD/C:06+

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

67-B367A-238

Vendor:MITSUMIPackage Cooled:QFPD/C:06+

128 macrocells in eight logic array blocks (LABs) 20 dedicated inputs, up to 64 bidirectional I/O pins Programmable interconnect array Advanced 0.65-micron CMOS technology to increase performance • Available in 84-pin CLCC, PLCC, and 100-pin PGA, PQFP

67B523B

Vendor:MITSUMIPackage Cooled:QFPD/C:06+

67C05

The GS82032A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.

67C13

Package Cooled:08+D/C:800

L = 25-50 MHz, M = 50-300 MHz, U = 300-400 MHz Upper range coupling 0.75 dB L = 40-100 MHz, M = 100-200 MHz L = fL-2fL 4-coupled ports, Isolation between coupled ports, 25 dB minimum. Insertion loss specification in L range may degrade up to 1dB at cold temperature, -55C When only specification for M or MU range given, specification applies to entire frequency range. Denotes 75 Ohm models General Q...

67C401-15J

The XC2164 series are high frequency, low current consumption CMOS ICs with built-in crystal oscillator and divider circuits. For fundamental oscillation, output is selectable from any one of the following values for f0 : f0/1, f0/2, f0/4, f0/8. With oscillation capacitors and a feedback resistor built-in, it is possible to configure a stable fundamental oscillator or 3rd overtone oscillator using only an ex...

67C402-35N

Vendor:MMIPackage Cooled:N/AD/C:0 0

The receive (D/A) filter provides interpolation filtering on the 8 kHz sample and hold signal from the codec. The filter consists of a 3.4 kHz lowpass fifth-order elliptic section clocked at 128 kHz and performs bandlimiting and smoothing of the 8 kHz "staircase" waveform. In addition, sinx/x gain correction is applied to the signal to compensate for the attenuation of higher frequencies caused by t...

67CXFOT

Package Cooled:SOP16

Edition 02.97 This edition was realized using the software system FrameMaker®. Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 Mnchen © Siemens AG 7/23/97. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits...

67F045

Vendor:1600

The INT5130 operates on both 2.5V and 3.3V supplies, offers 5V I/O tolerance, and is packaged in a 144-pin LQFP. Intellon offers a complete solution for powerline communication applications by providing the INT5130 in conjunction with the INT1000 Analog Conversion IC.

67F045

Vendor:1600

The INT5130 operates on both 2.5V and 3.3V supplies, offers 5V I/O tolerance, and is packaged in a 144-pin LQFP. Intellon offers a complete solution for powerline communication applications by providing the INT5130 in conjunction with the INT1000 Analog Conversion IC.

67F050

D/C:03+

Mounting a high resolution or three channel encoder with Module Side A as the mounting plane requires alignment pins in the motor base. These alignment pins provide the necessary centering of the module with respect to the center of the motor shaft. In addition to centering, the codewheel gap is also important. Please refer to the respective encoder data sheet for necessary mounting informa...

67F050

D/C:03+

Mounting a high resolution or three channel encoder with Module Side A as the mounting plane requires alignment pins in the motor base. These alignment pins provide the necessary centering of the module with respect to the center of the motor shaft. In addition to centering, the codewheel gap is also important. Please refer to the respective encoder data sheet for necessary mounting informa...

67F0500353

Vendor:AIRPAXPackage Cooled:07+D/C:TO-220

Meets SONET requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: 100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range: 3 mV to 15 mV Single reference clock frequency for all rates, including 15/14 (7%) wrapper rate Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK LVPECL/LVDS/...

67F053

R2 sets the balanced output impedance to 500 Ω. L1 and C2 serve dual purposes. L1 serves as an output bias choke, and C2 serves as a series DC block. In addition, the values of L1 and C2 may be chosen to form an impedance matching network of the load impedance is not 500 Ω. Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circuit at the IF when the load impedance i...

67F055

Vendor:AIRPAXPackage Cooled:SALE--STOCK!!D/C:08+

The 67F055 is an integral part of the signal chain for HBL. The driver has been optimized for flat gain response and reduced harmonic distortion and noise in the bands of interest to improve the overall signal to noise in the system. A unique internal compensation circuit eliminates the need for external common mode snubber filters in active termination applications.

67F060

Vendor:availPackage Cooled:AIRPAXD/C:05+

Sck C The standard product is delivered with an internal clock option (800kHz). This pin should be grounded when operating with the internal clock. An external clock option can be special ordered from the factory allowing the user to input a clock signal between 400kHz And 1.6MHz

67F065

Vendor:AIRPAXPackage Cooled:SALE--STOCK!!D/C:08+

Replace any reference to Flash Interface Unit with Flash Memory Module; changed example in Part 2.2; added note on VREFH and VREFLO in Table 2-2 and Table 11-1; added note to Vcap pin in Table 2-2; corrected typo FIVAL1 and FIVAH1 in Table 4-12; removed unneccessary notes in Table 10-12; corrected temperature range in Table 10-14; added ADC calibration information to Table 10-24 and new graphs in Figure 1...

67F075

Package Cooled:08+D/C:2000

Current Word Register Each channel has a 16-bit Current Word Count register. This register determines the number of transfers to be performed. The word count is decremented after each transfer. When the value in the register goes from zero to FFFFH, a TC will be generated. This register is loaded or read by the microproc- essor in the Program Condition.

Page: Pages: 36/60  At 10 31 32 33 34 35 36 37 38 39 40 Under 10
Home | About Us | Link | Contact | Website map

© 2008 SeekChips.com Corp.All Rights Reserved.