74HCT157DR

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Defense Supply Center Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, OH 43216-5000, using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

74HCT157DR

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Defense Supply Center Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, OH 43216-5000, using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

74HCT157DR2G

LO IN=-4dBm See note 1 and 2. Mixer Preamp ON Mixer Preamp OFF Mixer Preamp ON Mixer Preamp OFF Mixer Preamp ON Mixer Preamp OFF Mixer Preamp ON/Mixer/LO Input Amps Mixer Preamp OFF/Mixer/LO Input Amps Mixer Preamp ON Mixer Preamp OFF High and Low Side LO Injection. See note 3 and 4. Typical IF frequencies: 85.38MHz, 109.80MHz, 111.85MHz, 183.6MHz

74HCT157DTR2G

Vendor:ONPackage Cooled:TSSOP16D/C:0719+

74HCT157E

Vendor:HARPackage Cooled:99+D/C:DIP

Both the The MMC2080/2075 are members of the low-power, high-performance M•CORE family of 32-bit microcontroller units (MCUs). The M•CORE is a streamlined execution engine that provides many of the performance enhancements found in mainstream reduced instruction set computers (RISCs). Combining performance, speed, and cost efficiency in a compact, low-power design, the M•CORE microRISC arc...

74HCT157E

Vendor:HARPackage Cooled:99+D/C:DIP

Both the The MMC2080/2075 are members of the low-power, high-performance M•CORE family of 32-bit microcontroller units (MCUs). The M•CORE is a streamlined execution engine that provides many of the performance enhancements found in mainstream reduced instruction set computers (RISCs). Combining performance, speed, and cost efficiency in a compact, low-power design, the M•CORE microRISC arc...

74HCT157N652

Vendor:NXPPackage Cooled:N/AD/C:08+

The EDB7211-2 development kit is a complete devel- opment platform with access to the features and capabilities of the EP7211. The kit provides the tools required for developing and testing the design of a highly integrated EP7211 system.

74HCT157N652

Vendor:NXPPackage Cooled:N/AD/C:08+

The EDB7211-2 development kit is a complete devel- opment platform with access to the features and capabilities of the EP7211. The kit provides the tools required for developing and testing the design of a highly integrated EP7211 system.

74HCT157PW

Vendor:PHIPackage Cooled:TSSOPD/C:2006

When power is applied to VDD, an internal power-on reset holds the PCA74HCT157PW in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA74HCT157PW registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.

74HCT157PW

Vendor:PHIPackage Cooled:TSSOPD/C:2006

When power is applied to VDD, an internal power-on reset holds the PCA74HCT157PW in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA74HCT157PW registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.

74HCT157T

Several simplifications help to approximate the available output current. Assume zero forward drops in the diodes, and a zero shunt voltage in the IC regulator. With (for example) a 60Hz sinusoidal input of 24VRMS amplitude (Vpeak = 33.94V), you can then calculate as follows:

74HCT158D

Vendor:PHIPackage Cooled:SOP16SD/C:2007+

Lead temperature (soldering, 10 sec.)Tsol+300 † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute−maximum−rated conditions for extended p...

74HCT158N

TXD is an input, used to transfer serial Data or Preamble/Header information bits from the MAC or network processor to the HSP3824. The data is received serially with the LSB first. The data is clocked in the HSP3824 at the falling edge of TXCLK.

74HCT15TN

Vendor:PHIPackage Cooled:DIP-16D/C:9727

OSC IN/ These pins form an on-chip reference oscillator when a series resonant crystal is connected across OSC OUT them. Capacitors of appropriate value are also required between each end of the crystal and ground to provide the necessary additional phase shift. The addition of a 220Ω resistor between OSC OUT and the crystal will improve stability. An external reference signal may, alternatively, b...

74HCT160

Vendor:10Package Cooled:99/00+D/C:TSSOP16

FEATURES High Performance Member of Pin-Compatible TxDAC Product Family Excellent Spurious-Free Dynamic Range Performance SNR @ 5 MHz Output, 125 MSPS: 73 dB Twos Complement or Straight Binary Data Format Differential Current Outputs: 2 mA to 20 mA Power Dissipation: 135 mW @ 3.3 V Power-Down Mode: 15 mW @ 3.3 V On-Chip 1.20 V Reference CMOS-Compatible Digital Interface Package: 28-Lead SOIC and ...

74HCT160

Vendor:10Package Cooled:99/00+D/C:TSSOP16

FEATURES High Performance Member of Pin-Compatible TxDAC Product Family Excellent Spurious-Free Dynamic Range Performance SNR @ 5 MHz Output, 125 MSPS: 73 dB Twos Complement or Straight Binary Data Format Differential Current Outputs: 2 mA to 20 mA Power Dissipation: 135 mW @ 3.3 V Power-Down Mode: 15 mW @ 3.3 V On-Chip 1.20 V Reference CMOS-Compatible Digital Interface Package: 28-Lead SOIC and ...

74HCT160D

Vendor:PHIPackage Cooled:SOPD/C:01+

The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177−...

74HCT160N

Vendor:ELCAP

The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques.

74HCT161

Vendor:HARPackage Cooled:DIP-16LD/C:1992

1. Hitachi neither warrants nor grants licenses of any rights of Hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Pr...

74HCT161D-T

Vendor:ＮＸＰ

74HCT162374ETPA

Vendor:IDTPackage Cooled:TSOPD/C:99+

The result of the most recent Main Memory Page to Buffer Compare operation is indi- cated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer.

74HCT162374ETPA

Vendor:IDTPackage Cooled:TSOPD/C:99+

The result of the most recent Main Memory Page to Buffer Compare operation is indi- cated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer.

74HCT162D

Vendor:PHILIPSPackage Cooled:9844D/C:1022

(*) Our SO-8 package used for Voltage Regulators is modified internally to have pins 2, 3, 6 and 7 electrically communed to the die attach flag. This particular frame decreases the total thermal resistance of the package and increases its ability to dissipate power when an appro- priate area of copper on the printed circuit board is available for heat-sinking. The external dimensions are the same as for the...

74HCT162D

Vendor:PHILIPSPackage Cooled:9844D/C:1022

(*) Our SO-8 package used for Voltage Regulators is modified internally to have pins 2, 3, 6 and 7 electrically communed to the die attach flag. This particular frame decreases the total thermal resistance of the package and increases its ability to dissipate power when an appro- priate area of copper on the printed circuit board is available for heat-sinking. The external dimensions are the same as for the...

74HCT164

Vendor:PI

Figure 5 shows the output levels overlayed using a storage scope. The attack rate is determined by the step size and the value of CAV. The attack time to final value is a function of the step size increase. Table I shows the values of total settling times to within 5 dB, 3 dB, 2 dB and 1 dB of final value with CAV = 10 µF. When step sizes exceed 40 dB, the increase in settling time for larger steps ...

74HCT164D

Vendor:PHIPackage Cooled:SOP3.9mm-14LD/C:2002

Notes 1. Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation. 2. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ...

74HCT164D(SMD) D/C00 2

Vendor:PHID/C:0

74HCT164DT

Vendor:PHID/C:04+

Notes: a. Room = 25C, Full = as determined by the operating suffix. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Typical values are for design aid only, not guaranteed nor subject to production testing. d. Guarantee by design, nor subjected to production test. e. VIN = input voltage to perform proper function.

74HCT164D-T

Vendor:ＮＸＰ

Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification Supports ISP via Jam Standard Test and Programming Language (STAPL) Supports Joint Test Action Group (JTAG) boundary scan nINIT_CONF pin allows private JTAG instruction to initiate FPGA configuration Internal pull-up resistor on nINIT_CONF always enabled User programmable weak internal pull-up resistors on nCS and OE ...

74HCT164E

Vendor:RACPackage Cooled:DIPD/C:06+

After the Master sends a START condition and the slave address byte, the CAT24FC02 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24FC02 then performs a Read or a Write operation depending on the state of the R/W bit.

74HCT164E

Vendor:RACPackage Cooled:DIPD/C:06+

After the Master sends a START condition and the slave address byte, the CAT24FC02 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24FC02 then performs a Read or a Write operation depending on the state of the R/W bit.

74HCT164M

Vendor:stPackage Cooled:sopD/C:90+

SUMMARY DESCRIPTION The M68AF511AL is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation re- quiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 4.5 to 5.5V supply.

74HCT164M

Vendor:stPackage Cooled:sopD/C:90+

SUMMARY DESCRIPTION The M68AF511AL is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation re- quiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 4.5 to 5.5V supply.

74HCT164PW

Vendor:PHILIPSPackage Cooled:00+D/C:TSSOP

synchronous static RAM designed to provide a burstable, high-performance memory for high speed networking and communication applications. It is organized as 131,072 words by 32 bits or 36 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass...

74HCT165

Package Cooled:99D/C:3496

Full Compliance with T1.413 Issue-2, ITU-T G.992.1 (G.dmt) and G.992.2 (G.lite). FDM and EC-based DMT Line Coding Data Rate: over 8Mbps for Downstream and 640 Kbps for Upstream. Reach: 6.7 Km (22Kft) with 24 AWG and 5.5 Km (18 Kft) with 26 AWG Supports Rate Adaptive Mode (steps of 32kbps) Reed-Solomon Forward Error Correction with(or without) Interleaver Adaptive Frequency and Time Domain Equalizer. Trellis ...

74HCT165D

Vendor:SPackage Cooled:N/AD/C:93

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance ...

74HCT165D652

For applications requiring other voltages, see LM150 series adjustable regulator data sheet. Operation is guaranteed over the junction temperature range −55˚C to +150˚C for LM123, −40˚C to +125˚C for LM323A, and 0˚C to +125˚C for LM323. A hermetic TO-3 package is used for high reliability and low thermal resistance.

74HCT165D652

For applications requiring other voltages, see LM150 series adjustable regulator data sheet. Operation is guaranteed over the junction temperature range −55˚C to +150˚C for LM123, −40˚C to +125˚C for LM323A, and 0˚C to +125˚C for LM323. A hermetic TO-3 package is used for high reliability and low thermal resistance.

74HCT165D653

Vendor:PHILIPS/NXP

Hynix HYMD132G725B(L)8-M/K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD132G725B(L)8-M/ K/H/L series consists of eighteen 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD132G725B(L)8-M/K/H/L series provide a high performance 8-byte interface in 5....

74HCT165E

Vendor:RCAPackage Cooled:DIPD/C:83+

These N-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switching DC/DC converte...

74HCT165N

Vendor:PHPackage Cooled:00+D/C:DIP-16

250 ps propagation delay input to output 50 ps propagation delay dispersion Differential PECL compatible outputs Differential latch control Robust input protection Input common-mode range −2.0 V to +3.0 V Input differential range 5 V ESD protection >3 kV HBM, >200 V MM Power supply sensitivity >65 dB 200 ps minimum pulsewidth 5 GHz equivalent input rise time bandwidth Typical output...

74HCT165PW

Vendor:PHI/NXPPackage Cooled:TSSOPD/C:2008+

Data Registers (DR) The potentiometer has four 10-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms.

74HCT165PW

Vendor:PHI/NXPPackage Cooled:TSSOPD/C:2008+

Data Registers (DR) The potentiometer has four 10-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms.

74HCT166

D/C:02+

PLL P and Q data is spread between three bytes. Each byte becomes active on the acknowledge for that byte, so changing P and Q data for an active PLL will likely cause the PLL try to lock on an out-of-bounds condition. For this reason, it is recommended that the PLL being programmed be turned off during the update. This can be done by setting the PLL*_En bit LOW.

74HCT173D

Vendor:PHIPackage Cooled:00+D/C:SOP-16

The XP132A1275SR is a P-Channel Power MOS FET with low on-state resistance and ultra high-speed switching characteristics. Because high-speed switching is possible, the IC can be efficiently set thereby saving energy. The small SOP-8 package makes high density mounting possible.

74HCT173N

Vendor:PHIPackage Cooled:DIP-16D/C:9727

sFEATURES q Operating Voltage5V q Internal 6dB Amplifier q Internal 75Ω Driver Circuit thq Quad 5 order Butter worth Low Pass Filter q Internal High Impedance output control switch q 41dB Stop Band Rejection at 27MHz q Bipolar Technology q Package OutlineDMP20

74HCT174

Vendor:TIPackage Cooled:08+D/C:780

KEY FEATURES 80 MHz (12.5 ns) Core Instruction Rate Single-Cycle Instruction Execution, Including SIMD Operations in Both Computational Units 480 MFLOPS Peak and 320 MFLOPS Sustained Performance (Based on FIR) Dual Data Address Generators (DAGs) with Modulo and Bit-Reverse Addressing Zero-Overhead Looping and Single-Cycle Loop Setup, Providing Efficient Program Sequencing IEEE 1149.1 JTAG Standar...

74HCT174A

Vendor:N/APackage Cooled:NSCD/C:06+

Maximum Output Current: 250 mA. Highly Accurate Output Voltage +/- 1.4% Only 19µA Power Consumption MAX Shutdown Supply Current 1µA Ground Current of Less than 5µA Very Low Dropout 0.12V at 100mA 0.23V at 250mA Shutdown Mode for Power Savings With ON/OFF & BYPASS Features Offered in SOT-89 & SOT-25 Packages PIN-to-PIN S-818

74HCT174D(SMD2.5K/RL) D/C00

Vendor:PHID/C:0

74HCT174D652

DESCRIPTION The 74VHCT03A is an advanced high-speed CMOS QUAD 2-INPUT OPEN DRAIN NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provides high noise immunity and stable output. This device can, with an external pull-up resistor, be used in wired AND configuration. This devi...

74HCT174D652

DESCRIPTION The 74VHCT03A is an advanced high-speed CMOS QUAD 2-INPUT OPEN DRAIN NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provides high noise immunity and stable output. This device can, with an external pull-up resistor, be used in wired AND configuration. This devi...

74HCT174D653

Vendor:PHILIPSD/C:O9+

The ADC122S101 is a low-power, two-channel CMOS 12-bit analog-to-digital converter with a high-speed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC122S101 is fully speci- fied over a sample rate range of 500 kSPS to 1 MSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circui...

74HCT174D653

Vendor:PHILIPSD/C:O9+

The ADC122S101 is a low-power, two-channel CMOS 12-bit analog-to-digital converter with a high-speed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC122S101 is fully speci- fied over a sample rate range of 500 kSPS to 1 MSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circui...

74HCT174D-T

Vendor:ＮＸＰ

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

74HCT174M

Vendor:TIPackage Cooled:SOPD/C:02+

Output Adjustment all HR151 models (single output): The output can be adjusted upward by using the output adjust (pin3). The resistance between output adjust (pin 3) and output common (pin 4) will determine the magnitude of the increase in the output. The table above is only applicable to HR151-2805.

74HCT174T

Serial Interface The 74HCT174T supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive opera...

74HCT175

Vendor:NSPackage Cooled:SOIC16D/C:04+

Notes a. CSTRAY < 5 pF on COSC. After Start-Up, VDD of w 3 V. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Guaranteed by design, not subject to production testing.

74HCT175D653

For the clock signal, use the crystal connected to XTAL EXTAL pin with which the clock signal is obtained by the self-oscillation at the crystal oscillation circuit, or external signal supplied through EXTAL pin. The frequency of the clock obtained by the self-oscillation is 2.822 MHz (or 44.1 kHz * 64). The internal operation is carried out with 512 fs clock that is made by the PLL. Insert an analog filte...

74HCT175DB

Software features Program Suspend & Resume: read other sectors before programming operation is completed Erase Suspend & Resume: read/program other sectors before an erase operation is completed Data# polling & toggle bits provide status Unlock Bypass Program command reduces overall multiple-word or byte programming time CFI (Common Flash Interface) compliant: allows host system...

74HCT175DR2

Vendor:PHID/C:96

74HCT175D-T

Vendor:ＮＸＰ

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be m...

74HCT175M

The MAX6950 and MAX6951 were intended to drive single-digit displays, and this allows the segments for each digit to be routed to the correct driver pin. Many dual-digit displays pin out the two digits separately, treating the digits as two singles in one package. These can be driven directly by the MAX6950 and MAX6951. Other dual-digit displays internally pair the segment anodes for the two digits (Figure ...

74HCT175M96

Vendor:TI

On page 3-31, the last paragraph implies that either a software breakpoint (BKPT instruction) or hardware breakpoint can be used to insert an instruction. As noted in the following paragraphs, only a software breakpoint can be used to insert an instruction on the breakpoint acknowledge cycle.

74HCT175M96

Vendor:TI

On page 3-31, the last paragraph implies that either a software breakpoint (BKPT instruction) or hardware breakpoint can be used to insert an instruction. As noted in the following paragraphs, only a software breakpoint can be used to insert an instruction on the breakpoint acknowledge cycle.

74HCT175P

Figure 2 on Page 5 shows one sample configuration of a SPORT using the precision clock generator to interface with an I2S ADC and an I2S DAC with a much lower jitter clock than the serial port would generate itself. Many other SRU configurations are possible.

74HCT175PW

Vendor:PHILIPSPackage Cooled:SOPD/C:05+

Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impeda...

74HCT181N3

The first step in choosing the right product is to select the diode type. All of the products in the HSMS-282A family use the same diode chip, and the same is true of the HSMS-281A and HSMS-280A families. Each family has a different set of characteristics which can be compared most easily by consulting the SPICE parameters in Table 1.

74HCT186PW

Vendor:M/NPackage Cooled:TSSOPD/C:00+

74HCT191D

Analog composite video signal output or Cb or B signal output current drive(positive) Analog composite video signal output or Cb or B signal output current drive(negative) Power Supply for CVBS / Cb / B DAC1 circuit Analog luminance or G signal output current drive(positive) Analog luminance or G signal output current drive(negative) Power Supply for Y / G DAC1 circuit Analog chrominance signal output o...

74HCT191N

*Specifications same as ISO120BG, ISO121BG. NOTE: (1) Input voltage range = 10V for VS1, VS2 = 4.5VDC to 18VDC. (2) Ripple frequency is at carrier frequency. (3) Overload recovery is approximately three times the settling time for other values of C2. (4) The SG-grade is specified C55C to +125C; performance of the SG in the C25C to +85C temperature range is the same as the BG-grade.

74HCT193N

Vendor:380

The TS7221 is amicropower comparator featuring rail to rail input performance in a tiny SOT23-5 package. This comparator is ideally suited to space and weight critical applications. It is fully specified at 2.7V, 5V and 10V operations over the industrial temperature range (-40/+85C).

74HCT193N

Vendor:380

The TS7221 is amicropower comparator featuring rail to rail input performance in a tiny SOT23-5 package. This comparator is ideally suited to space and weight critical applications. It is fully specified at 2.7V, 5V and 10V operations over the industrial temperature range (-40/+85C).

74HCT194D

Vendor:PHIPackage Cooled:SOP16SD/C:2007+

1. Externally detect a write to the low-power address. You select this address which can be any address in the 16 Mbyte addressing range of the MC68SEC000. A write to the low-power address can be detected by polling A23CA0, R/W, and FC2CFC0. When the low-power address is detected, R/W is a logic low, and the function codes have a five (101) on their output, the processor is writing to the low-power add...

74HCT195

Vendor:TIPackage Cooled:DIP

and sets the output buffer in the 3-state condition. MR can be left floating since an internal pull-up resistor will make the MR inactive. In the HCT version, the MR input and the two mode select pins S1 and S2 are TTL compatible, but the X1 input has CMOS input switching levels and may be driven by a TTL output using a pull-up resistor connected to VCC.

74HCT195

Vendor:TIPackage Cooled:DIP

and sets the output buffer in the 3-state condition. MR can be left floating since an internal pull-up resistor will make the MR inactive. In the HCT version, the MR input and the two mode select pins S1 and S2 are TTL compatible, but the X1 input has CMOS input switching levels and may be driven by a TTL output using a pull-up resistor connected to VCC.

74HCT195N

Vendor:PHILIPSPackage Cooled:DIP-16D/C:6+

74HCT1G00GV

1. Corrected the errata 2. Added Data Protection flow chart. 3. Removed Cache Read Operation. 4. Added additional information on command register. 5. Revised Interrupt status register information. 6. Added INT pin schematic. 7. Changed tPGM1 to 205 from 320us, tPGM2 to 220 from 350us. 8. Revised AC/DC parameters 9. Revised ECC Bypass Description 10. Revised Reset Parameters and Timing Diagrams.

74HCT1G00GW

Vendor:PHIPackage Cooled:SOT353-1D/C:2006+

Boundary scan instructions and associated data registers support a standard methodology for accessing and config- uring Virtex-II devices that complies with IEEE standards 1149.1 - 1993 and 1532. A system mode and a test mode are implemented. In system mode, a Virtex-II device per- forms its intended mission even while executing non-test boundary-scan instructions. In test mode, boundary-scan test ins...

74HCT1G00GW

Vendor:PHIPackage Cooled:SOT353-1D/C:2006+

Boundary scan instructions and associated data registers support a standard methodology for accessing and config- uring Virtex-II devices that complies with IEEE standards 1149.1 - 1993 and 1532. A system mode and a test mode are implemented. In system mode, a Virtex-II device per- forms its intended mission even while executing non-test boundary-scan instructions. In test mode, boundary-scan test ins...

74HCT1G02GW

Vendor:PHILIPS ?Package Cooled:04+?D/C:3000

The relays can switch currents in the range of nano- amps to hundreds of milliamps. The MOSFET switches are ideal for small signal switching and are primarily suited for dc or audio frequency applica- tions. The LH1518 relays feature a monolithic output die that minimizes wire bonds and permits easy integra- tion of high-performance circuits such as current lim- iting in normally-open switches. The ...

74HCT1G02GW-G

Vendor:ＮＸＰ

74HCT1G04GW125

The 74HCT1G04GW125 (single) is available in SOT23-5 and SO-8 packages, and the 74HCT1G04GW125 (dual) is available in MSOP-8 and SO-8 packages. The 74HCT1G04GW125 (single with shutdown) is available in MSOP-8 and SO-8. The 74HCT1G04GW125 (dual with shutdown) is available in MSOP-10. All versions are specified for operation from −40C to +125C.

74HCT1G08GV

Vendor:PHIPackage Cooled:SOT753D/C:2006+

The MAX5026 successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxims continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxims quality and reliability standards.

74HCT1G08GW

74HCT1G08GW

74HCT1G125GV

Vendor:PHIPackage Cooled:SOT753D/C:2006+

put, although this does improve transient response. Input by- passing is needed only if the regulator is located far from the filter capacitor of the power supply. For output voltage other than 5V, 12V and 15V the LM117 series provides an output voltage range from 1.2V to 57V.

74HCT1G125GW

Vendor:PHILIPSPackage Cooled:SOT-353D/C:00+

The customer¢s voice sources are recorded sec- tion by section into an internal mask ROM. The sectional playback arrangement instructions of each key are stored in the table ROM. The key features are also programmable. With such a flexible structure, the HT815D0 is excellent for versatile voice applications.

74HCT1G125GW.125

Vendor:PHILIPSPackage Cooled:SOT353D/C:05+

74HCT1G126G

Vendor:PHILIPSPackage Cooled:SOT-353D/C:05+NOPB

Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Parallel Data Inputs Parallel Enable Input (Active LOW) Flip-Flop Outputs Terminal Count Output

74HCT1G126G

Vendor:PHILIPSPackage Cooled:SOT-353D/C:05+NOPB

Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Parallel Data Inputs Parallel Enable Input (Active LOW) Flip-Flop Outputs Terminal Count Output

74HCT1G126GV

Vendor:PHIPackage Cooled:SOT753D/C:2006+

SNR 102dB (A weighted @ 48kHz) THD -90dB (at C1dB) Sampling Frequency: 8 C 192kHz Master or Slave Clocking Mode System Clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs Audio Data Interface Modes - 16-24 bit I2S, 16-24 bit Left, 16-24 bit Right Justified Supply Voltages - Analogue 2.7 to 5.5V - Digital core: 2.7V to 3.6V 20-pin SSOP package

74HCT1G126GV

Vendor:PHIPackage Cooled:SOT753D/C:2006+

SNR 102dB (A weighted @ 48kHz) THD -90dB (at C1dB) Sampling Frequency: 8 C 192kHz Master or Slave Clocking Mode System Clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs Audio Data Interface Modes - 16-24 bit I2S, 16-24 bit Left, 16-24 bit Right Justified Supply Voltages - Analogue 2.7 to 5.5V - Digital core: 2.7V to 3.6V 20-pin SSOP package

74HCT1G126GW

Vendor:PHILIPSPackage Cooled:N/AD/C:04+

Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment.

74HCT1G126GW125N

74HCT1G14GV.125

74HCT1G14GW

Package Cooled:PhilipsD/C:06+

COMPENSATION FOR THE CHANGE IN SENSITIVITY OVER TEMPERATURE All thermal accelerometers display the same sensitivity change with temperature. The sensitivity change depends on variations in heat transfer that are governed by the laws of physics. Manufacturing variations do not influence the sensitivity change, so there are no unit-to-unit differences in sensitivity change. The sensitivity change is gove...

74HCT1G32GV.125

74HCT1G32GW115

Vendor:PHILIPSD/C:0320

Ausgabe 07.99 Herausgegeben von Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 Mnchen © Siemens AG 1995. Alle Rechte vorbehalten. Wichtige Hinweise! Gewähr fr die Freiheit von Rechten Dritter leisten wir nur fr Bauelemente selbst, nicht fr Anwendungen, Verfahren und fr die in Bauelementen oder Baugruppen realisierten Schaltungen. Mit den Angaben w...

74HCT1G32GW115

Vendor:PHILIPSD/C:0320

Ausgabe 07.99 Herausgegeben von Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 Mnchen © Siemens AG 1995. Alle Rechte vorbehalten. Wichtige Hinweise! Gewähr fr die Freiheit von Rechten Dritter leisten wir nur fr Bauelemente selbst, nicht fr Anwendungen, Verfahren und fr die in Bauelementen oder Baugruppen realisierten Schaltungen. Mit den Angaben w...

74HCT1G32GW125N