7132-LA100J

Vendor:IDTPackage Cooled:PLCC52D/C:99+

7132LA35C

7132LA55PDGI

7132-LA90J

Vendor:IDTPackage Cooled:PLCC52D/C:92+

7132SA100J

D/C:01+

a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction tem- perature of 175C for an extended period can result in device failure. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 2.

7132SA20J

Vendor:IDTPackage Cooled:QFPD/C:95

The SD1010A implements four advanced display technologies: 1. Advanced mode detection and auto-calibration without any external CPU assist 2. Advanced programmable interpolation algorithm 3. Stand-alone mode support, and 4. Advanced true color support with both dithering and frame modulation.

7132SA55J

7132SA90J

D/C:01+

DESCRIPTION The HOA0901 sensor consists of a dual channel IC detector and an IRED encased in a black thermoplastic housing. The device is typically used with an interrupter strip or disk (code wheel) to encode the rate and direction of mechanical motion. Applications include linear and rotary encoders; it is especially suited for the encoding function in an optical mouse. As the interruptive pattern ...

7132SA90J

D/C:01+

DESCRIPTION The HOA0901 sensor consists of a dual channel IC detector and an IRED encased in a black thermoplastic housing. The device is typically used with an interrupter strip or disk (code wheel) to encode the rate and direction of mechanical motion. Applications include linear and rotary encoders; it is especially suited for the encoding function in an optical mouse. As the interruptive pattern ...

7133A260 QHH6QS

Vendor:INTELPackage Cooled:01+D/C:BGA

7133SA55J

D/C:01+

The TTL level LOOP pin is used to perform loop-back testing. When LOOP is asserted (held LOW) the Transmitter serial in- put (TSER) is used by the Receiver PLL for clock and data recovery. This allows in-system testing to be performed on the entire device except for the differential Transmit drivers (TOUT) and the differential Receiver inputs (RIN). For ex- ample, an ATM controller can present ATM cell...

7133SA90

Vendor:IDTPackage Cooled:30D/C:N/A

The M divider divides the VCSO output frequency, feeding the result into the plus input of the phase detector. The output of the R divider is fed into the minus input of the phase detector. The phase detector compares its two inputs. The phase detector output, filtered externally, causes the VCSO to increase or decrease in speed as needed to phase- and frequency-lock the VCSO to the reference input.

71342 SA35J

Vendor:IDTPackage Cooled:PLCC52D/C:2007+

71342LA35J

71342LA45J

713432-2

Vendor:NSD/C:08+

7134-4282

Vendor:0Package Cooled:07＋D/C:496

7134-4284

Vendor:0Package Cooled:07＋D/C:392

71349

Vendor:MITELPackage Cooled:SOP14D/C:07+

Comparator hysteresis can be increased with the addition of resistor RH. The hysteresis equation has been simplified and does not account for the change of input current Iin as VCC crosses the comparator threshold (Figure 4). An increase of the lower threshold ∆Vth(lower) will be observed due to Iin which is typically 340 µA at 4.59 V. The equations are accurate to 10% with RH less than 150 ...

71349

Vendor:MITELPackage Cooled:SOP14D/C:07+

Comparator hysteresis can be increased with the addition of resistor RH. The hysteresis equation has been simplified and does not account for the change of input current Iin as VCC crosses the comparator threshold (Figure 4). An increase of the lower threshold ∆Vth(lower) will be observed due to Iin which is typically 340 µA at 4.59 V. The equations are accurate to 10% with RH less than 150 ...

7134LA20J

This CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Office. It provides simultaneous connections for up to 256 64kbit/s channels. Each of the eight serial inputs and outputs consist of 32 64kbit/s channels multiplexed to form a 2048kbit/s ST-BUS stream. In addition, the IMP8980D provides microprocessor read...

7134LA20J

This CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Office. It provides simultaneous connections for up to 256 64kbit/s channels. Each of the eight serial inputs and outputs consist of 32 64kbit/s channels multiplexed to form a 2048kbit/s ST-BUS stream. In addition, the IMP8980D provides microprocessor read...

7134SA20J

Vendor:IDTPackage Cooled:436D/C:1335

Data pin for I2C circuitry 5V tolerant Clock input of I2C input Analog ground pins PCI clock outputs, selectable to be either 33.33 or 66.66MHz at 3.3V. PCI clock outputs, selectable to be either 33.33 or 66.66MHz at 3.3V. PCI clock outputs, selectable to be either 33.33 or 66.66MHz at 3.3V. PCI clock outputs, selectable to be either 33.33 or 66.66MHz at 3.3V. Enables Spread Spectrum, default...

7134SA25J

7135 TI

Vendor:TIPackage Cooled:DIPD/C:06+

7135 TI

Vendor:TIPackage Cooled:DIPD/C:06+

7135216350

7135216351

7135CP1

Vendor:HARRISD/C:08+

7-1393215-5

7139A

713R950

Vendor:ADD/C:199

Two independent LVDS receiver serial ports for optional 1:1 protection Main and redundant LVDS transmit ports Loop timing capability enables LVDS recovered clock to internally drive LVDS transmit clock Internal buffers allow maximum LVDS serial bit rate independent of UTOPIA clock rate Programmable UTOPIA interface UTOPIA Level 2 up to 52 MHz ATM layer or PHY layer interface ATM layer in...

713R950

Vendor:ADD/C:199

Two independent LVDS receiver serial ports for optional 1:1 protection Main and redundant LVDS transmit ports Loop timing capability enables LVDS recovered clock to internally drive LVDS transmit clock Internal buffers allow maximum LVDS serial bit rate independent of UTOPIA clock rate Programmable UTOPIA interface UTOPIA Level 2 up to 52 MHz ATM layer or PHY layer interface ATM layer in...

71408.050.0000

71408.060.0000

71408.08

7140SA25J

AUXILIARY VIDEO MUTE All auxiliary video outputs can be simultaneously disabled by programming Bits 3-5 in Register 1. The power-up default condition is xx111xxx, which sets all auxiliary video outputs to 0 VDC and switches the auxiliary audio outputs to Lin/Rin.

7140SA45J

ELECTRICAL CHARACTERISTICS The block diagram is given in Figure 1. The values of the different networks used in this datasheet are defined as followed : - The return loss is adjusted by R10 of 600Ω. - The transmit adjust gain network R8 is calculated in order to have a gain of 46dB typical with ILS = 22mA. - The sidetone network ZST is set to be lower than 20dB (Vear/Vmic) on a 600Ω load on l...

7140SA55J

Vendor:IDTPackage Cooled:PLCCD/C:01+

7141106

− 0 V to 2.5 V High Speed Parallel Interface 78 dB SNR and 88.5 dB THD at 3 MSPS Power Dissipation 85 mW at 3 MSPS Nap Mode (10 mW Power Dissipation) Power Down (10 mW) Internal Reference Internal Reference Buffer 8-/14-Bit Bus Transfer 48-Pin TQFP Package

7141L3CJN

Vendor:INTERSILPackage Cooled:金DIPD/C:N/A

Figure 1 shows a typical application circuit. The regulator is enabled any time the shutdown input is at or above VIH. And shutdown (disabled) when SHDN is at or below VIL. SHDN maybe controlled by a CMOS logic gate, or I/O port of a micro controller. If the SHDN input is not. Required, it should be connected directly to the supply. While in shutdown, supply current decreases to 0.05µA (typi...

71421

Vendor:IDTPackage Cooled:PLCC52D/C:2007+

(25-MHzC165-MHz Pixel Rates) Universal Graphics Controller Interface C 12-Bit, Dual-Edge and 24-Bit, Single-Edge Input Modes C Adjustable 1.1-V to 1.8-V and Standard 3.3-V CMOS Input Signal Levels C Fully Differential and Single-Ended Input Clocking Modes C Standard Intel 12-Bit Digital Video Port Compatible as on Intel 81x Chipsets Enhanced PLL Noise Immunity C On-Chip Regulators and Bypas...

71421-SA25J

Vendor:IDTPackage Cooled:PLCC52D/C:01+

71421SA55J

Vendor:IDTPackage Cooled:PLCC-52D/C:1999

The fixed 2.5-V output controller uses an internal temperature-compensated bandgap reference centered at 1.2 V. Its tolerance is designed to be <2% over the specified temperature range, which, when coupled with the low offset of the driver circuit, allows the 2.5-V output to have a tolerance of 2% over the specified temperature range and full load.

71421SA55J

Vendor:IDTPackage Cooled:PLCC-52D/C:1999

The fixed 2.5-V output controller uses an internal temperature-compensated bandgap reference centered at 1.2 V. Its tolerance is designed to be <2% over the specified temperature range, which, when coupled with the low offset of the driver circuit, allows the 2.5-V output to have a tolerance of 2% over the specified temperature range and full load.

7142LA35J

71430-0004

Vendor:MolexD/C:08+

IV Conclusions A silicon bipolar low power LNA for 1.9GHz has been designed and tested. It shows a noise figure of 2.3dB along with a 15dB gain. The power consumption is only 5.2mW resulting in a high gain/DC-power figure of merit of 2.9dB/mW. The design was done on a transistor array showing almost no performance degradation relative to full custom design.

7143138-006

71436-0164

Vendor:MOLEXD/C:07+

(8-2) Input Timing Digital audio signal data into DIN terminal is fetched into the internal shift register by BCK signal rising edge. The fetched data in the shift register are transferred by rising edge or falling edge of LRCK as shown below:

71436-0464

714361164

Vendor:MolexPackage Cooled:N/AD/C:4

Power Back-up pin(+). . At Li Mode, connect a 0.1u capacitor to GND. LCD supply voltage and positive supply pins. . In Ag power mode, connect positive power to VDD1. . In Li or ExtV power mode, connect positive power to VDD2. Input pin for external reset request signal, built-in internal pull-down resistor. . Reset cycle time can be defined as PH15/2 or PH12/2 by mask option. . Reset Type can be defined as ...

71436-1464

Vendor:MOLEXD/C:07+

The HMJ1 is a high dynamic range, GaAs FET mixer. This active FET realizes a typi- cal third order intercept point of +39 dBm at an LO drive level of +17 dBm. The HMJ1 comes in a low cost, J-lead package. Typical applications include frequency up/down conversion, modulation and demodulation for receivers and transmitters used in cellular communications systems.

71436-1464

Vendor:MOLEXD/C:07+

The HMJ1 is a high dynamic range, GaAs FET mixer. This active FET realizes a typi- cal third order intercept point of +39 dBm at an LO drive level of +17 dBm. The HMJ1 comes in a low cost, J-lead package. Typical applications include frequency up/down conversion, modulation and demodulation for receivers and transmitters used in cellular communications systems.

71436-2164

Vendor:MOLEXD/C:07+

This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.04 / Jun.01Hynix Semiconductor

71436-2464

Vendor:MolexD/C:08+

The second contributor to the constantly varying pixel offsets is the fact that, at high pixel rates, the floating capacitor never has time to fully discharge (charge) during the period in which its shunt switch is closed. There is always some "residual" charge left on the cap, and the amount of this charge varies as a function of what was the total charge held during the previous pixel. This...

71436-2864

Vendor:MolexD/C:08+

Transmit and Receive frames and time-slots may be skewed from each other by any number of BCLK cycles. During each assigned Transmit time-slot, the selected DX0/1 output shifts data out from the PCM register on the rising edges of BCLK. TSX0 (or TSX1 as appropriate) also pulls low for the first 71⁄2 bit times of the time-slot to control the TRI-STATE Enable of a backplane line-driver. Serial PCM ...

7-1437012-0

71439-0164

Vendor:MOLEXD/C:07+

The Am29DL320G is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ15CDQ0; byte mode data appears on DQ7CDQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers.

71439-0864

Vendor:MolexD/C:08+

These 10-bit bus-interface latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

71439-1464

Vendor:MOLEXD/C:N/A

Note: 1. Enhancement mode technology employs a single positive Vgs, eliminating the need of negative gate voltage associated with conventional depletion mode devices. 2. Refer to reliability datasheet for detailed MTTF data. 3. Conforms to JEDEC reference outline MO229 for DRP-N

71439-1464

Vendor:MOLEXD/C:N/A

Note: 1. Enhancement mode technology employs a single positive Vgs, eliminating the need of negative gate voltage associated with conventional depletion mode devices. 2. Refer to reliability datasheet for detailed MTTF data. 3. Conforms to JEDEC reference outline MO229 for DRP-N

71439-1864

Vendor:MolexD/C:08+

71439-2164

Vendor:MOLEXD/C:07+

Write Enable (WEN) When VCC is applied to the part it powers up in the Write Disable (WDS) state Therefore all programming modes must be preceded by a Write Enable (WEN) instruction Once a Write Enable instruction is executed programming remains enabled until a Write Disable (WDS) instruction is executed or VCC is completely removed from the part

71439-3164

Vendor:MOLEXD/C:07+

The 71439-3164F and 71439-3164S are sound processor ICs that perform phase and harmonic compensation on audio signals to accurately reproduce the rise section of audio signals that determines the characteristics of the sound, and thus reproduce the original recording as naturally as possible.

71439-3164

Vendor:MOLEXD/C:07+

The 71439-3164F and 71439-3164S are sound processor ICs that perform phase and harmonic compensation on audio signals to accurately reproduce the rise section of audio signals that determines the characteristics of the sound, and thus reproduce the original recording as naturally as possible.

7143SA55J

Vendor:IDTPackage Cooled:PLCC68D/C:2007+

7144069-000

71449-02

D/C:DIP

RXCLK is the clock output bit clock. This clock is used to transfer Header information and data through the RXD serial bus to the network processor. This clock reflects the bit rate in use.RXCLK will be held to a logic 0 state during the acquisition process. RXCLK becomes active when the HSP3824 enters in the data mode. This occurs once bit sync is declared and a valid signal quality estimate is made...

7146AH

Vendor:PHILIPSPackage Cooled:PQFP152

7146L15Y

Vendor:IDTPackage Cooled:SOJ-7.2-28PD/C:07+

The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can tra...

7146S20Y

Vendor:IDTPackage Cooled:SOJ-7.2-28PD/C:07+

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All ...

7147A450QIL8QS

Vendor:100Package Cooled:INTELD/C:01+

This low failure rate represents data collected from Maxims reliability monitor program. I addition ton routine production Burn-In, Maxim pulls a sample from every fabrication process three times per week and subjects it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be shipped as standard product is 59 F.I.T. at a 60% confidence level, which...

714-87-108-41-001101

7148Q

Vendor:TID/C:01+

The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2) or midscale (AD5620-3 and AD5660-3) and remains there until a valid write takes place. The parts contain a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The power consumpt...

7148Q

Vendor:TID/C:01+

The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2) or midscale (AD5620-3 and AD5660-3) and remains there until a valid write takes place. The parts contain a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The power consumpt...

715-000914-000

Vendor:MCDATAPackage Cooled:PBGAD/C:04+

715-0111-01B

FC-AL Features In addition to the high-perfor- mance architecture, Tachyon TS builds on the Tachyon TL with Public Loop, multiple I/Os in the same loop arbitration cycle, Loop Map, Loop Broadcast, and Loop Directed Reset while offering 66 MHz PCI connectivity. These features allow the designer to achieve higher performance in an arbitrated loop topology.

71502L25J

Choice of Open-Collector or Active Pullup (Totem-Pole) Outputs Single 5-V Supply Differential Line Operation Dual-Channel Operation TTL Compatible 15-V Common-Mode Input Voltage Range Optional-Use Built-In 130-Ω Line- Terminating Resistor Individual Frequency-Response Controls Individual Channel Strobes Designed for Use With SN55113, SN75113, SN55114, and SN75114 Drivers Designed to Be Intercha...

71506.05

71506.08

71506.25

715-0720-002

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.

7150MLF

Vendor:NULLPackage Cooled:SOP-8D/C:07+

7150Q

Vendor:TIPackage Cooled:01+D/C:SOP-8

DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

7150Q

Vendor:TIPackage Cooled:01+D/C:SOP-8

DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

715-1-1/10W-0603

7151M150L

Vendor:ICSPackage Cooled:SOP-3.9-8PD/C:6+

4mA and sink 8mA in 3.3V mode. The output drivers have a separate VCCIO reference input which is inde- pendent of the main VCC supply for the device. This feature allows the output drivers to drive either 3.3V or 2.5V output levels while the device logic and the output current drive is always powered from 3.3V. The output drivers also provide individually programmable edge rates and open drain capabi...

7152A

7153-12411

71550

D/C:92

For best results, an Xtal oscillator design should drive the clock inverter input with signal levels of at least 40% of VDD peak-to-peak. Tuning-fork Xtals generally cannot meet this requirement. To obtain Xtal oscillator design assistance, please consult your Xtal manufacturer.

7156CS

Vendor:ELPackage Cooled:SOP-8

Like all of the UltraLogic™ FLASH370i devices, the CY7C375i is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins. The ISR interface is enabled using the programming voltage pin (ISREN). Additi...

7156CS

Vendor:ELPackage Cooled:SOP-8

Like all of the UltraLogic™ FLASH370i devices, the CY7C375i is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins. The ISR interface is enabled using the programming voltage pin (ISREN). Additi...

7157-1573

Vendor:0Package Cooled:07＋D/C:281

7157-3596-30

Vendor:0Package Cooled:07＋D/C:430

7157-6327-70

Vendor:0Package Cooled:07＋D/C:800

7157-6367-70

Vendor:0Package Cooled:07＋D/C:606

7157-6407-70

Vendor:0Package Cooled:07＋D/C:800

7157-6410-40

Vendor:0Package Cooled:07＋D/C:200

7157-6520-80

Vendor:0Package Cooled:07＋D/C:271

7157-6560-40

Vendor:0Package Cooled:07＋D/C:244