74LCX16245MT

Vendor:FAIPackage Cooled:TSSOPD/C:00+

250-kHz Sampling Rate 4-V, 5-V, 10 V, 3.33-V, 5-V, and 10-V Input Ranges 2.0 LSB Max INL 1 LSB Max DNL, 16-Bit No Missing Codes SPI Compatible Serial Output with Daisy-Chain (TAG) Feature Single 5-V Supply Pin-Compatible With ADS7809 (Low Speed) and 12-Bit ADS8508/7808 Uses Internal or External Reference 70-mW Typ Power Dissipation at 250 KSPS 20-Pin SO and 28-Pin SSOP Packages Simple DSP Interface

74LCX16245MTCX

Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

74LCX16245MTD_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

74LCX16245TTR

Vendor:STPackage Cooled:10350D/C:07+

The UCC1800/1/2/3/4/5 family offers a variety of package options, tem- perature range options, choice of maximum duty cycle, and choice of critical voltage levels. Lower reference parts such as the UCC1803 and UCC1805 fit best into battery operated systems, while the higher refer- ence and the higher UVLO hysteresis of the UCC1802 and UCC1804 make these ideal choices for use in off-line power supplies.

74LCX16245TTR

Vendor:STPackage Cooled:10350D/C:07+

The UCC1800/1/2/3/4/5 family offers a variety of package options, tem- perature range options, choice of maximum duty cycle, and choice of critical voltage levels. Lower reference parts such as the UCC1803 and UCC1805 fit best into battery operated systems, while the higher refer- ence and the higher UVLO hysteresis of the UCC1802 and UCC1804 make these ideal choices for use in off-line power supplies.

74LCX163245

74LCX16373

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments.

74LCX16373DTR2

Vendor:ONPackage Cooled:TSSOPD/C:2000

The MAX3060E features slew-rate-limited drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 115kbps. The MAX3061E, also slew- rate limited, transmits up to 500kbps. The MAX3062E driver is not slew-rate limited, allowing transmit speeds up to 20Mbps. All transmitter outputs are protected to 15kV using the Human Body Model.

74LCX16373MDTX

Vendor:FAIPackage Cooled:SSOP

(*) Typical temperature coefficient for all VDD value is 0.3 %/C. (1) Input tr, tf = 5ns (2) If more than unit is cascaded in a parallel clocked application, tr should be made less than or equal to the sum of the fixed propagation delay time at 15pF and the transition time of the carry output driving stage for the estimated capacitive load.

74LCX16373MEA

Hynix HYMD512G726(L)4M-K/H/L series is Low Profile registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix HYMD512G726(L)4M-K/H/L series consists of eighteen 128Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD512G726(L)4M-K/H/L series provide a high performance 8-byte interfac...

74LCX16373MEAX

Vendor:FAIRCHILDPackage Cooled:SSOP48D/C:07+

Port 1 is an 8 bit bi-directional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pullups.

74LCX16373MTD

Vendor:FSCPackage Cooled:TSSOPD/C:09+

DESCRIPTION Input. Decoded by LAN91C100FD to determine access to its registers. Input. Used by LAN91C100FD for internal register selection. Input. Used as an address qualifier. Address decoding is only enabled when AEN is low. Input.Used during LAN91C100FD register accesses to determine the width of the access and the register(s) being accessed. nBE0-nBE3 are ignored when nDATACS is low (burst accesses)...

74LCX16373MTDX

Vendor:FAIRCHILDPackage Cooled:TSSOP48D/C:07+

The on-board Flash program memory is accessible through the ISP serial interface. Holding RST active forces the device into a serial programming interface and allows the program mem- ory to be written to or read from, unless one or more lock bits have been activated.

74LCX16373MTDX /LCX16373

Vendor:FAIPackage Cooled:TSSOPD/C:03+

74LCX16373MTDX_NL

Vendor:TSSOPPackage Cooled:FAIRCHILDD/C:0530+

74LCX16374

• Floating Channel Designed For Bootstrapping Operation To +600V • Typically 90mA/180mA Sourcing/Sinking Current Driving Capability For Both Channels • Common-Mode dv/dt Noise Canceling Circuit • Extended Allowable Negative VS Swing To -9.8V For Signal Propagation @ VCC=VBS=15V • VCC & VBS Supply Range From 10V To 20V • UVLO Functions For Both Channels ̶...

74LCX16374 /LCX16374

Vendor:FAIPackage Cooled:SSOPD/C:01+

74LCX16374A

Package Cooled:SSOP48D/C:00+

The Preliminary designation indicates that the product development has progressed such that a com- mitment to production has taken place. This designation covers several aspects of the product life cy- cle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifi- cations presen...

74LCX16374A /LCX16374A

Vendor:TOSPackage Cooled:0317+D/C:TSSOP

74LCX16374AFT

Vendor:TOS

Write all (WRAL) The Write All (WRAL) instruction programs all registers with the data pattern specified in the instruction. While the WRAL instruction is being loaded, the address field becomes a sequence of DON'T-CARE bits. (Shown in Figure 7) As with the WRITE instruction, if CS is brought HIGH after a minimum wait of 250ns (tcs), the DO pin indicates the READY/BUSY status of the chip. (shown in figure 7)

74LCX16374D

74LCX16374DTR

Vendor:ONPackage Cooled:TSSOP-48D/C:03

Clock with 1/2 frequency of XTL1 Test pin Chip reset negative logic signal Test pin Test pin Test pin Ground pin CPU register read strobe negative logic signal CPU register write strobe negative logic signal Chip select negative logic signal from CPU Interrupt request signal to CPU CPU address signal CPU data bus (MSB) CPU data bus CPU data bus Ground pin Power supply pin

74LCX16374MEA

Note: 1) The input voltage range 19...36 V meets the requirements for Normal input voltage range in 24 V DC power systems, 2030 V. At input voltages exceeding 36 V (abnormal voltage) the power loss will be higher than at normal input voltage and TC must be limited to max +90 C. Absolute max continuous input voltage is 40 V dc. Output characteris- tics will be marginally affected at 18 V (see also Turn-off...

74LCX16374TTR

Vendor:STPackage Cooled:TSOP-7.2-48D/C:6+

The 3D7205 5-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 8.0ns through 100ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7205 is TTL- and CMOS- co...

74LCX16374TTR

Vendor:STPackage Cooled:TSOP-7.2-48D/C:6+

The 3D7205 5-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 8.0ns through 100ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7205 is TTL- and CMOS- co...

74LCX16374TTRS2

74LCX16500

D/C:96

Propagation delay is affected by the number of outputs switching simultaneously. Typically, devices with more than one output will follow the rule: for each output switching, derate the databook specification by 250 ps. This effect typically is not significant on an octal device unless more than four outputs are switching simultaneously. This derating is valid for the entire temperature range and 5.0 V 10% ...

74LCX16500MEAX

Vendor:NSCPackage Cooled:TSSOPD/C:98+

This family is a 16M bit dynamic RAM organized 1,048,576 x 16-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70 or 80ns) and refresh cycle(1K ref. or 4K ref.) and power cons...

74LCX16500MEAX

Vendor:NSCPackage Cooled:TSSOPD/C:98+

This family is a 16M bit dynamic RAM organized 1,048,576 x 16-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70 or 80ns) and refresh cycle(1K ref. or 4K ref.) and power cons...

74LCX16500MTD

Vendor:Fairchild

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.03 / Jun.98©1998 Hyundai Semiconductor

74LCX16500MTD

Vendor:Fairchild

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.03 / Jun.98©1998 Hyundai Semiconductor

74LCX16501

Vendor:FAIRCHILDPackage Cooled:SMDD/C:05+

1.1 Scope. This specification covers the performance requirements for NPN, silicon, low-power transistors. Four levels of product assurance are provided for each device type as specified in MIL-PRF-19500. Two levels of product assurance are provided for the unencapsulated device type 2N3700.

74LCX16501 /LCX16501

Vendor:FAIPackage Cooled:SSOPD/C:04+

74LCX16501MEA

A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit eliminates the prop delay that would be added by the STA111 LSPN logic between TDIn and TDO(n+1) or TDOB by buffering and synchronizing the LSP TDI inputs to the falling edge of TCKB, thus allowing data to be scanned at higher frequencies without violating set-up and hold times.

74LCX16501MEAX

Vendor:FSCPackage Cooled:SSOP7.2D/C:06+

The FM811 has an active low RESET output, while the FM812 offers an active high RESET output. The reset output is guaranteed to remain asserted for a minimum of 140ms after VCC has risen above the designated reset threshold. The FM811/FM812 is available in a 4-pin SOT-143.

74LCX16501MTD

Vendor:NSPackage Cooled:.D/C:2008+

The improvements in the DG411/883 series are made possi- ble by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits con- trolling 40VP-P signals. Power supplies may be single-ended from +5V to +34V, or split from 5V to 20V.

74LCX16501MTDX

Vendor:FSCPackage Cooled:TSSOPD/C:08+

The HCPL-7850/7851 is an isolation amplifier that provides accurate, electrically isolated and amplified representations of voltage and current. When used with a shunt resistor to monitor the motor phase current in a high speed motor drive, the device will offer superior reliability compared with the traditional solutions such as current transformers and Hall-effect sensors. The HCPL-7850/7...

74LCX16543

Vendor:FAIPackage Cooled:TSSOP-56D/C:00+

The operating system can theoretically shut down an RS-232 port if, after a suitable delay, it sees no incoming data transitions or status-line changes. But the choice of delay period presents a problem-you can miss data if you happen to power down just as a data burst begins, and you'll probably miss some of the data that wakes up the system and initiates power-up. For these reasons, designers seldom go...

74LCX16543MEA

PARAMETER Collector-emitter voltage peak value Collector-emitter voltage (open base) Collector current (DC) Collector current peak value Base current (DC) Base current peak value Total power dissipation Storage temperature Junction temperature

74LCX16543MTD

Vendor:600

FEATURES 40 MSPS Correlated Double Sampler (CDS) 4 dB 6 dB Variable CDS Gain with 6-Bit Resolution 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Analog Preblanking Function 10-Bit 40 MSPS A/D Converter Auxiliary Inputs with VGA and Input Clamp 3-Wire Serial Digital Interface 3 V Single Supply Operation Low Power: 155 mW @ 3.0 V Supply 48-Lead LQFP Package

74LCX16543MTD

Vendor:600

FEATURES 40 MSPS Correlated Double Sampler (CDS) 4 dB 6 dB Variable CDS Gain with 6-Bit Resolution 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Analog Preblanking Function 10-Bit 40 MSPS A/D Converter Auxiliary Inputs with VGA and Input Clamp 3-Wire Serial Digital Interface 3 V Single Supply Operation Low Power: 155 mW @ 3.0 V Supply 48-Lead LQFP Package

74LCX16543MTDX

Vendor:FSCPackage Cooled:TSSOPD/C:08+

NOTE: 1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.

74LCX16543MTDX_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

74LCX16646M

The TLE 4471 is a monolithic integrated very low-drop triple voltage regulator. The main output supplies loads up to 450 mA and the additional tracked outputs can provide up to 50 mA and 100 mA. In addition the device includes a watchdog for microcontroller-supervision, an under-voltage reset, a power on reset and extended enabling features. The watchdog and reset timing can be chosen independently of each...

74LCX16646MEA

Industry Standard Surface Mount Packages Low Capacitance Diodes Low Resistance Diodes Low Loss Switch Diodes High Isolation Switch Diodes Low Distortion Attenuator Diodes Fast Switching Diodes Single and Dual Diode Configurations Tape and Reel Packaging

74LCX16646MEAX

Vendor:FAIRCHILDPackage Cooled:SSOP56D/C:07+

REF is 5V tolerant 4 pairs of programmable skew outputs Low skew: 200ps same pair, 250ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Output frequency: 3.75MHz to 85MHz 2x, 4x, 1/2, and 1/4 outputs 3 skew grades: IDT5V991A-2: tSKEW0<250ps IDT5V991A-5: tSKEW0<500ps IDT5V991A-7: tSKEW0<750ps 3-level inputs for skew and ...

74LCX16646MEAX

Vendor:FAIRCHILDPackage Cooled:SSOP56D/C:07+

REF is 5V tolerant 4 pairs of programmable skew outputs Low skew: 200ps same pair, 250ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Output frequency: 3.75MHz to 85MHz 2x, 4x, 1/2, and 1/4 outputs 3 skew grades: IDT5V991A-2: tSKEW0<250ps IDT5V991A-5: tSKEW0<500ps IDT5V991A-7: tSKEW0<750ps 3-level inputs for skew and ...

74LCX16646MTD

Vendor:FSCPackage Cooled:TSSOPD/C:05+

The ACE1501 product family has an 8-bit microcontroller core, 64 bytes of RAM, 64 bytes of data EEPROM and 1K bytes of code EEPROM. Its on-chip peripherals include a multifunction 16-bit timer, a watchdog/idle timer, and programmable under- voltage detection circuitry. On-chip clock and reset functions reduce the number of required external components. The ACE1501 product family is available in 8- and ...

74LCX16646MTDX

Vendor:FAIRCHILDPackage Cooled:TSS0PD/C:07+

Highest sustained bandwidth per DRAM device - 1.6GB/s sustained data transfer rate - Separate control and data buses for maximized efficiency - Separate row and column control buses for easy scheduling and highest performance - 16 banks: four transactions can take place simul- taneously at full bandwidth data rates

74LCX16652MEA

Vendor:ＦＡＩＲＣＨＩＬＤ

prevent output pulses when power is turned on. An unused RESET input should be tied to VDD. How- ever, if an entire section of the HCC/HCF4538B is not used, its inputs must be tied to either VDD or VSS (see table 1). In normal operation the circuit triggers (extends the output pulse one period) on the appli- cation of each new trigger pulse. For operation in the non-retriggerable mode, Q is connected...

74LCX16652MEAX

Vendor:FAIRCHILDPackage Cooled:SSOP56D/C:07+

The 32-bit multiplexed bus interface unit of MX98715A provides a direct interface to a PCI local bus, simplifing the design of an Ethernet adapter in a PC system. With its on-chip support for both little and big endian byte alignment, MX98715A can also address non-PC appli- cations.

74LCX16821

Vendor:FAID/C:06+

This device contains an integrated charge pump and level shifter (for gate drive voltages), integrated shoot-through current protection (cross-conduction suppression logic and timing), and undervoltage detection and shutdown circuitry.

74LCX16821MEA

properties. Used for insulation and protection of cables, harnesses, and electrical and electronic components in enclosed spaces, such as in marine applications, mass transit systems, and offshore installations, to reduce toxicity risks, or where equipment would be irreparably damaged by corrosive products of combustion.

74LCX16821MTD

AMBE-2000™ Vocoder Chip is a registered trademark of Digital Voice Systems, Inc. Other product names mentioned may be trademarks or registered trademarks of their respective companies and are the sole property of their respective manufacturers. All Rights Reserved Data subject to change

74LCX16821MTDX

Vendor:FAIRCHILDPackage Cooled:TSS0PD/C:07+

SOT-323 PCB Footprint A recommended PCB pad layout for the miniature SOT-323 (SC-70) package is shown in Figure 11 (dimensions are in inches). This layout provides ample allowance for package placement by auto- mated assembly equipment without adding parasitics that could impair the performance.

74LCX16839

Package Cooled:2005D/C:TSSOP

Edition Jun. 2002 This edition was realized using the software system FrameMakerâ. Published by Infineon Technologies, Marketing-Kommunikation, Balanstraße 73, 81541 Mnchen © Infineon Technologies 6/30/2002. All Rights Reserved.

74LCX16841

D/C:96

Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial pre...

74LCX16841 /LCX16841

Vendor:FAIPackage Cooled:SSOPD/C:98+

74LCX16841MEA

VBIAS (VCC , VBS1,2,3) = 15V, VS0,1,2,3 = VSS and TA = 25C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3 . The VO and IO parameters are referenced to VS0,1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.

74LCX16841MTD

These N-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switching DC/DC converte...

74LCX2244MSA

This circuit consists of two independent, high gain, internally frequency compensated which were designed specifically for automotive and industrial control system. It operates from a single power supply over a wide range of voltages. The low power supply drain is independent of the magnitude of the power supply voltage.

74LCX2244MTC

Vendor:FAIRCHILDD/C:05+

A: The value of R JA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25C. The value in any a given application depends on the user's specific board design. The current rating is based on the t 10s thermal resistance rating. B: Repetitive rating, pulse width limited by junction temperature. C. The R JA is the sum of the thermal impedence from junc...

74LCX2244WM

Vendor:FAIRCHILPackage Cooled:SOP20D/C:2003+

The DS1270 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 21 address inputs (A0CA20) defines which of the 2,097,152 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing...

74LCX2244WMX

Vendor:FSCPackage Cooled:SOP20D/C:0825

NOTES: (1) Does not include errors from external gain setting resistors (2) Output voltage swings are measured between the output and power-supply rails. Output swings to rail only if G 10. Output does not swing to positive rail if gain is less than 10. (3) See typical characteristic Percent Overshoot vs Load Capacitance. (4) See typical characteristic Shutdown Voltage vs Supply Voltage.

74LCX2244WMX

Vendor:FSCPackage Cooled:SOP20D/C:0825

NOTES: (1) Does not include errors from external gain setting resistors (2) Output voltage swings are measured between the output and power-supply rails. Output swings to rail only if G 10. Output does not swing to positive rail if gain is less than 10. (3) See typical characteristic Percent Overshoot vs Load Capacitance. (4) See typical characteristic Shutdown Voltage vs Supply Voltage.

74LCX240CQ

Bay Linear products are not authorized for and should not be used within life support systems which are intended for surgical implants into the body to support or sustain life, in aircraft, space equipment, submarine, or nuclear facility applications without the specific written consent of Bay Linear President.

74LCX240M

Vendor:FAIRCHILDD/C:06+

74LCX240MSA

Vendor:FAIPackage Cooled:SSOP/20

hold the output low (Figure 2). This resistor value, though not critical, should be chosen such that it does not appreciably load RESET under normal operation (100kW will be suitable for most applications). Similarly, a pullCup resistor to VCC is required for the MAX810 to ensure a valid high RESET for VCC below 1.0V.

74LCX240MSA

Vendor:FAIPackage Cooled:SSOP/20

hold the output low (Figure 2). This resistor value, though not critical, should be chosen such that it does not appreciably load RESET under normal operation (100kW will be suitable for most applications). Similarly, a pullCup resistor to VCC is required for the MAX810 to ensure a valid high RESET for VCC below 1.0V.

74LCX240MTCX /LCX240

Vendor:FAIPackage Cooled:05+D/C:TSSOP

74LCX240MTCX_E4

Vendor:ＦＡＩＲＣＨＩＬＤ

74LCX240MTR

Vendor:STPackage Cooled:SOP-20D/C:99

This performance over temperature is achieved by having both the shear stress strain gauge and the thinCfilm resistor circuitry on the same silicon diaphragm. Each chip is dynam- ically laser trimmed for precise span and offset calibration and temperature compensation.

74LCX240MTR

Vendor:STPackage Cooled:SOP-20D/C:99

This performance over temperature is achieved by having both the shear stress strain gauge and the thinCfilm resistor circuitry on the same silicon diaphragm. Each chip is dynam- ically laser trimmed for precise span and offset calibration and temperature compensation.

74LCX240SJX

Vendor:FAIPackage Cooled:N/AD/C:99+

The logic control inputs can be driven up to +3.6V regardless of the supply voltage. For example, given a 3.0V supply, the control or select pins may be driven low to 0V and high to 3.6V. Driving the control or select pins Rail-toRail minimizes power consumption.

74LCX240WM

As a member of the 51LPC microcontroller family, the 87LPC768 offers an 8-bit ADC with four multiplexed channels and an 8-bit Pulse Width Modulator (PWM.) Further, the device provides 4K of OTP code memory and 128 bytes of data SRAM, making it suitable for high-level programming. The code memory is In-System Programmable (ISP) through a serial interface. Other embedded features that reduce the need for...

74LCX240WMX

Vendor:FAIPackage Cooled:SMDD/C:08+

After a program or erase cycle has been com- pleted, or after assertion of the RESET# pin (which terminates any operation in progress), the device is ready to read data or to accept another com- mand. Reading data out of the device is similar to reading from other Flash or EPROM devices.

74LCX241

Vendor:FAIRCHILDPackage Cooled:SMDD/C:05+

The sensor array is a row-oriented device. Images are read out one row at a time. The High-Order Row Address Register (RAH) and the Low-Order Row Address Register (RAL) must be programmed to select a row to be captured. Writing to RAL initiates a row capture. The capture time is a function of the external clock and the DTR. After the discharge cycle, the outputs of the row elements will be stored in analog sa...

74LCX241MSA

Either 256 refresh cycles or read/write cycles on 212 consecutive row addresses have to be executed within an 8 ms interval to maintain the data in the memory arrays. A refresh cycle is determined by the mode control bits, see Addressing and Mode Control. In the refresh mode, the row and column addresses are ignored. It should be noted that the shift registers are also dynamic storage elements and that th...

74LCX241MTC

The LEDs are packed in cardboard boxes after packaging in anti-electrostatic bags.According to the total delivery amount, cardboard boxes will be used to protect the LEDs from mechanical shocks during transportation.Please refer to figures page.The label on the minimum packing unit bag shows; Part Number, Lot Number, Ranking, Quantity The boxes are not water resistant and therefore must be kept away fr...

74LCX241MTCX

Vendor:FAIRCHILDD/C:O9+

Youre probably having trouble keeping the constant voltage across RA and RB really constant. The pulse output on pin 9 puts a moderate load on both supplies as it switches current on and off. Changes in the supply reflect as variations in charging current, hence non-linearity. Decoupling both power supply pins to ground right at the device pins is a good idea. Also, pins 7 and 8 are susceptible to pick...

74LCX241MTCX

Vendor:FAIRCHILDD/C:O9+

Youre probably having trouble keeping the constant voltage across RA and RB really constant. The pulse output on pin 9 puts a moderate load on both supplies as it switches current on and off. Changes in the supply reflect as variations in charging current, hence non-linearity. Decoupling both power supply pins to ground right at the device pins is a good idea. Also, pins 7 and 8 are susceptible to pick...

74LCX241SJ

Vendor:FAIRCHILDPackage Cooled:00+D/C:300

74LCX241SJ

Vendor:FAIRCHILDPackage Cooled:00+D/C:300

74LCX244DTR2

Vendor:ON

reset (pin 4) An active low input that forces both outputs low, and causes all counter stages to initialize. If unused, it can be left open circuited (due to the internal resistor) or preferrably tied to VDD. Refer to the minimum timing requirements in the Electrical Characteristics section.

74LCX244DWR

Vendor:NSPackage Cooled:SOP

Note 1) The specified condition Tj = 25C means that the test should be carried out within so short a test time (within 10ms) that the characteristic value drift due to the chip junction temperature rise can be ignored. Note 2) Unless otherwise specified, VI = −9V, IO = 40mA, CI = 2µF, CO = 1µF, Tj = 0 to 125C

74LCX244DWR

Vendor:NSPackage Cooled:SOP

Note 1) The specified condition Tj = 25C means that the test should be carried out within so short a test time (within 10ms) that the characteristic value drift due to the chip junction temperature rise can be ignored. Note 2) Unless otherwise specified, VI = −9V, IO = 40mA, CI = 2µF, CO = 1µF, Tj = 0 to 125C

74LCX244FT

Vendor:TOS

MANUAL RESET INPUTMR: Manual Reset input is a debounced input that can be connected to an external source for Manual Reset. Pulling the MR input low will generate a Reset condition. Reset outputs are active while MR input is low and for the reset timeout period after MR returns to high. The input has an internal pull up resistor.

74LCX244FT

Vendor:TOS

MANUAL RESET INPUTMR: Manual Reset input is a debounced input that can be connected to an external source for Manual Reset. Pulling the MR input low will generate a Reset condition. Reset outputs are active while MR input is low and for the reset timeout period after MR returns to high. The input has an internal pull up resistor.

74LCX244MSA_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

74LCX244MTCX

Vendor:FAIRCHILDPackage Cooled:642D/C:532

Description The Integrated Telecom Circuit combines a 1-Form-A solid state relay, bridge rectifier, Darlington transistor and opto- coupler into one 16 pin SOIC package, consolidating designs and reducing component count in telecom appli- cations. The ITC117s optocoupler provides for full wave detection of ring signals.

74LCX244MTCX /LCX244

Vendor:FAIPackage Cooled:TSSOPD/C:05+

74LCX244MTCX_F042

Vendor:ＦＡＩＲＣＨＩＬＤ

74LCX244MTCX_NF042

Vendor:ＦＡＩＲＣＨＩＬＤ

74LCX244MTCX-NL

Notes: 1. VBR measured after IT applied for 300us, IT =square wave pulse or equivalent. 2. Surge current waveform per Figure 3 and derate per Figure 2. 3. For bipolar types having VWM of 10 volts and under, the ID limit is doubled. 4. All terms and symbols are consistent with ANSI/IEEE C62.35.

74LCX244MTR

Vendor:ＳＴ

Analog Reference Voltage input. The voltage at this pin should be in the range of 0.6V to 1.6V. With 1.4V at this pin and the GAIN pin low, the full scale differential inputs are 1.4 VP-P. With 1.4V at this pin and the GAIN pin high, the full scale differential inputs are 2.8 VP-P. This pin should be bypassed with a minimum 1 µF capacitor.

74LCX244SJX(LVC244)

Vendor:NS

If the instruction preceding the REF has a redundancy effect, this effect is cancelled and the referenced instruction is not skipped. If the instruction following the REF has a redundancy effect, the instruction following the REF is skipped.

74LCX244WM_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

74LCX244WMX_NF40

Vendor:ＦＡＩＲＣＨＩＬＤ

74LCX245BQX

Vendor:FAIRCHILDPackage Cooled:QFN20D/C:08+

74LCX245DWR2

Vendor:ONPackage Cooled:SOP7.2D/C:142

ADJ: In the adjustable version, the user programs the output voltage with two external resistors. The resistors should be 0.1% for high accuracy. The output amplifier is configured as a non-inverting-operational amplifier. The resistors should meet the criteria of R3 || R4 < 100 Ω. Connect ADJ to VOUT for an output voltage of 1.2 V. Note that the point at which the feedback network is connected to...