7808AF

† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL-voltage levels rather than 0 V to VCC.

7808CT

Vendor:ONPackage Cooled:T0220D/C:02

• International standard package JEDEC TO-247 AD • High frequency IGBT and anti-parallel FRED in one package • 2nd generation HDMOSTM process • Low VCE(sat) - for minimum on-state conduction losses • MOS Gate turn-on - drive simplicity • Fast Recovery Epitaxial Diode (FRED) - soft recovery with low IRM

7808F

The S-Bus is a four wire, full duplex, time division multiplexed transmission facility which exchanges information at 192 kbit/s rate including two 64 kbit/s PCM voice or data channels, a 16 kbit/s signalling channel and 48 kbit/s for synchronization and overhead. The relative position of these channels with respect to the ST-BUS is shown in Figures 4 and 5.

7808KA

Notes: 5. Distribution data sample size is 500 samples taken from 5 different wafers and 3 different lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 6. Measurements are made on production test board, which represents a trade-off between optimal OIP3, NF and VSWR. Circuit losses have been de-embedded from actual measurements.

7808TI

The 7808TI is a high-speed 16K x 36 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the 7808TI has ...

7809 KA

Vendor:KAPackage Cooled:DIPD/C:05+

7809 ST

Vendor:STPackage Cooled:DIPD/C:05+

78095BGC502

7809A

Vendor:IORPackage Cooled:SOP-8D/C:N/A

NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 W to VCC−2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR...

7809AV

Vendor:IORPackage Cooled:08+D/C:15000

These octal D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

7809F

This is the inverting input of the transmit gain setting op- erational amplifier. Gain setting resistors are usually con- nected from this pin to TG and from this pin to the analog signal source. The common mode range of the TI+ and TIC pins is from 1.2 V to VDD C 1.2 V. This is an FET gate input. The TIC pin also serves as one of the transmit input multi- plexer pins when the TI+ pin is connected to...

781.0666.01A

Vendor:.Package Cooled:2005D/C:500

• 256 Resistor Taps • 2-Wire Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance, 100Ω typical @ 5V • 16 Nonvolatile Data Registers for Each Potentiometer • Nonvolatile Storage of Multiple Wiper Positions • Power On Recall. Loads Saved Wiper Position on Power Up. • Standby Current < 5µA Max • VC...

781.21.1.02

o 17µA Max Supply Current (781.21.1.02A/781.21.1.02A) o 70µV Max Offset Voltage (781.21.1.02A) o Single-Supply Operation: Input Voltage Range Includes Ground Output Swings to Ground While Sinking Current No Pull-Down Resistors Required o Dual Op Amp in 8-Pin DIP/SO Package (781.21.1.02) Quad Op Amp in 14-Pin DIP/SO Package (781.21.1.02) o 250pA Max Input Offset Current (781.21.1.02...

78108FGKA06

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property o...

7810AF

The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C24x23A family can have up to three IO ports that connect to the global digital and analog interconnects, providing access to 4 digital bloc...

7810KA

The 80C152 which is based on the MCS -51 CPU is a highly integrated single-chip 8-bit microcontroller designed for cost-sensitive high-speed serial communications It is well suited for implementing Integrated Services Digital Networks (ISDN) emerging Local Area Networks and user defined serial backplane applica- tions In addition to the multi-protocol communication capability the 80C152 offers traditional mi...

7811PB3

Vendor:HIFNPackage Cooled:685D/C:05+

The UC3844B, UC3845B series are high performance fixed frequency current mode controllers. They are specifically designed for Off−Line and dc−dc converter applications offering the designer a cost−effective solution with minimal external components. These integrated circuits feature an oscillator, a temperature compensated reference, high gain error amplifier, current sensing comparato...

7811PB3/2

7811W

Vendor:IRFPackage Cooled:SOPD/C:02+

The CS8920As Ethernet Media Access Control (MAC) engine is fully compliant with the IEEE 802.3 Ethernet standard (ISO/IEC 8802-3, 1993), and supports full-duplex operation. The full-du- plex mode may be entered by a command from the host, or via auto-negotiation using link-pulse signaling.

7812 KA

Vendor:KAPackage Cooled:DIPD/C:05+

78125KHZ

7812A

Vendor:KIAPackage Cooled:T0220D/C:00

The 80960CA is the second-generation member of the 80960 family of embedded processors. The 80960CA is object code compatible with the 32-bit 80960 Core Architecture while including Special Function Register extensions to control on-chip peripherals and instruction set extensions to shift 64- bit operands and configure on-chip hardware. Multiple 128-bit internal buses, on-chip instruction caching an...

7812A

Vendor:KIAPackage Cooled:T0220D/C:00

The 80960CA is the second-generation member of the 80960 family of embedded processors. The 80960CA is object code compatible with the 32-bit 80960 Core Architecture while including Special Function Register extensions to control on-chip peripherals and instruction set extensions to shift 64- bit operands and configure on-chip hardware. Multiple 128-bit internal buses, on-chip instruction caching an...

7812AF

Collector-to-Emitter Voltage Continuous Collector Current Continuous Collector Current Pulsed Collector Current Clamped Inductive Load Current Gate-to-Emitter Voltage Reverse Voltage Avalanche Energy Maximum Power Dissipation Maximum Power Dissipation Operating Junction and Storage Temperature Range Soldering Temperature, for 10 sec. Mounting torque, 6-32 or M3 screw.

7812BCZ

Vendor:PROPackage Cooled:07+D/C:10000

The CM1450 comprises a family of inductor-capacitor (L-C) based EMI filter arrays with integrated ESD pro- tection in CSP form factor. The CM1450-06 and CM1450-08 are configured in 6 and 8 channel formats respectively. Each EMI filter channel of the CM1450 is implemented as a 5-pole L-C filter where the compo- nent values are 15pF-17nH-15pF-17nF-15pF. The CM1450's roll-off frequency at -10dB attenuat...

7812CT

Vendor:MOTPackage Cooled:07+D/C:800

The bit rate for data transmitted by the chip, either during the ID frame or in response to a command, is determined by the TCLK_GEN bits in the options page. The chip sup- ports multiples of 16 carrier cycles per bit in the range of 16 to 1024 cycles/bit. All transmission options are amplitude modulated, using a resistive load across the coil.

7812NS

7812TI

A common ground is required between the input and the output voltages. The input voltage must remain typically 2.0V above the output voltage even during the low point on the Input ripple voltage. XX = these two digits of the type number indicate voltage. * = Cin is required if regulator is located an appreciable distance from power supply filter. ** = Co is not needed for stability; however, it does impr...

7814-0006 PR

7814009

Vendor:0Package Cooled:07＋D/C:853

7814J-1-051E

Vendor:BOURNSPackage Cooled:5X5D/C:05+

Power Factor World Wide Line Operation Over-Voltage Protection Accurate Power Limiting Average Current Mode Control Improved Noise Immunity Improved Feed-Forward Line Regulation Leading Edge Modulation 150-µA Typical Start-Up Current Low-Power BiCMOS Operation 10.8-V to 17-V Operation Programmable Output Voltage (Tracking Boost Topology)

7815 ST

Vendor:STPackage Cooled:DIPD/C:05+

7815 TI

Vendor:TIPackage Cooled:DIPD/C:05+

7815A

Low power dc-to-dc regulator designers must consider both the on-resistance of the switches and the gate charge required to turn them on and off. Conventional MOSFETs need more gate charge per ampere of current rating, while Vishay Siliconixs extremely low gate charge, PWM optimized MOSFET technology offers optimum performance even above 1-MHz switching frequencies. The Si9167 has 180-mW internal driv...

7815AF

Vendor:600

An electrical circuit model is shown in Figure 1-4. The coupling capacitance between X and Y electrodes is represented by Cx. While the reset switch is open, a sampling switch is gated so that it transfers charge flows only from the rising edge of X into the sample capacitor Cs. Cs is a large value capacitor, typically in the range of 1 - 50nF. The voltage rise captured on Cs after each X edge is quite...

7815AF

Vendor:600

An electrical circuit model is shown in Figure 1-4. The coupling capacitance between X and Y electrodes is represented by Cx. While the reset switch is open, a sampling switch is gated so that it transfers charge flows only from the rising edge of X into the sample capacitor Cs. Cs is a large value capacitor, typically in the range of 1 - 50nF. The voltage rise captured on Cs after each X edge is quite...

7815AIH

Vendor:SGD/C:01+

7815CT

Vendor:MOTOROLAPackage Cooled:669D/C:07+

VB: Supplies power to all circuits of the regulator except the collector of the output-power transistor. The 2-V headroom from VB to VOUT allows the use of a Darlington output stage for inherently-low-output impedance and fast response. (Dropout is derated for junction temperatures below 0C.)

7815K

Vendor:SNPackage Cooled:04+D/C:DIP

The MC145532 allows for the encoding and decoding of data at one of four rates on a sampleCbyCsample basis. Each data sample that is provided to the part is accompanied by an indication of the rate at which it is to be encoded or decoded. The width of the enable pulse determines the encoding/decoding rate chosen for each sample. The 64 kbps rate allows for PCM data to be passed directly through the ...

7815K/883B

7815KA

Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ...

781642BGC-114

Vendor:NECPackage Cooled:2694D/C:07+

The device is organized as an 8-bit switch bank with dual output enable inputs (OE and OE). When OE is LOW or OE is HIGH, the switch is ON and Port A is connected to Port B. When OE is HIGH and OE is LOW, the switch is OPEN and a high-impedance state exists between the two ports.

78171-40112

Vendor:TECH INC

7817UC

7818AF

The output signals of the SDA 9188-3X are analog. Either RGB or Y, U, V signals can be output, whereby a 6-bit broadband conversion is obtained for all components. Clamping for RGB output signal is performed in an RGB processor (e.g. TDA 4685).

7818C

Vendor:ANKPackage Cooled:TO-220D/C:9503

The SOA curves combine the effect of these limits. For a given application, the direction and magnitude of the output current should be calculated or measured and checked against the SOA curves. This is simple for resistive loads but more complex for reactive and EMF generating loads. However, the following guidelines may save extensive analytical efforts.

78201386

Vendor:N/APackage Cooled:06+D/C:500

782025SM

Vendor:NULL Package Cooled:MODULED/C:07+

Guaranteed by design but not tested. Typical parameters are representative of actual device performance but are for reference only. Industrial grade and "E" suffix devices shall be tested to subgroups 1 and 4 unless otherwise specified. Military grade devices ("H" Suffix) shall be 100% tested to Subgroups 1, 2, 3 and 4. Subgroups 5 and 6 testing available upon request. Subgroup 1, 4 TA...

78205AC

78207108

78207120

The 78P7200 is a line interface transceiver IC intended for STS-1 (51.84 Mbit/s), DS3 (44.736 Mbit/s) and E3 (34.368 Mbit/s) applications. The receiver has a very wide dynamic range and is designed to accept either HDB3 or B3ZS-encoded Alternate-Mark Inversion (AMI) inputs; it provides CMOS logic level clock, positive data, negative data and low-level signal detector outputs. An on-chip equalizer improves t...

78208-103

Vendor:FCIPackage Cooled:3,000

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

78208-106

Vendor:FCI

Hynix HYMD18M645A(L)6-K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 8Mx64 high-speed memory arrays. Hynix HYMD18M645A(L)6-K/H/L series consists of four 8Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin glass- epoxy substrate. Hynix HYMD18M645A(L)6-K/H/L series provide a high performance 8-byte interface in...

7821 KA

Vendor:KAPackage Cooled:DIPD/C:05+

7821120B-09

Vendor:NULL Package Cooled:MODULED/C:07+

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

78213GC

78214G(A)B17

Vendor:NECPackage Cooled:654D/C:05+

7821-5613REV1.4

Vendor:STPackage Cooled:TQFP

These devices are adjustable high-precision shunt regulators whose output voltage (VKA) can be set arbitrarily using two external resistors. These devices have a precise internal reference voltage of 1.26 V, enabling them to operate at low voltage. These devices are ideal for use as error amplifiers in 3-V switching-regulator systems. In addition, they can be used as zener diodes to perform temperature ...

7822U

Vendor:20D/C:SMD8

all eight channels of 7822U. The device also provides 7 signaling pins to SLIC on per channel basis. The 7822U provides 2 programming interfaces: Microprocessor Interface (MPI) and General Control Interface (GCI), which is also known as ISDN Oriented Module (IOM ®-2). For both MPI and GCI programming, the device supports both compressed and linear data format. The device also offers strong test c...

7824 ON

Vendor:ONPackage Cooled:DIPD/C:05+

7824AF

NOTE: 1. The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage or temperature. 2. VDD bias must be operated before reset pulse operation. 3. Substrate DC bias(OFD bias) must be operated before horizontal, reset pulse operation.

7824CT

Vendor:MOT

You can connect the board directly to the DALI input (2 connections) or you can use the RS232/DALI converter board (for demo purposes with the 7824CT board) to connect it to the PC. The ballast control circuit uses the IR21592 Dimming Ballast Control IC programmed by the PIC16F628 microcontroller. The IR21592 controls the ballast according to the signals received from the microcontroller. The microcontro...

7824ON

7824ST

78250C

Vendor:C&DPackage Cooled:DIP6D/C:06+

1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.

78250MC

Vendor:MurataPackage Cooled:SOP-6D/C:09+

Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The Recommended Operating Conditions tables will define the conditions for actual device operation.

78253/55M

Vendor:C&DPackage Cooled:SOP-6D/C:2008+

For this application, the derived voltage reading, Vd, is related to the actual instantaneous line voltage Vi by the expression, Vd = Vi Kd/Kv or Vi = Vd Kv/Kd, where Kd is the digitization constant for the ADC in this applica- tion and Kv is the voltage proportionality constant for the circuit design. For this particular application, Kd is 204.6, the digital value from the ADC that represents 1V. Kv ...

7825335C

7825335MVC

78307P-1163

The ADR380 and ADR381 are precision 2.048 V and 2.500 V band gap voltage references featuring high accuracy, high stabil- ity, and low-power consumption in a tiny footprint. Patented temperature drift curvature correction techniques minimize nonlinearity of the voltage change with temperature. The wide operating range and low power consumption make them ideal for 3 V to 5 V battery-powered applications.

78307P-1168

Parameter ENCODE INPUTS (ENCODE, ENCODE) Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance LOGIC OUTPUTS (D15 to D0) Logic Compatibility Logic 1 VoltageILOAD 100 mA Logic 0 VoltageILOAD 100 mA Output Coding Series Output Resistanceper Bit

7830AU

Package Cooled:CDIP28D/C:2007+

7831CR

Vendor:TIPackage Cooled:SSOPD/C:08+

Using a true 10-bit color depth system, the 30-bit RGB color produces over 1.07 billion colors to represent High Definition (HD) displays in their most natural color, surpassing the maximum 16.7 million colors achieved by 6/8-bit color con- ventionally used for large-scale LCD televisions and LCD monitors.

7831CR

Vendor:TIPackage Cooled:SSOPD/C:08+

Using a true 10-bit color depth system, the 30-bit RGB color produces over 1.07 billion colors to represent High Definition (HD) displays in their most natural color, surpassing the maximum 16.7 million colors achieved by 6/8-bit color con- ventionally used for large-scale LCD televisions and LCD monitors.

78328-312

Vendor:NECPackage Cooled:QFP100

Rail-to-rail input and output voltage ranges 5.0V/µs slew rate Output settles to 2mV of supply rails High capacitive load capability -- up to 4000pF Symmetrical push-pull output drives No frequency compensation required -- unity gain stable Extremely low input bias currents -- 1.0pA typical (20pAMax) Ideal for high source impedance applications High voltage gain -- typically 150V/mV Outpu...

7832CTRLS

Vendor:IRPackage Cooled:SOP-8

78351A

Package Cooled:SOP16MD/C:2007+

7835AA

Vendor:InfineonPackage Cooled:TO252-3

On the next clock rise the data presented to DQs and DQP[A:D] (or a subset for byte write operations, see truth table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle.

7835AA

Vendor:InfineonPackage Cooled:TO252-3

On the next clock rise the data presented to DQs and DQP[A:D] (or a subset for byte write operations, see truth table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle.

78389-1

Vendor:ICPackage Cooled:PLCC

7838S

Package Cooled:SOP16WD/C:2007+

783JR

78400APE

7840341A-1

Package Cooled:BGA

Bits D7 and D6 in the register must be set low, and bits D5 through D0 control the gain range in 64 increments. See fig- ure for a graph of the PGA gain versus PGA register code. The coding for the PGA register is straight binary, with an all zero words corresponding to the minimum gain setting (1x) and an all one word corresponding to the maximum gain setting (5.85x).

784046(A)512

Vendor:NECPackage Cooled:QFP

After D/CLK and RES have been set, the time slot begins when ENI is driven to its active state. A falling edge on ENI causes the DS1481 to save the state of D/CLK and RES. If the time slot is a 1Cwire reset the DS1481 will issue a busy signal by driving O1/BSY1 low and O2/BSY2 high. After 2 µs O2/BSY2 is driven low. Both outputs will remain low until the communication on the I/O line is finish...

784214A

Vendor:NECPackage Cooled:02+D/C:QFP

• Pin to pin and functionally compatible to the Indus- try Standard 16450 • 2.97 to 5.5 volt operation • 1.5 Mbps transmit/receive operation (24MHz) • Programmable word lengths (5, 6, 7, 8) • Even, odd, force, or no parity generation and detection • Independent transmit and receive control • Standard modem interface • Low operating current ( 1.2mA typ.)

784214AY-113

The L1 memory system is the primary highest performance memory available to the Blackfin processor core. The L2 memory provides additional capacity with slightly lower performance. Lastly, the off-chip memory system, accessed through the External Bus Interface Unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing more than 768M bytes of external physical memory.

784215A

Vendor:NECPackage Cooled:TQFPD/C:03+

The microprocessor monitor circuitry of the 784215A provides three basic functions. First, a precision temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-of- tolerance condition occurs, an internal power-fail signal is generated which forces the reset to the active state. When VCC returns to an in-tolerance condition, the reset signals are kept in the active...

784215A105

Vendor:NECPackage Cooled:222D/C:07+

Use of the above model permits junction to lead thermal resistance for any mounting configuration to be found. For a given total lead length, lowest values occur when one side of the rectifier is brought as close as possible to the heat sink. Terms in the model signify: TA = Ambient TemperatureTC = Case Temperature TL = Lead TemperatureTJ = Junction Temperature RqS = Thermal Resistance, Heatsink to Ambi...

784216BGC114

Vendor:NECPackage Cooled:26212D/C:07+

International Rectifier Radiation Hardened MOSFETs are tested to verify their radiation hardness capability. The hardness assurance program at International Rectifier is comprised of two radiation environments. Every manufacturing lot is tested for total ionizing dose (per notes 5 and 6) using the TO-3 package. Both pre- and post-irradiation performance are tested and specified using the same drive circuit...

784224YGK502

Vendor:NECPackage Cooled:QFPD/C:0348+

Data is clocked on the negative transition of the CLOCK waveform. If less than 30 negative clock transitions have been received when the ENABLE line goes low (i.e., only B,M and A will have been clocked in), then the R counter latch will remain unchanged and only M and A will be transferred from the input shift register to the counter latches. This will protect the R counter from being corrupted by any glit...

7843ARQ

Vendor:SSOP-16Package Cooled:ADD/C:2004+

The SY88782L is a single supply 3.3V low power consumption, small form factor, driver for telecom/datacom applications using FP/DFB lasers at data rates up to 1.25Gbps. The driver can deliver modulation current up to 90mA, and the high compliance voltage it offers makes the part suitable for high-current operation (with the laser AC- or DC- coupled to it.) This device is intended to be used with Micrel MIC3...

7843E

Vendor:n/nD/C:07+

The MAX1165/MAX1166 16-bit, low-power, successive- approximation analog-to-digital converters (ADCs) fea- ture automatic power-down, factory-trimmed internal clock, and a 16-bit wide (MAX1165) or byte wide (MAX1166) parallel interface. The devices operate from a single +4.75V to +5.25V analog supply and a +2.7V to +5.25V digital supply. The MAX1165/MAX1166 use an internal 4.096V refer- ence or an external r...

7843I

Vendor:INTERSILPackage Cooled:TSSOP-8D/C:NULL

tsk(p)See Figure 350 † All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25C. ‡ Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V 0.5 V.

7844EM

• 100,000 erase/write cycle Enhanced Flash program memory typical • 1,000,000 erase/write cycle Data EEPROM memory typical • Flash/Data EEPROM Retention: > 40 years • Self-programmable under software control • Priority levels for interrupts • 8 x 8 Single-Cycle Hardware Multiplier • Extended Watchdog Timer (WDT): - Programmable period from 41 ms to 131...

78455

Vendor:ToshibaPackage Cooled:TO3P

The UCC5630A Multimode SCSI Terminator provides a smooth transition into the LVD SCSI Parallel Interface (SPI-2, SPI-3, SPI-4). It automatically senses the bus, via DIFFB, and switches the termination to either single ended (SE) or low voltage differential (LVD) SCSI, dependent on which type of devices are connected to the bus. The UCC5630A can not be used on a HVD, EIA485, differential SCSI bus. If the ...

7845CR

Vendor:TIPackage Cooled:SSOPD/C:08+

The DS7545X series of dual peripheral drivers is a family of versatile devices designed for use in systems that use TTL logic. Typical applications include high speed logic buffers, power drivers, relay drivers, lamp drivers, MOS drivers, bus drivers and memory drivers. The DS75451, DS75452 and DS75453 are dual peripheral AND, NAND and NOR drivers, respectively, (positive logic) with the output of th...

78471612-000

Package Cooled:QFP144D/C:00+

7847226

7847JR

Vendor:MAXPackage Cooled:SOP-24D/C:02+

When setting BC1# and BC2# at a high lev el or S1# at a high lev el or S2 at a low lev el, the chips are in a non- selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1#, BC2# and S1#, S2. The power supply c urrent is reduced as low as 0.2µA (25C, ty pical), and the me...