7001BB

Vendor:PHILIPSPackage Cooled:07+D/C:800

7001C

Vendor:LMIPackage Cooled:SMDD/C:98

The MCP6295s VCM for op amp B (pins VOUTA/VINB+ and VINBC) is VSS + 100 mV. The current at the MCP6295s VINBC pin is specified by IB only. This specification does not apply to the MCP6295s VOUTA/VINB+ pin. The MCP6295s VINBC pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD C 100 mV. The MCP6295s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL.

7001-ES/NO4

Vendor:M

7001GCS-A0051EK

7001I

Vendor:LMIPackage Cooled:SMDD/C:98

With the circuit modification shown in Figure 2, the trailing black level will be replaced with a trailing white level. If this white level equals the OSDFILL level then the trail effectively disappears, eliminating the finite switch time effect. This is shown in Figure 3. The resistor divider formed by R14 and R sets the brightness of the trailing white level, which can be set to equal the brightness of OS...

7001SB/MC

Vendor:NS

The first solution simply sacrifices the segment drive that share a cathode drive for each dual-digit. This is SEG dp for Digit 0 and Digit 1 discussed earlier. By examining Table 1, it can be seen that the other sacrificed segments are SEG f for Digit 2 and Digit 3, SEG d for Digit 4 and Digit 5, and SEG b for Digit 6 and Digit 7. However, it's usually the DP segments that applications can sacrifice, not se...

700208432

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal ...

70020AB

Vendor:STPackage Cooled:PDIP14D/C:9505

Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for d...

70020FB

Vendor:NSPackage Cooled:SIP-11PD/C:1994

Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example, for a fOP of 2.1MHz, the period equals 476ns. In this case if t CLH = is set to 190ns, then tCLL must be set to a minimum of 286ns.

700-2-0UM1C16

Package Cooled:BGA

70021AE2

Vendor:ADPackage Cooled:SOPD/C:03+

70021BB

Vendor:N/APackage Cooled:50D/C:N/A

The Samsung M464S1724CT1 is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M464S1724CT1 consists of eight CMOS 8M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy substrate. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M464S1724CT1 is ...

70022AB

Ultra low dropout voltage (110 mV @ 1.5A typ) Low ground pin current Load regulation of 0.04%/A 60 nA typical quiescent current in shutdown 1.5% output accuracy (25˚C) TO-220, TO-263 packages Over temperature/over current protection −40˚C to +125˚C junction temperature range

70023FB

Vendor:STPackage Cooled:SILD/C:06+

The 24xx128 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus must be con- trolled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions while the 24xx128 works as a slave. Both master a...

70023SC

Package Cooled:TSOP

Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via program- ming equipment.

70024AB

Vendor:STPackage Cooled:ZIP

for this lower supply voltage operation, in which case the sensitivity and zero g bias level specifications on this page will be met. Please contact the factory for specially trimmed devices for low supply voltage operation. The device operates over a 3.0V to 5.0V supply range. Please note that sensitivity and zero g bias level will be slightly different at 3.0V operation. For devices to be operated at 3...

70024B

Vendor:TIPackage Cooled:SSOP

Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 18.9mH, IAS = 4.5 A, VDD = 50V, RG = 25 Ω, Starting TJ = 25C 3. ISD 4.5A, di/dt 200A/µs, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse width 300µs, Duty cycle 2% 5. Essentially independent of operating temperature

70024B

Vendor:TIPackage Cooled:SSOP

Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 18.9mH, IAS = 4.5 A, VDD = 50V, RG = 25 Ω, Starting TJ = 25C 3. ISD 4.5A, di/dt 200A/µs, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse width 300µs, Duty cycle 2% 5. Essentially independent of operating temperature

70024SB

Vendor:PHILIPSPackage Cooled:07+D/C:800

Figure 3 illustrates a simplified model of the typical ZL40518 and the application. The ZL40518 consist of an ideal switched current source and an equivalent model of the ZL40518 output stage. The Electrical Model for the Laser Diode is a Voltage source Vd (V_on) in series with the On Resistance Rd all in parallel with the Junction Capacitance Cd. This simplified model approximately represents the Laser Diod...

700255813

Vendor:INTELD/C:03

The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits.

70025B

Vendor:SOP- 8Package Cooled:TID/C:2004+

The HT71XX series is a set of three-terminal low power high voltage regulators implemented in CMOS technology. They allow input voltages as high as 24V. They are available with several fixed output voltages ranging from 3.0V to 5.0V. CMOS technology ensures low voltage drop and low quiescent current.

70025FB

Vendor:STPackage Cooled:TO-220D/C:05+

These N-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switching DC/DC converte...

70027BB

Vendor:N/APackage Cooled:50D/C:N/A

In practice, VCC1 and the supply side of the choke on VCC2 will be tied to the same supply. It is important to isolate VCC1 from other RF and low-frequency bypass capacitors on this supply line. This can be accomplished using a suit- ably-long transmission line which is RF shorted on the other end as described above. Ideally the length of this line will be a quarter wavelength, but it only needs to be lon...

70027BB

Vendor:N/APackage Cooled:50D/C:N/A

In practice, VCC1 and the supply side of the choke on VCC2 will be tied to the same supply. It is important to isolate VCC1 from other RF and low-frequency bypass capacitors on this supply line. This can be accomplished using a suit- ably-long transmission line which is RF shorted on the other end as described above. Ideally the length of this line will be a quarter wavelength, but it only needs to be lon...

70027SC

7002A614-SL3PL

D/C:99

The FMS6346 Low Cost Video Filter (LCVF) provides 6dB gain (9dB optional, contact factory for further information) from input to output. In addition, the input will be slightly offset to optimize the output driver performance. The offset is held to the minimum required value to decrease the standing DC current into the load. Typical voltage levels are shown in the diagram below.

7002D

Vendor:JRCPackage Cooled:DIP8D/C:00+

Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface. SNMP Management frames can be received and transmitted via the CPU interface creating a complete network management solution.

7002EB

Vendor:MOTPackage Cooled:02+D/C:DIP

7002EB

Vendor:MOTPackage Cooled:02+D/C:DIP

7002SR

The DAC5687 is a dual-channel 16-bit high-speed digital-to-analog converter (DAC) with integrated 2x, 4x, and 8x interpolation filters, a complex numerically controlled oscillator (NCO), on-board clock multiplier, IQ compensation and on-chip voltage reference. The DAC5687 is pin compatible to the DAC5686, requir- ing only changes in register settings for most appli- cations, and offers additional fea...

70030.00

Vendor:NSPackage Cooled:SMDD/C:02+

70030AB

Vendor:PHIPackage Cooled:ZIP

The DS1265 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 20 address inputs (A0CA19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing...

70030AB

Vendor:PHIPackage Cooled:ZIP

The DS1265 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 20 address inputs (A0CA19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing...

70030BFAB001

Vendor:PHIPackage Cooled:SMD

The AD5381 is a complete, single-supply, 40-channel, 12-bit DAC available in a 100-lead LQFP package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5381 includes a programmable internal 1.25 V/2.5 V, 10 ppm/C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier bo...

70030SB

Vendor:PHILIPSPackage Cooled:07+D/C:800

70032AB

Vendor:PHILIPSPackage Cooled:07+D/C:800

Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BWEQ = 0.22/ (trCOMP2 C trIN2), where trIN is the 20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input.

70033AB

Vendor:PHIPackage Cooled:SIP9D/C:07+

Features 1) Synchronous rectification enables high efficiency 2) Built-in charge pump circuits for operating output power MOS 3) Built-in variable reset circuit 4) Built-in power MOS Tr requires fewer external components 5) Mute circuit built-in 6) Built-in thermal shut down circuit 7) SSOP-B16 package has a smaller board footprint

70034AB

Vendor:PHIPackage Cooled:SIP

Transmitter Operations: 1. 16-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver Operations: 1. Serial input 2. Serial-to-parallel conversion 3. 16-bit parallel output Internal clocking and control functions are transpar- ent to the user. S3067 Supports six different code rates, besides the normal rate, for each of the four operating modes.

70039

DESCRIPTION The number expressed in binary notation on these 3 bits is the number of the ST-BUS stream for the source of the connection. Bit 7 is the most significant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on STi4. The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (The S...

70040

7004010261

70040AB

Vendor:STPackage Cooled:99D/C:2000

RESET FLAG Proper operation of the RESET circuity is not guaranteed for VIN voltages of less than 2.0V. The RESET pin will provide information on the status of the regulator VOUT voltage level. Any condition that causes the VOUT voltage to drop to typi- cally 89% normal would cause the RESET pin to go low. This will warn of a system Vcc supply that may cause abnormal operation. Of course, when the re...

70040AB

Vendor:STPackage Cooled:99D/C:2000

RESET FLAG Proper operation of the RESET circuity is not guaranteed for VIN voltages of less than 2.0V. The RESET pin will provide information on the status of the regulator VOUT voltage level. Any condition that causes the VOUT voltage to drop to typi- cally 89% normal would cause the RESET pin to go low. This will warn of a system Vcc supply that may cause abnormal operation. Of course, when the re...

700410F

Vendor:ONPackage Cooled:02+D/C:TO220-5P

The M41T81S Serial Access TIMEKEEPER ® SRAM is a low power Serial RTC with a built-in 32.768kHz oscillator (external crystal controlled). Eight bytes of the SRAM (see Table 2., page 12) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 bytes of SRAM provide status/ control of Alarm, Watchdog and Square Wave functions. Addresses an...

700410F

Vendor:ONPackage Cooled:02+D/C:TO220-5P

The M41T81S Serial Access TIMEKEEPER ® SRAM is a low power Serial RTC with a built-in 32.768kHz oscillator (external crystal controlled). Eight bytes of the SRAM (see Table 2., page 12) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 bytes of SRAM provide status/ control of Alarm, Watchdog and Square Wave functions. Addresses an...

70044

Vendor:UNITRDEPackage Cooled:PLCCD/C:03+

− Timer 1: Offers auto-reload function and one of two internal clock frequencies (FOSC or FOSC/64) can be selected or falling edge of pin RC.0 can be selected (output through MFP pin) • Built-in 18/14-bit watchdog timer selectable for system reset • Powerful instruction set: 118 instructions • 8-level subroutine (include interrupt) nesting

70044SB

Vendor:ALLEGROD/C:08+

The DC/DC power module shall be installed in an end-use equip- ment and considerations should be given to measuring the case tem- perature to comply with TC max when in operation. Abnormal compo- nent tests are conducted with the input protected by an external 3 A fuse. The need for repeating these tests in the end-use appliance shall be considered if installed in a circuit having higher rated devices.

70045SB

Vendor:PHPackage Cooled:96D/C:DIP-24

stream. EEPROM emulation (bit or byte alterability) is easily handled with a self- contained three step Read-Modify-Write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a SPI serial interface to sequentially access its data. DataFlash sup- ports SPI mode 0 and mode 3. The simple serial interface facilitates h...

70046402

The AT40KAL is a family of fully PCI-compliant, SRAM-based FPGAs with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), auto- matic component generators, and range in size from 5,000 to 50,000 usable gates. I/O counts range from 128 to 384 in industry standard packages ranging f...

70049SB

Vendor:ONPackage Cooled:PLCC44D/C:08+

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

7004D-1M-330M

The HC595 contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading.

7004D-1M-3R3M

D/C:08+

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

7005060

Vendor:MOTPackage Cooled:QFPD/C:NULL

The IP117M Series are three terminal positive adjustable voltage regulators capable of supplying in excess of 0.5A over a 1.25V to 60V output range. These regulators are exceptionally easy to use and require only two external resistors to set the output voltage. In addition to improved line and load regulation, a major feature of the A series is the initial output voltage tolerance, which is guaranteed to...

70050A

The Power Saving (PS) module implements the Idle Mode (ARM7TDMI core clock stopped until the next interrupt) and enables the user to adapt the power consumption of the microcontroller to application requirements (independent peripheral clock control).

70053D

Vendor:TIPackage Cooled:SOP-8

The test set described in this paper allows complete quanti- tative characterization of all dc operational amplifier param- eters quickly and with a minimum of additional equipment The method used is accurate and is equally suitable for lab- oratory or production test for quantitative readout or for limit testing As embodied here the test set is conditioned for testing the LM709 and LM101 amplifiers ho...

70053D

Vendor:TIPackage Cooled:SOP-8

The test set described in this paper allows complete quanti- tative characterization of all dc operational amplifier param- eters quickly and with a minimum of additional equipment The method used is accurate and is equally suitable for lab- oratory or production test for quantitative readout or for limit testing As embodied here the test set is conditioned for testing the LM709 and LM101 amplifiers ho...

700560FB

7005ACDR

7005BCF

Vendor:FAIPackage Cooled:SOP8

The Spartan™ and the Spartan-XL families are a high-vol- ume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume, approach and in many cases are equivalent to mask pro- grammed ASIC devices.

7005L45J

7005MC

1.1 Scope. This specification covers the performance requirements for NPN, Darlington, silicon, power transistors. Two levels of product assurance are provided for each device type as specified in MIL-PRF-19500. For JAN quality assurance level (see 6.3).

7005MC

1.1 Scope. This specification covers the performance requirements for NPN, Darlington, silicon, power transistors. Two levels of product assurance are provided for each device type as specified in MIL-PRF-19500. For JAN quality assurance level (see 6.3).

7005S15J

Vendor:sdtPackage Cooled:95+D/C:PLCC-68P

Clocks in the ispLSI 2096V device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock.

70060F

Vendor:CHERRYPackage Cooled:SOP-8

(2) Storage The LEDs should be stored at 30C or less and 70%RH or less after being shipped from Nichia and the storage life limits are 3 months.If the LEDs are stored for 3 months or more, they can be stored for a year in a sealed container with a nitrogen atmosphere and moisture absorbent material. Nichia LED leadframes are comprised of a silver plated Iron. The silver surface may be affected by envi...

70065SB

Vendor:PHIPackage Cooled:SOP-7.2-32PD/C:6+

The memory array of the 70065SB can be sectored in two ways simply by using two differ- ent erase commands. Using one erase command allows the device to contain a total of eleven sectors comprised of a 64-Kbyte boot sector, six 64-Kbyte sectors, a 32-Kbyte sector, a 16- Kbyte sector, and two 8-Kbyte sectors. The 64-Kbyte boot sector is located at the top (upper- most) of the devices memory address space an...

70065SBDD

Output of the error amplifier for compensation Analog ground return pin Input to the current limit comparator Inverting input to the error amplifier Non-inverting input to the error amplifier High current totem pole output A of the on-chip drive stage. High current totem pole output B of the on-chip drive stage. Ground return pin for the output driver stage Non-inverting input to the PWM comparator...

70065SBDD

Output of the error amplifier for compensation Analog ground return pin Input to the current limit comparator Inverting input to the error amplifier Non-inverting input to the error amplifier High current totem pole output A of the on-chip drive stage. High current totem pole output B of the on-chip drive stage. Ground return pin for the output driver stage Non-inverting input to the PWM comparator...

70067AB

Vendor:PHILPSPackage Cooled:ZIP-23

The M95040 is a 4 Kbit (512 x 8) electrically eras- able programmable memory (EEPROM), access- ed by a high speed SPI-compatible bus. The other members of the family (M95020 and M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial inter- face that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2. and Figur...

70067AB

Vendor:PHILPSPackage Cooled:ZIP-23

The M95040 is a 4 Kbit (512 x 8) electrically eras- able programmable memory (EEPROM), access- ed by a high speed SPI-compatible bus. The other members of the family (M95020 and M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial inter- face that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2. and Figur...

70068FB

Parallel Enable (Active LOW) Input Parallel Data Inputs First Stage J (Active HIGH) Input First Stage K (Active LOW) Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs (Note b) Complementary Last Stage Output (Note b)

7006L20PFI

Vendor:IDTPackage Cooled:734D/C:25

The VC33 instruction register is 8 bits long. Table 1 shows the instructions code. The uses of SAMPLE and HIGHZ opcodes, though defined, have no meaning for the SM/SMJ320VC33, which has no boundary scan. For example, HIGHZ will affect only the dummy cell (no meaning) and will not put the device pins in a high-impedance state.

7006S20J

Vendor:IDTPackage Cooled:PLCC68D/C:2007+

7006S35J

Vendor:IDTPackage Cooled:01+D/C:PLCC-68P

Space saving POWR-T™ fuses are the most compact fuses available in ratings above 30 amperes less than one-third the size of comparable Class R fuses. When rated in accor- dance with the NEC, POWR-T fuses provide fast-acting overload and short circuit protection for non-inductive circuits and equipment. Used in inductive circuits, the ampere rating of POWR-T fuses must be increased to prevent ope...

70070-615

70071SB

Package Cooled:QFP

In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the TLC77...

70072-200

2.2 Order of precedence. In the event of a conflict between the text of this document and the references cited herein, the text of this document shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.

70072AB

Vendor:300

The four bytes at memory addresses 01 to 04 contain the UniqueWare Project ID 00001129H. The two bytes at addresses 0BH and 0CH are the 16-bit CRC over the length byte, Project ID and node address value. The least significant byte of the CRC is stored at address 0B. This CRC is generated according to the standardized CRC16 polynomial function X16 + X15 + X2 + 1. For more details on generating CRC values incl...

70072FB0

Vendor:NECPackage Cooled:1200D/C:07+

Maximum Average Forward Rectified Current at Tc=125OC Peak Repetitive Forward Current (Rated VR, Square Wave, 20KHz) at Tc=125oC Peak Forward Surge Current, 8.3 ms Single Half Sine-wave Superimposed on Rated Load (JEDEC method ) Peak Repetitive Reverse Surge Current (Note 1)

70072FBO

Package Cooled:DIP

International Rectifiers RAD HARD technology HEXFETs demonstrate excellent threshold voltage stability and breakdown voltage stability at total radiaition doses as high as 1x106 Rads(Si). Under identical pre- and post-irradiation test conditions, In- ternational Rectifiers RAD HARD HEXFETs retain identical electrical specifications up to 1 x 105 Rads (Si) total dose. No compensation in gate drive circu...

70072FBO

Package Cooled:DIP

International Rectifiers RAD HARD technology HEXFETs demonstrate excellent threshold voltage stability and breakdown voltage stability at total radiaition doses as high as 1x106 Rads(Si). Under identical pre- and post-irradiation test conditions, In- ternational Rectifiers RAD HARD HEXFETs retain identical electrical specifications up to 1 x 105 Rads (Si) total dose. No compensation in gate drive circu...

700732TP

7007-FBC9

Package Cooled:TO-92

This new generation of trench MOSFETs from Zetex utilizes a unique structure that combines the benefits of low on-resistance with fast switching speed. This makes them ideal for high efficiency, low voltage, power management applications.

7007S20PF

Vendor:IDTPackage Cooled:QFPD/C:N/A

The Intersil ISL4238E/44E/45E devices are 2.7V to 5.5V powered RS-232 transmitters/receivers which meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Additionally, they provide 15kV ESD protection (IEC6100-4-2 Air Gap and Human Body Model) on transmitter outputs and receiver inputs (RS-232 pins). Targeted applications are PDAs, Palmtops, and notebook and laptop computers where the low...

7007S20PF

Vendor:IDTPackage Cooled:QFPD/C:N/A

The Intersil ISL4238E/44E/45E devices are 2.7V to 5.5V powered RS-232 transmitters/receivers which meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Additionally, they provide 15kV ESD protection (IEC6100-4-2 Air Gap and Human Body Model) on transmitter outputs and receiver inputs (RS-232 pins). Targeted applications are PDAs, Palmtops, and notebook and laptop computers where the low...

7007S35JI

•The module is a Max.4dBm( Class2 ) module. •Bluetooth® standard Ver1.1 conformity. •Internal baseband clock oscillator. •Internal 1.8V regulator •Low current consumption •Support functions

7007SE

Vendor:STPackage Cooled:SOP-20D/C:06+

256-position TTP (two-time programmable) set-and-forget resistance setting allows second-chance permanent programming Unlimited adjustments prior to OTP (one-time programming) activation OTP overwrite allows dynamic adjustments with user defined preset End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Compact MSOP-10 (3 mm 4.9 mm) package Fast settling time: tS = 5 &micr...

7008 /7843YB

Vendor:INTERSILPackage Cooled:95+D/C:DIP-22

70080SR

Vendor:PHIPackage Cooled:QFP

70085FB

Vendor:ONPackage Cooled:TO-220/5D/C:05+

10 ms. typical 5 ms. typical 100 MΩ, at 500 VDC, 50%RH 500 Vrms,1 min. 10 g,11ms. DA 1.5 mm, 10 - 55 Hz 1 M height drop on concrete Standard: 0.6W; Big Gap: 0.8W -30ºC to 85ºC operating; -40ºC to 100ºC storage 6 g, approx.

700882-002

Fixed Frequency 1.2MHz/2.2MHz Operation Very Low Noise: 1mVP-P Output Ripple C 5V at 350mA from 5V Input C12V at 150mA from 5V Input Uses Small Surface Mount Components Wide Input Range: 2.6V to 16V Low Shutdown Current: <1µA Low VCESAT Switch: 400mV at 1A Low Profile (1mm) ThinSOTTM Package Pin-for-Pin Compatible with the LT1611

700883-002

Vendor:.Package Cooled:2005D/C:500

General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Regis...

700883-002

Vendor:.Package Cooled:2005D/C:500

General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Regis...

700884

Vendor:N/APackage Cooled:N/AD/C:N/A

700884

Vendor:N/APackage Cooled:N/AD/C:N/A

7008DSB

Vendor:4500Package Cooled:03+D/C:TQFP64

SMJ320C62x, VelociTI, and C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. All trademarks are the property of their respective owners. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

700900

Vendor:NSPackage Cooled:PLCC

Highest pin bandwidth available 4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling • Bi-directional differential RSL (DRSL) - Flexible read/write bandwidth allocation - Minimum pin count • On-chip termination -Adaptive impedance matching -Reduced system cost and routing complexity

700923

Vendor:TPPackage Cooled:30D/C:N/A

NOTES: 1. Address A14X is a NC for IDT70V9269. 2. LB and UB are single buffered regardless of state of FT/PIPE. 3. CE0 and CE1 are single buffered when FT/PIPE = VIL, CE0 and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.

700923

Vendor:TPPackage Cooled:30D/C:N/A

NOTES: 1. Address A14X is a NC for IDT70V9269. 2. LB and UB are single buffered regardless of state of FT/PIPE. 3. CE0 and CE1 are single buffered when FT/PIPE = VIL, CE0 and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.

70097SB1

Vendor:PHILIPSPackage Cooled:TQFPD/C:2005

Drain-to-Source Breakdown Voltage Gate Threshold Voltage  Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Zero Gate Voltage Drain Current Static Drain-to-Source  On-State Resistance (TO-39) Static Drain-to-Source  On-State Resistance (SMD-0.5) Diode Forward Voltage 

70099FR