74ABT16541DL

Vendor:PHIPackage Cooled:SSOPD/C:N/A

These graphs show mixer conversion loss vs. frequency, with both low-side LO excitation (LO frequency below the RF fre- quency) and high side excitation (LO frequency above the RF frequency). Operation both as a down-converter and an up- converter is shown, with LO powers of 14, 17, and 20dBm. In all cases, the IF frequency is 150MHz.

74ABT16541DL

Vendor:PHIPackage Cooled:SSOPD/C:N/A

These graphs show mixer conversion loss vs. frequency, with both low-side LO excitation (LO frequency below the RF fre- quency) and high side excitation (LO frequency above the RF frequency). Operation both as a down-converter and an up- converter is shown, with LO powers of 14, 17, and 20dBm. In all cases, the IF frequency is 150MHz.

74ABT16543BDSM

convection cooling and have an operational ambient temperature range in compliance with present and future application needs, including non temperature controlled environments. The mechanical design offers the choice of surface mount or through-hole versions, delivered in ready-to-use tubes, trays or tape & reel package and compatibility with semi and fully aqueous cleaning processes. The PKF series is ...

74ABT16543CMTD

Vendor:FSCPackage Cooled:TSSOPD/C:08+

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. 60 to 150 seconds maximum above 183C, 260C peak.

74ABT16543CMTDX

Vendor:FAIRCHILDPackage Cooled:TSS0PD/C:07+

The WM8802 is controlled via a 4-wire CCB compatible control interface. This interface provides access to the channel status bits. The WM8802 also provides a number of flag outputs including PCM data valid, de-emphasis, lock and IEC 61937, DTS-CD/LD detection.

74ABT16543CMTDX

Vendor:FAIRCHILDPackage Cooled:TSS0PD/C:07+

The WM8802 is controlled via a 4-wire CCB compatible control interface. This interface provides access to the channel status bits. The WM8802 also provides a number of flag outputs including PCM data valid, de-emphasis, lock and IEC 61937, DTS-CD/LD detection.

74ABT16543CSSC

Vendor:FSCPackage Cooled:SSOP7.2D/C:07+

When #CE and #RESET pins are at VDD, the ICC CMOS standby mode is enabled. When the #RESET pin is at VSS, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from #RESET switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from #RESET-high until writes to the CUI are recognized. With #R...

74ABT16543CSSCX

Vendor:FAIRCHILDPackage Cooled:SSOP56D/C:07+

The A/D D/A converters are implemented with 2nd- order sigma-Delta modulators. The on-chip digital filters, which are carried out with 16-bit and 2's complement format, are used to get the required frequency response of a PCM Codec. The Codec can support 8-bit u/A law and linear format. For the latter, it is 16-bit format with 14-bit resolution .

74ABT16543CWM

DESCRIPTION The ST3237E is a 3V to 5.5V powered EIA/ TIA-232 and V.28/V.24 communication interfaces high data-rate capability and enhanced electrostatic discharge (ESD) protection at 8KV using IEC1000-4-2 contact discharge and 15kV using Human Body Model (HBM). The other pins are protected with standard ESD protection at 2kV using HBM method. The ST3237C is a transceiver (5 drivers, 3 receivers) f...

74ABT16543DGG

Vendor:PHIPackage Cooled:TSOP56D/C:2007+

Note 9: For best accuracy, minimize output loading. Higher sink currents can affect sensor accuracy with internal heating. This can cause an error of 0.64˚C at full rated sink current and saturation voltage based on junction-to-ambient thermal resistance.

74ABT16543DGGR

Vendor:TI

Since the CDC913 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the X1 input, and following any changes to the SELn inputs.

74ABT16543DLR

Vendor:TI

NOTES: 1. Minimums are guaranteed but not production tested. 2. This parameter is guaranteed but not production tested. 3. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.12ns for CL = 50pF. Since this time constant is much smaller than the rise and fall times o...

74ABT16601

Vendor:TIPackage Cooled:SMD

The HEXFET technology is the key to International Rectifiers advanced line of power MOSFET transistors. The efficient geometry and unique processing of this latest State of the Art design achieves: very low on-state resis- tance combined with high transconductance. The HEXFET transistors also feature all of the well established advantages of MOSFETs such as volt- age control, very fast switching, eas...

74ABT16623DL

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

74ABT16646

Vendor:TID/C:97

The LS160 and LS162 count modulo-10 in the BCD (8421) sequence From state 9 (HLLH) they increment to state 0 (LLLL) The 161 and 163 count modulo-16 binary se- quence From state 15 (HHHH) they increment to state 0 (LLLL) The clock inputs of all flip-flops are driven in parallel through a clock buffer Thus all changes of the Q outputs (except due to Master Reset of the LS160) occur as a re- sult of and ...

74ABT16646C

Vendor:FAIRCHILDPackage Cooled:SMDD/C:03+

Luma/Chroma Swap. Internally pulled-up. YCSWAP=0 indicates a luminance sample is the first sample following the leading edge of HSYNC*. YCSWAP=1 indicates a chroma sample (Cb or CR depending on CbSWAP) is the first sample following the leading edge of HSYNC*. See Figure 5 on page 7. Frequency Select. Internally pulled-up FS = 1 (default), then DCLK = 40.5 MHz, ACLK = 16.934 MHz FS = 0, then DCLK = 33.9 MHz,...

74ABT16646CMTD

Connect a resistor from this pin to the drain of the upper PWM MOSFET. This resistor, an internal 40µA current source (typical), and the upper MOSFETs on-resistance set the converter overcurrent trip point. An overcurrent trip cycles the soft-start function.

74ABT16646DL

Vendor:PHILIPSPackage Cooled:TSOPD/C:08+

Byte 0: Frequency, Function Select Register Bit @Pup Pin# Description, see page 8 for SSCG description. 70n/aS4 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1 60n/aS2 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1 50n/aS1 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1 40n/aS0 (for freque...

74ABT16646DLR

Vendor:TIPackage Cooled:TSSOPD/C:2000

The MAX1978 operates from a single supply and provides bipolar 3A output by biasing the TEC between the outputs of two synchronous buck regulators. True bipolar operation controls temperature without dead zones or other nonlin- earities at low load currents. The control system does not hunt when the set point is very close to the natural operating point, where only a small amount of heating or cooling is nee...

74ABT16652CSSC

The CS61880 is a full-featured Octal E1 short-haul LIU that supports 2.048 Mbps data transmission for both E1 75 Ω and E1 120 Ω applications. Each channel provides crystal-less jitter attenuation that complies with the most stringent standards. Each channel also provides internal AMI/HDB3 encoding/decoding. To support enhanced system diagnostics, channel zero can be configured for G.772 no...

74ABT16652CSSC

The CS61880 is a full-featured Octal E1 short-haul LIU that supports 2.048 Mbps data transmission for both E1 75 Ω and E1 120 Ω applications. Each channel provides crystal-less jitter attenuation that complies with the most stringent standards. Each channel also provides internal AMI/HDB3 encoding/decoding. To support enhanced system diagnostics, channel zero can be configured for G.772 no...

74ABT16652DL

Vendor:PHILIPSPackage Cooled:TSOPD/C:08+

Note : 1.All voltages are referenced to VSS = 0V 2.VDD/VDDQ(min) is 3.15V for HY5V62CF-7/S 3.VIH (max) is acceptable 5.6V AC pulse width with 3ns of duration with no input clamp diodes 4.VIL (min) is acceptable -2.0V AC pulse width with 3ns of duration with no input clamp diodes

74ABT16821ADL

Vendor:PHIPackage Cooled:SSOPD/C:0035+

N otes: 1. D Q -to-I/O wiring is shown as recom m ended but m ay be changed 2. D Q /D Q S/D M /C KE /S relationships m ust be m aintained as shown 3. D Q , D Q S, D M /D Q S resistors : 22O hm s+ /-5% 4. V D D ID strap connections (for m em ory dev ice V D D , V D D Q ) : S trap out :(open) : VD D = VD D Q S trap In (V ss) : V D D = V D D Q

74ABT16823

Vendor:TIPackage Cooled:05+D/C:3360

Voltage gain Upper cut-off frequency (Fig. 3) Lower cut-off frequency (Fig. 3) Propagation delay Max. rectified video output current (Fig. 4 and 5) Variation of gain supply voltage Variation of maximum rectified output current with supply voltage Maximum input signal before overload Noise figure (Fig. 6) Maximum RF output voltage Supply current

74ABT16823ADGG

Vendor:PHILIPSPackage Cooled:TSOPD/C:08+

Master Clock. Master clock provides the clock for DSP. In MPI mode, it can be 1.536 MHz, 1.544 MHz, 2.048 MHz, 3.072 MHz, 3.088 MHZ, 4.096 MHz, 6.144 MHz, 6.176 MHz or 8.192 MHz. It can be asynchronous to BCLK. In GCI mode, it is recommended to connect MCLK and DCL pin together. The frequency of MCLK can be 2.048 MHz or 4.096 MHz. See BCLK/DCL pin description.

74ABT16823ADL

Vendor:PHIPackage Cooled:SSOPD/C:N/A

Hynix HYMD532646(L)6-K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Mem- ory Modules (DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD532646(L)6-K/H/L series consists of four 32Mx16 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HMD532646(L)6-K/H/L series provide a high performance 8-byte interface in 5.25" width ...

74ABT16823ADL518

74ABT16825DL

For example, assume a desired continuous output current of 1.0A, an input voltage of 5V, and an FZT749 pass transistor. The FZT749 has a typical hFE of 170, and a VBE of 0.8V; both specified at a collector current of 1.0A. Substituting these values into the equation above results in an RB value of 704Ω (closest standard value = 680Ω).

74ABT16833DL

Vendor:PHIPackage Cooled:06+D/C:1284

The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO) at 12 times the TCLK frequency. For example, if TCLK is 10 MHz, the serial rate is 10 12 = 120 Mbps. Because only 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 12 MHz, the useful data rate is 10 12 = 120 Mbps. The data source, which provides...

74ABT16833DL

Vendor:PHIPackage Cooled:06+D/C:1284

The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO) at 12 times the TCLK frequency. For example, if TCLK is 10 MHz, the serial rate is 10 12 = 120 Mbps. Because only 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 12 MHz, the useful data rate is 10 12 = 120 Mbps. The data source, which provides...

74ABT16833DLR

Vendor:TID/C:96+

The NL17SZ07 is a high performance single inverter with open drain outputs operating from a 1.65 to 5.5 V supply. The Output stage is open drain with Over Voltage Tolerance. This allows the NL17SZ07 to be used to interface 5.0 V circuits to circuits of any voltage between 0 and +7.0 V.

74ABT16833DLR10

Vendor:TID/C:96+

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in aval...

74ABT16841ADGG

Vendor:PHILIPSPackage Cooled:TSOPD/C:08+

This demonstrates that with more complex devices the con- cept of CPD greatly simplifies the calculation of total power consumption. It becomes an easy task to compute power for different voltages and frequencies by use of Figure 6 and the equations above.

74ABT16841ADL

Vendor:NXPPackage Cooled:SSOP56D/C:0811

BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. To perform a Buffer Read, the eight bits of the opcode must be followed by 14 dont care bits, ten address bits, and eight dont care bits. Since the buffer si...

74ABT16841DLR

Vendor:TI

requires that the differential linearity error not exceed 1 LSB in the negative direction. MONOTONICITY: A DAC is said to be monotonic if the out- put either increases or remains constant as the digital input increases. UNIPOLAR OFFSET ERROR: The deviation of the analog output from the ideal (0 V or 0 mA) when the inputs are set to all 0s is called unipolar offset error. BIPOLAR OFFSET ERROR: The devia...

74ABT16841DLR

Vendor:TI

requires that the differential linearity error not exceed 1 LSB in the negative direction. MONOTONICITY: A DAC is said to be monotonic if the out- put either increases or remains constant as the digital input increases. UNIPOLAR OFFSET ERROR: The deviation of the analog output from the ideal (0 V or 0 mA) when the inputs are set to all 0s is called unipolar offset error. BIPOLAR OFFSET ERROR: The devia...

74ABT16899DGG

The MAX3060E features slew-rate-limited drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 115kbps. The MAX3061E, also slew- rate limited, transmits up to 500kbps. The MAX3062E driver is not slew-rate limited, allowing transmit speeds up to 20Mbps. All transmitter outputs are protected to 15kV using the Human Body Model.

74ABT168ADL

Vendor:PHILIPSPackage Cooled:TSOPD/C:08+

The HYM72V16M636TU6 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of four 16Mx16bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.

74ABT16952CMTD

Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface. SNMP Management frames can be received and transmitted via the CPU interface creating a complete network management solution.

74ABT16952CSSC

Vendor:580

The necessary decimation and interpolation operations are activated automatically when the format is set. Together with a corresponding Memory Sync Controller (SDA 9220) it enables functions like multi-picture, tuner scanning, picture-in-still and still-in-picture. The different modes can be activated by a microcontroller on the I2C Bus interface (slave receiver). The I2C Bus address for accessing the d...

74ABT16952DGG

The MAX 7000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density integration of SSI, MSI, and LSI logic functions. It easily integrates multiple devices including PALs, GALs, and 22V10s devices. MAX 7000A devices are available in a wide range of packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA, PQFP, and TQFP packages. See Table 3 and Table 4.

74ABT16952DLR

Vendor:TIPackage Cooled:TSSOPD/C:2000

Simultaneous 50Hz/60Hz Rejection (87dB Minimum) Differential Input and Differential Reference with GND to VCC Common Mode Range 2ppm INL and No Missing Codes at 24 Bits 0.1ppm Offset and 2.5ppm Full-Scale Error 0.16ppm Noise No Latency: Digital Filter Settles in a Single Cycle. Internal OscillatorNo External Components Required 24-Bit ADC in Narrow SSOP-16 Package (SO-8 Footprint) Single Supply 2.7V to ...

74ABT16952DLR10

Vendor:TexasD/C:95

74ABT20

Vendor:99Package Cooled:99/00+D/C:TSSOP14

Input or Output Voltage (DC or Transient) (Referenced to VSS Vin, Vout for Control Inputs and VEE for Switch I/O) Input Current (DC or Transient), per Control PinIin Switch Through CurrentISW Power Dissipation. Per Package**PD Storage TemperatureTstg Lead Temperature (8 - Second Soldering)TLead * Maximum Ratings are those values beyond which damage to the device may occur. ** Temperature Derating: DIP a...

74ABT20

Vendor:99Package Cooled:99/00+D/C:TSSOP14

Input or Output Voltage (DC or Transient) (Referenced to VSS Vin, Vout for Control Inputs and VEE for Switch I/O) Input Current (DC or Transient), per Control PinIin Switch Through CurrentISW Power Dissipation. Per Package**PD Storage TemperatureTstg Lead Temperature (8 - Second Soldering)TLead * Maximum Ratings are those values beyond which damage to the device may occur. ** Temperature Derating: DIP a...

74ABT20D

Vendor:PHIPackage Cooled:SOPD/C:01+

FR CPU • 32-bit RISC, load/store architecture, 5-stage pipeline • Operating frequency 66MHz [with PLL: base frequency 16.5 MHz] • 16-bit fixed length instructions (basic instructions), 1 instruction per cycle • Instructions for built-in applications: memory-to-memory transfer, bit processing, barrel shift etc. • Instructions adapted for high-level languages: function inp...

74ABT224

Vendor:FAIRCHILDPackage Cooled:SOP-20

One of the industry's first ultra high-speed, 8-bit data converters with highest AC performance and a GHz input bandwidth, the MAX104/6/8 family of data converters offers both sampling speed and signal bandwidth for applications where these parameters are of the utmost importance. At their introduction in 1999, this family of high-speed analog-to-digital converters (ADCs) set a new standard for dynamic perf...

74ABT2240

Vendor:PHILIPSPackage Cooled:2005D/C:500

74ABT2240C

Vendor:FAIRCHILDPackage Cooled:03+D/C:SOP-7.2-20P

* Specifications will vary with foreign standards certification ratings. *1 Measurement at same location as "Initial breakdown voltage" section. *2 Detection current: 10mA. *3 Nominal voltage applied to the coil, excluding contact bounce time. *4 By resistive method, nominal voltage applied to the coil; contact carrying current: 1 A. *5 Half-wave pulse of sine wave: 6 ms; detectio...

74ABT2240CMSA

Ÿ Miniature, cost-effective switching solution. Ÿ State of the art capsule designs. Ÿ Molded construction for compatibility with automatic board processing. Ÿ Epoxy-molded dual-in-line package. Ÿ Completely washable.

74ABT2240CSC

Maximum Average Forward Current at TC = 55C Peak Forward Surge Current, 8.3 ms single half sine - wave superimposed on rated load Maximum Forward Voltage Drop per Element at 12.5A Maximum Reverse Current at Rated DC Blocking Voltage per Element(see Fig 4)

74ABT2240CSJ

INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12) SCL Clock FrequencyfSCL tBUF Bus free time between STOP & STARTt1 tHD;STA Hold Time (repeated START)t2After this period the first clock pulse is generated tLOW Low Period of SCL Clockt3 tHIGH High Period of SCL Clockt4 tSU;STA Setup Time For START Condition t5 tHD;DAT Data Hold Timet6 tSU;DAT Data Setup Timet7 tR Rise Time of both SDA &...

74ABT2240D

Vendor:PHILIPSPackage Cooled:SOP20D/C:0118+/9922+

Fully compatible with the standard 8051 microcontroller Superset of the 8051 architecture with 8 datapointers Up to 20 MHz operating frequency C 375 ns instruction cycle time @ 16 MHz C 300 ns instruction cycle time @ 20 MHz (50% duty cycle) Program Memory C 32K bytes of on-chip OTP memory C Externally expandable up to 64 Kbytes 256-byte on-chip RAM 256-byte on-chip XRAM Five 8-bit and one 6-bit...

74ABT2240D-T

Vendor:ＮＸＰ

74ABT2240PW

Vendor:PHIPackage Cooled:TSSOPD/C:01+

Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.13 Note c: Bringing E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Note d: VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCC...

74ABT2241

Vendor:PHILIPSPackage Cooled:TSOPD/C:08+

BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of t...

74ABT2241

Vendor:PHILIPSPackage Cooled:TSOPD/C:08+

BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of t...

74ABT2241DB

Vendor:PHIPackage Cooled:SSOPD/C:01+

The DVR EN*, DATA, and VTT EN pins are digital inputs that control the driver (see Table 1). With DVR EN* low, DATA determines whether the driver will force VH or VL at DOUT. With DVR EN* high, VTT EN* controls whether the driver goes into high impedance or drives VTT..

74ABT2241PW

Vendor:PHIPackage Cooled:TSSOPD/C:01+

While in user mode, the RC4700 provides a single, uniform virtual address space of 256GB (2GB for 32-bit address mode). When oper- ating in the kernel mode, four distinct virtual address spacestotalling 1024GB (4GB in 32-bit address mode)are simultaneously available and are differentiated by the high-order bits of the virtual address.

74ABT2244

Vendor:PHIPackage Cooled:SSOPD/C:98

∗1 The VDD typical voltage setting is noted as 12.0V in these specifications. ∗2 Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below. ∗3 For the VDDG, VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing Zener diode as shown in the figure below.

74ABT2244AN

On the positive transition of the clock (CLK) input, the Q outputs are set to the complement of the logic states set up at the data (D) inputs. The ALS534A and SN74AS534 have inverted out- puts, but otherwise are functionally equivalent to the ALS374A and SN74AS374.

74ABT2244APW

Vendor:PHI

Typical active current 400 mA Typical standby current 25 mA Reliable CMOS floating gate technology 4 5V to 5 5V operation in all modes MICROWIRE compatible serial I O Self-timed programming cycle Device status indication during programming mode 15 years data retention Endurance 100 000 read write cycles minimum Packages available 8-pin DIP 8-pin SO

74ABT2244APW

Vendor:PHI

Typical active current 400 mA Typical standby current 25 mA Reliable CMOS floating gate technology 4 5V to 5 5V operation in all modes MICROWIRE compatible serial I O Self-timed programming cycle Device status indication during programming mode 15 years data retention Endurance 100 000 read write cycles minimum Packages available 8-pin DIP 8-pin SO

74ABT2244C

Vendor:FAIRCHILDPackage Cooled:SOP-20D/C:03+

POWER SUPPLY Supply Voltages AVDD DVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD)4 Digital Supply Current (IDVDD)5 Supply Current Sleep Mode (IAVDD) Power Dissipation4 (5 V, IOUTFS = 20 mA) Power Dissipation5 (5 V, IOUTFS = 20 mA) Power Dissipation6 (5 V, IOUTFS = 20 mA) Power Supply Rejection Ratio7AVDD Power Supply Rejection Ratio7DVDD

74ABT2244CMSA

The integrated receiver is intended to be used as a single-conversion FSK/OOK receiver. It consists of a low noise amplifier, mixer, limiter, FM/FSK demodulator with an external LC tank circuit or ceramic resonator, LPF amplifier, and a data slicer with clock recovery and an integrated data bit synchronizer. The received strength signal indicator (RSSI) can also be used for fast carrier sense on/off keyin...

74ABT2244CMSA

The integrated receiver is intended to be used as a single-conversion FSK/OOK receiver. It consists of a low noise amplifier, mixer, limiter, FM/FSK demodulator with an external LC tank circuit or ceramic resonator, LPF amplifier, and a data slicer with clock recovery and an integrated data bit synchronizer. The received strength signal indicator (RSSI) can also be used for fast carrier sense on/off keyin...

74ABT2244CMTC

Vendor:FSCPackage Cooled:TSSOPD/C:04+

74ABT2244CPC

The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information

74ABT2244CPC

The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information

74ABT2244CSC

Vendor:SMDPackage Cooled:8880D/C:05+

In actuality, if the ADCR is written to within 2.5 ADC_clock cycles, a new conversion is started but the DONE bit is not set. If the ADCR is written to after 2.5 ADC_clocks, but within a conversion time, the DONE bit is set within one ADC_clock and a new conversion is started.

74ABT2244CSC

Vendor:SMDPackage Cooled:8880D/C:05+

In actuality, if the ADCR is written to within 2.5 ADC_clock cycles, a new conversion is started but the DONE bit is not set. If the ADCR is written to after 2.5 ADC_clocks, but within a conversion time, the DONE bit is set within one ADC_clock and a new conversion is started.

74ABT2244CSCX

Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pull-ups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general-purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally bei...

74ABT2244CSJ

The SM320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The SM/SMJ320VC33 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a ...

74ABT2244CX

Vendor:NSPackage Cooled:2000

The Automatic Shut-Off is a safety system which turns off the electrical power of a load based either on a movement detection or a position detection. This detection will be taken into account after a well defined time delay. A typical application is the safety feature in irons which will switch off the heating element: if the iron is connected to the mains and left immobile in the ironing position for a ...

74ABT2244D112

74ABT2244DB

Vendor:PHIPackage Cooled:SSOPD/C:3000

The LTC ®3406B-2 is a high efficiency monolithic synchro- nous buck regulator using a constant frequency, current mode architecture. Supply current with no load is 350µA, dropping to <1µA in shutdown. The 2.5V to 5.5V input voltage range makes the LTC3406B-2 ideally suited for single Li-Ion battery-powered applications. 100% duty cycle capability provides low dropout operation, extend- ing...

74ABT2244N

Vendor:PHPackage Cooled:DIP-20PD/C:9640+

202 or CCITT V.23 FSK format and transmitted at 1200 baud from the serving end office to the subscribers terminal. Additionally in off-hook signalling, the special dual tone CAS is used to alert the terminal before FSK data transmission. BT uses CAS to alert the terminal prior to FSK in both on- hook (Idle State) and off-hook (Loop State) signalling.

74ABT2245

Vendor:PHILIPSPackage Cooled:SSOP

• High Performance 16-bit CPU with 5-Stage Pipeline C 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) C 1-Cycle Multiplication (16 16 bit), Background Division (32 / 16 bit) in 21 Cycles C 1-Cycle Multiply-and-Accumulate (MAC) Instructions C Enhanced Boolean Bit Manipulation Facilities C Zero-Cycle Jump Execution C Additional Instructions to Support HLL and Operatin...

74ABT2245D

Vendor:TID/C:N/A

External Data pins allow for In-System Programming of the device and setting of the EEPROM-based security bit. When the security bit is set (active) this programming con- nection will only respond to a device erase command. Data cannot be read out of the external programming/data pins when the security bit is set. The part can be re-pro- grammed, but only after first being erased.

74ABT2245DB

Vendor:PHILIPSPackage Cooled:01+D/C:792

The IDT5T905 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The IDT5T905 can act as a tra...

74ABT224-5DB

74ABT2245PW

Vendor:PHIPackage Cooled:TSSOPD/C:01+

The VHC164 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissi- pation. The VHC164 is a high-speed 8-Bit Serial-In/Paral- lel-Out Shift Register. Serial data is entered through a 2- input AND gate synchronous with the LOW-to-HIGH transi- tion of the...

74ABT2245PW

Vendor:PHIPackage Cooled:TSSOPD/C:01+

The VHC164 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissi- pation. The VHC164 is a high-speed 8-Bit Serial-In/Paral- lel-Out Shift Register. Serial data is entered through a 2- input AND gate synchronous with the LOW-to-HIGH transi- tion of the...

74ABT2400

SUMMARY High-Performance 32-Bit DSPApplications in Audio, Medical, Military, Graphics, Imaging, and Communication Super Harvard ArchitectureFour Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive, Zero-Overhead I/O Backwards-CompatibleAssembly Source Level Compatible with Code for ADSP-2106x DSPs Single-Instruction-Multiple-Data (SIMD) Computational ArchitectureTwo 32-Bi...

74ABT2401DBD

74ABT240A

Vendor:TIPackage Cooled:TSOP

AFEU processing begins after this shared session key is agreed upon. The plaintext message to be encrypted is logically partitioned into n sets of 8-bit blocks. In practice, the host processor groups 4 bytes at a time into 32-bit blocks and write that data to the AFEU. The AFEU internally processes each word one byte at a time. The AFEU engine processes each block in turn, byte by byte, producing n sets of ...

74ABT240ADBLE

Vendor:TI

Luma/Chroma Swap. Internally pulled-up. YCSWAP=0 indicates a luminance sample is the first sample following the leading edge of HSYNC*. YCSWAP=1 indicates a chroma sample (Cb or CR depending on CbSWAP) is the first sample following the leading edge of HSYNC*. See Figure 5 on page 7. Frequency Select. Internally pulled-up FS = 1 (default), then DCLK = 40.5 MHz, ACLK = 16.934 MHz FS = 0, then DCLK = 33.9 MHz,...

74ABT240ADBLE

Vendor:TI

Luma/Chroma Swap. Internally pulled-up. YCSWAP=0 indicates a luminance sample is the first sample following the leading edge of HSYNC*. YCSWAP=1 indicates a chroma sample (Cb or CR depending on CbSWAP) is the first sample following the leading edge of HSYNC*. See Figure 5 on page 7. Frequency Select. Internally pulled-up FS = 1 (default), then DCLK = 40.5 MHz, ACLK = 16.934 MHz FS = 0, then DCLK = 33.9 MHz,...

74ABT240AN

1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as listed below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q designators will not be included in the PIN and will not be marked on the device.

74ABT240C

Vendor:FAIRCHILDPackage Cooled:SMDD/C:03+

Each MMU provides read-only and supervisor-only protections on a page basis. Also, processes can be given isolated address spaces by assigning each a unique table structure and updating the root pointer upon a task swap. Isolated address spaces pro- tect the integrity of independent processes.

74ABT240CMSA

Vendor:ＦＡＩＲＣＨＩＬＤ

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

74ABT240CMSA

Vendor:ＦＡＩＲＣＨＩＬＤ

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

74ABT240CMSAX

Vendor:ＦＡＩＲＣＨＩＬＤ

This document contains information on a product under development at Advanced Micro Devices. The information is in- tended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

74ABT240CMTC

Vendor:FSCPackage Cooled:TSSOPD/C:03

G.703 2048kHz Synchronization Interface Compliant G.703 64kHz Centralized (Option A) and Codirectional Timing Interface Compliant G.703 Appendix II 64kHz and 6312kHz Japanese Synchronization Interface Compliant Interfaces to Standard T1/J1 (1.544MHz) and E1 (2.048MHz) Interface to CMI-Coded T1/J1 and E1 Short- and Long-Haul Line Interface Transmit and Receive T1 and E1 SSM Messages with Message Validati...

74ABT240CSC

Vendor:FSCPackage Cooled:1980D/C:N/A

This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

74ABT240CSCX

Package Cooled:02D/C:1000

• HiPerFET TM technology C low RDSon C unclamped inductive switching (UIS) capability C dv/dt ruggedness C fast intrinsic reverse diode C low gate charge • thermistor for internal temperature measurement • package C low inductive current path C screw connection to high current main terminals C use of non interchangeable connectors for auxiliary terminals possible C ...

74ABT240CSCX_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

74ABT240CSJ

Vendor:Fairchild

Data Input/Outputs (DQ0-DQ7). The input is data to be programmed in the memory array or a com- mand to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the E...

74ABT240CSJX

D/C:97

This family is a 1M bit dynamic RAM organized 1,048,576 x 1-bit configuration with Fast Page mode CMOS DRAMs. Fast Page mode offers high speed of random access memory within the same row. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70 or 80ns) and power consumption (Normal or Low power). Hyundais advanced circuit...

74ABT240CSJX

D/C:97

This family is a 1M bit dynamic RAM organized 1,048,576 x 1-bit configuration with Fast Page mode CMOS DRAMs. Fast Page mode offers high speed of random access memory within the same row. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70 or 80ns) and power consumption (Normal or Low power). Hyundais advanced circuit...