74AHC374PW.118

Vendor:PHAPackage Cooled:122,500

135-mΩ -Maximum (5-V Input) High-Side MOSFET Switch 250 mA Continuous Current per Channel Independent Short-Circuit and Thermal Protection With Overcurrent Logic Output Operating Range . . . 2.7-V to 5.5-V Logic-Level Enable Input 2.5-ms Typical Rise Time Undervoltage Lockout 10 µA Maximum Standby Supply Current Bidirectional Switch Available in 8-pin SOIC and PDIP Packages Ambient Temperatu...

74AHC377

Vendor:PHILIPSD/C:00

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. (2) All typical values are at 25C and with a 3.3-V supply voltage. (3) HP4194A impedance analyzer (or equivalent)

74AHC377PW

This table shows the Phase Output state versus the state of the Hall-Effect and Direction Inputs. Please note that the Hall-Effect Inputs are Grey-encoded; that is, only one input is allowed to change from one input state to another at a tm.ie

74AHC377PW

This table shows the Phase Output state versus the state of the Hall-Effect and Direction Inputs. Please note that the Hall-Effect Inputs are Grey-encoded; that is, only one input is allowed to change from one input state to another at a tm.ie

74AHC3G04DC

Vendor:PHIPackage Cooled:SOT765D/C:2006+

Delay(Pin 5): PMOS switch delay control pin. See Operation section for setting the delay time. The delay time begins when the output voltage of the DC/DC switching regulator reaches 85% of its true output voltage. This corresponds to a FB voltage of about 1.1V. The PMOS switch is controlled with both the delay time and the switch control pin, SWC. If no Cdelay capacitor is used, the PMOS switch is con...

74AHC3G04DP

Vendor:PHIPackage Cooled:SOT505-2D/C:2006+

Operating and Storage temperature: -65ºC to +175ºC Thermal Resistance: 150ºC/W junction to end cap and 300ºC/W junction to ambient when mounted on FR4 PC board (1 oz Cu) with recommended footprint (see last page) Steady-State Power: 0.5 watts at end cap temperature TEC < 100oC or ambient temperature TA < 25ºC when mounted on FR4 PC board as described for thermal resistanc...

74AHC3GU04DP

Vendor:PHIPackage Cooled:SOT505-2D/C:2006+

The MIC5306 is a micropower, µCap low dropout regulator designed for optimal performance in a small space. It is capable of sourcing 150mA of output current and only draws 16µA of operating current. This high performance LDO offers fast transient response and good PSRR while consuming a minimum of current.

74AHC541D.118

Vendor:NXPD/C:08+

74AHC541D-T

Vendor:PHILIPSD/C:6+

PWM With Tri-State Enable 12-V Low-Side Gate Drive (SiP41109) 8-V Low-Side Gate Drive (SiP41110) Undervoltage Lockout Internal Bootstrap Diode Switching Frequency Up to 1 MHz 30-ns Max Propagation Delay Drive MOSFETs In 5- to 48-V Systems Adaptive Shoot-Through Protection

74AHC541DW

Vendor:TIPackage Cooled:ORG PACKINGD/C:08+

• Up to 10 MIPs operation: - DC - 40 MHz osc./clock input - 4 MHz - 10 MHz osc./clock input with PLL active • 16-bit wide instructions, 8-bit wide data path • Priority levels for interrupts • 8 x 8 Single Cycle Hardware Multiplier

74AHC541DW

Vendor:TIPackage Cooled:ORG PACKINGD/C:08+

• Up to 10 MIPs operation: - DC - 40 MHz osc./clock input - 4 MHz - 10 MHz osc./clock input with PLL active • 16-bit wide instructions, 8-bit wide data path • Priority levels for interrupts • 8 x 8 Single Cycle Hardware Multiplier

74AHC541PW.118

Vendor:NXPD/C:08+

SHORT-CIRCUITS Some amplifier applications must be designed to survive a short-circuit to ground. This forces the full power supply voltage (either V+ or VC) across the conducting output transistor. The amplifier will immediately go into current limit. To survive this condition a power op amp with adjustable current limit must be set to limit at a safe level.

74AHC573

Vendor:PHILIPSD/C:0050+/0111

Note 10: Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster than 0.5 V/ns, measured between 1.3V and 1.8V (approximately 20% to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5Ω tied to +2.1V DC.

74AHC573D

Vendor:PHIPackage Cooled:SOP20WD/C:2007+

For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-06043 Rev. *ARevised December 27, 2002

74AHC573PW

Vendor:PHIPackage Cooled:TSSOPD/C:05+

The deflection amplifier circuit of Figure 1 achieves arbitrary beam positioning for a fast heads-up display. Maximum tran- sition times are 4µs while delivering 2A pk currents to the 13mH coil. The key to this circuit is the sense resistor (RS) which converts yoke current to voltage for op amp feedback. This negative feedback forces the coil current to stay exactly proportional to the control v...

74AHC573PW.118

Vendor:NXP/PhilipsD/C:07+

• 3.3V LOW VOLTAGE, ZERO POWER OPERATION JEDEC Compatible 3.3V Interface Standard Interfaces with Standard 5V TTL Devices 50µA Typical Standby Current (100µA Max.) 45mA Typical Active Current (55mA Max.) Dedicated Power-down Pin

74AHC574D

Package Cooled:2000

The 74AHC574D is a highly integrated laser diode bias controller which incorporates two digitally controlled Programmable Current Generators, temperature compensation with dedicated look-up tables, and supplementary EEPROM array. All functions of the device are controlled via a 2-wire digital serial interface.

74AHC574D.118

Vendor:SOPPackage Cooled:14000D/C:PHI

In addition to being backwards compatible with the F2MC* family architecture, the instruction set has been ex- panded to add support for high-level language instructions, expanded addressing mode, and enhanced multiply/ divide and bit processing instructions. A 32-bit accumulator is also provided, making it possible to process long word (32-bit) data.

74AHC574DW

Note 2: All currents into device pins are positive, all currents out of device pins are negative, and all voltages are referenced to GND, unless otherwise noted. Note 3: All specifications are 100% tested at TA = +25C, unless otherwise noted. Specifications over -40C to +85C are guaran- teed by characterization. Note 4: This is the delay time from a valid on condition until VGS begins rising. Valid on cond...

74AHC574PW

Vendor:PHI

HIGH SPEED: tPD = 5.3 ns (TYP.) at VCC = 3V 5V TOLERANT INPUT LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25C INPUT VOLTAGE LEVEL : VIL= 0.8, VIH=2V AT VCC=3V POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) IMPROVED LAT...

74AHC595D118

Vendor:PHILIPSD/C:O9+

The NE251 is a dual gate GaAs FET designed to provide flexibility in its application as a mixer, AGC amplifier, or low noise amplifier. As an example, by shorting the second gate to the source, higher gain can be realized than with single gate MESFETs. This device is available in a mini-mold (surface mount) package.

74AHC595PW118

Use with 10 to 14-bit A/D converters 5 Megapixels/second minimum throughput (14 bits) 2.5V input/output ranges, Gain = C1 Low noise, 200µVrms Two independent S/H amplifiers Gain matching between S/H's Offset adjustments for each S/H Four external A/D control lines Small package, 24-pin ceramic DDIP Low power, 350mW Low cost

74AHC74DR

Vendor:TIPackage Cooled:69500D/C:07+

Note 1: Tested at VDD = +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: Offset nulled. Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 5: Resistance measured from the source to drain of the switch. Note 6: ADC p...

74AHC74DR

Vendor:TIPackage Cooled:69500D/C:07+

Note 1: Tested at VDD = +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: Offset nulled. Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 5: Resistance measured from the source to drain of the switch. Note 6: ADC p...

74AHC74D-T

Vendor:ＮＸＰ

74AHC74PW

Vendor:PHIPackage Cooled:TSSOP-14D/C:2002

The Programmable Interconnect Matrix (PIM) consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting and density limitations.

74AHC74PW.118

Vendor:PHAPackage Cooled:22,500

Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than 25 ppm).

74AHC74PW118

Vendor:PHILIPS

This series of hermetic packaged MOSFETs are ideally suited for low voltage applications; battery powered voltage power supplies, motor controls, dc to dc converters and synchronous rectification. The low conduction loss allows smaller heat sinking and the low gate change simpler drive circuitry.

74AHC74PWR

Vendor:TIPackage Cooled:TSSOPD/C:506;336

Each device requires only a single 3.0 volt power supply for read, program, and erase functions. Inter- nally generated and regulated voltages are provided for program and erase operations. A VCCQ pin is pro- vided to allow 5 volts to be applied to the output buffer logic. With 5 volt tolerant inputs, the VCCQ pin provides the Flash device with 5 volt tolerant I/O.

74AHC823DB(AB823)

Vendor:TI

2.7V to 3.6V on A-port and 4.5V to 5.5V on B-port TTL Compatible Inputs Latch-up performance exceeds 200mA Per JESD78 ESD protection exceeds JESD22 2000V Human-Body Model (A114-B) 200V Machine Model (A115-A) • Industrial Temperature: C40C to +85C • Available Packages: 24-pin 173-mil wide plastic TSSOP (L) 24-pin 150-mil wide plastic QSOP (Q) 24-pin 300-mil wide plastic SOIC (S)

74AHC823DB(AB823)

Vendor:TI

2.7V to 3.6V on A-port and 4.5V to 5.5V on B-port TTL Compatible Inputs Latch-up performance exceeds 200mA Per JESD78 ESD protection exceeds JESD22 2000V Human-Body Model (A114-B) 200V Machine Model (A115-A) • Industrial Temperature: C40C to +85C • Available Packages: 24-pin 173-mil wide plastic TSSOP (L) 24-pin 150-mil wide plastic QSOP (Q) 24-pin 300-mil wide plastic SOIC (S)

74AHC86

Vendor:TIPackage Cooled:SOP14D/C:*

s Meets or exceeds the requirements of ANSI TIA/EIA-644 Standard s Low-Voltage Differential Signaling with output voltage of 350 mV across a 50 Ω load or 700 mV across a 100 Ω load s 200 ps maximum channel-to-channel output skew s 600 ps typical output voltage rise and fall times s Driver at high impedance when disabled or with VCC = 0 V s 5 volt tolerant inputs with Low Voltage TTL (LVTTL)...

74AHC86APW

Vendor:PHILIPSPackage Cooled:TSSOPD/C:06+/07+PB-FREE

This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the op amps to...

74AHC86D

Vendor:NXPPackage Cooled:SOP14D/C:0822

Dimensions InchesMillimeters MinMaxMinMax .305.3357.758.51 .240.2606.126.60 .335.3708.519.40 .200 TP5.08 TP .016.0190.410.48 0.500 0.75012.719.0 .016.0190.410.48 .0501.27 .2506.35 .1002.54 .0300.76 .029.0450.741.14 .028.0340.710.86 .0100.25 45 TP45 TP

74AHC86PW

Vendor:TIPackage Cooled:TSSOPD/C:99

Notes: 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 7. Outputs driving 50Ω transmission lines. 8. 50% input duty cycle. 9. Outputs loaded with 30 pF each. 10. Part-to-Part Skew at a given temperature and voltage. 11. Set-up and Hold times are relative to the falling edge of the input clock.

74AHC86PW-T

Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State

74AHCIG08

Vendor:NXPPackage Cooled:N/AD/C:35

Power Amplifier* Output power into 50Ω load, high power mode (TX_P_CNT=0V) Output power into 50Ω load, low power mode (TX_P_CNT=VDD) Voltage Gain (internal) Output impedance (after combiner) Output 1dB compression point Output spurious suppression

74AHCT00D

Vendor:PHID/C:O9+

SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time LDAC Pulsewidth SCLK Falling Edge to LDAC Rising Edge SCLK Falling Edge to LDAC Falling Edge

74AHCT00D118

This is the inverting input of the transmit gain setting op- erational amplifier. Gain setting resistors are usually con- nected from this pin to TG and from this pin to the analog signal source. The common mode range of the TI+ and TIC pins is from 1.2 V to VDD C 1.2 V. This is an FET gate input. The TIC pin also serves as one of the transmit input multi- plexer pins when the TI+ pin is connected to...

74AHCT00N

ECOS1EA472AA ECOS1EA562AA ECOS1EA682AA ECOS1EA222BL ECOS1EA222BA ECOS1EA332BA ECOS1EA472BA ECOS1EA562BA ECOS1EA682BA ECOS1EA822BA ECOS1EA103BA ECOS1EA123BA ECOS1EA332CL ECOS1EA682CA ECOS1EA822CA ECOS1EA103CA ECOS1EA123CA ECOS1EA153CA ECOS1EA183CA ECOS1EA472DL ECOS1EA822DA ECOS1EA103DA ECOS1EA123DA ECOS1EA153DA ECOS1EA183DA ECOS1EA223DA ECOS1EA682EL ECOS1EA123EA ECOS1EA153EA ECOS1EA183EA...

74AHCT00PW-T

74AHCT02

Vendor:246Package Cooled:99/00+D/C:TSSOP14

While first-generation deep- memory scopes update the display slowly, Infiniiums MegaZoom memory management system instantaneously updates the display even with the deepest memory. And deep memory is on all the time so you always have the maximum available sample rate and dont undersample or miss fast events. Discover prob- lems you never found with your first-generation deep-memory scope.

74AHCT02D

Vendor:PHIPackage Cooled:SOP14SD/C:508

A key component that follows the limiting amplifier in a receiver unit is the clock and data recovery (CDR) circuit. The CDR performs timing and amplitude-level decisions on the incoming signal, which leads to a time- and amplitude-regenerated data stream. First to be recovered from the received signal is the clock. Several possibilities can support this clock- recovery function (external SAW filter, extern...

74AHCT02D

Vendor:PHIPackage Cooled:SOP14SD/C:508

A key component that follows the limiting amplifier in a receiver unit is the clock and data recovery (CDR) circuit. The CDR performs timing and amplitude-level decisions on the incoming signal, which leads to a time- and amplitude-regenerated data stream. First to be recovered from the received signal is the clock. Several possibilities can support this clock- recovery function (external SAW filter, extern...

74AHCT02PW

Vendor:PHID/C:0619+

Because of the large dynamic range for load current, a selectable gain amplifier is used to match the current range to the range of the ADC. The gain is controlled by summing the current for 2½ cycles of the supply frequency. If the value exceeds an equivalent of 3A, the amplifiers gain is switched to low. If the value falls below an equivalent of 2.8A, the gain is switched to high. The small ...

74AHCT02PW.118

• High current transition frequency fT=9.0 GHz(Typ.) @VCE=6V, IC=15mA • Low Noise Figure NFmin=1.4dB(Typ.) @1.0 GHz, VCE=8V, IC=3mA • Maximum Stable Gain(MSG)=19dB @1.0 GHz, VCE=6V, IC=10mA • Output third order intercept output(IP3)=29dBm @ 1.0 GHz,VCE=6V, IC=10mA

74AHCT02PWLE

Referenced to VCCA Voltage VCC Isolation Feature − If Either VCC Input Is at GND, All I/O Ports Are in the High-Impedance State Ioff Supports Partial-Power-Down Mode Operation Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range I/Os Are 4.6-V Tolerant

74AHCT02PWR

74AHCT04

the transmitted frequency to exceed its 0 01% tolerance The frequency marked on the crystal is usually measured with a fixed shunt capacitance (CL) that is specified in the crystals data sheet This capacitance for 20 MHz crystals is typically 20 pF The capacitance between the X1 and X2 pins of the SNI of the PC board traces and the plated through holes plus any stray capacitance such as the sock- et ca...

74AHCT04D118

Vendor:NXPPackage Cooled:N/AD/C:08+

AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) CMOS Rail-To-Rail Input/Output Input Bias Current . . . 2.5 pA Low Supply Current . . . 600 µA/Channel Gain-Bandwidth Product . . . 2.8 MHz

74AHCT04D-118

Vendor:PHILIPSPackage Cooled:SO-14D/C:08+

The 74AHCT04D-118 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced, and Stratum 4 and ETSI ETS 300 011 interfaces. It will meet the jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range, phase change slope frequency and MTIE requirements for these specifications.

74AHCT04N

Vendor:SAMSUNGPackage Cooled:1998D/C:DIP

As indicated in the diagram, capacitors C1 and C2 deter- mine the treble component cutoff frequency. By varying the values of these components, the frequency charac- teristic can be changed as indicated by the dotted line in the diagram. This varies the balance of the harmonic component, and is an important factor in determining the tone quality.

74AHCT04PW118

This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is HIGH, each channel may still be put into high-impedance by software control. This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CCO bit in the Connection Memory HIGH locations. This input (active LOW) puts the IDT72V8985 i...

74AHCT04PW-118

Vendor:PHILIPSPackage Cooled:TSSOP-14D/C:08+

PORT I is an 8-bit Hi-Z input port The 28-pin device does not have a full complement of PORT I pins The unavailable pins are not terminated i e they are floating A read opera- tion for these unterminated pins will return unpredictable values The user must ensure that the software takes this into account by either masking or restricting the accesses to bit operations The unterminated PORT I pins will dr...

74AHCT04PW-T

Since IAdj is controlled to less than 100 µA, the error associated with this term is negligible in most applications A common ground is required between the input and the output voltages. The input voltage must remain typically 2.0V above the output voltage even during the low point on the Input ripple voltage. * = Cin is required if regulator is located an appreciable distance from power supply f...

74AHCT04S

Package Cooled:SMD14D/C:02+

NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303C675C2175 or 800C344C3860 Toll Free USA/Canada Fax: 303C675C2176 or 800C344C3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303C675C2167 or 800C344C3810 Toll Free USA/Canada

74AHCT08

Vendor:TID/C:SOP/14

The external bus interface (EBI) provides a glueless interface to 8 and 16-bit asynchronous Flash EE- PROM, 16 bit SDRAM devices and to slave devices with an i960-like 16 bit bus interface with multiplexed address and data (as available on DynaMiTe chips).

74AHCT08D118

Vendor:PHILIPSD/C:O9+

- Added part ID for 3L00M maskset. - Added cycle definition to CPU 12 Block Description. - Diagram Clock Connections: Connected Bus Clock to HCS12 Core. - Corrected Background Debug Module to HCS12 Breakpoint at address $0028 - $002F in table 1-1. - Corrected Blank Check Time Flash value in table NVM Timing Characteristics - Added EXTAL pin VIH, VIL and EXTAL pin hysteresis value to Oscillator ...

74AHCT08PW118

Some care must be used in interpreting the numbers in this table. Philips Semiconductors feels strongly that the specifications set forth in a data sheet should reflect as accurately as possible the operation of the part in an actual system. In particular, the input threshold values of VIH and VIL can be tested by the user with parametric test equipment … if VIH and VIL are applied to the inputs, ...

74AHCT08PWE

Vendor:TID/C:06+

DIMMING Dimming can be accomplished both with current amplitude control (changing the RSET resistor value) with a PWM signal (toggling the DIG_DIM input) or both. Current between the ISET+ and ISET- pins may be varied for current amplitude dimming. If a mechanical input is needed, a rheostat in series with a resistor connected from ISET+ to ISET- can be used.:

74AHCT08PWE

Vendor:TID/C:06+

DIMMING Dimming can be accomplished both with current amplitude control (changing the RSET resistor value) with a PWM signal (toggling the DIG_DIM input) or both. Current between the ISET+ and ISET- pins may be varied for current amplitude dimming. If a mechanical input is needed, a rheostat in series with a resistor connected from ISET+ to ISET- can be used.:

74AHCT08PWR

Vendor:2500

The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. With a 16 MHz crystal, 58% of the instructions are executed in 0.75 µs and 40% in 1.5 µs. Multiply and divide instructions require 3 µs.

74AHCT08S

Package Cooled:SMD14D/C:02+

Introduction The IRU1261 is a dual fixed output Low Dropout (LDO) regulator available in a 5-pin TO-220 or TO-263 pack- ages. This voltage regulator is designed specifically for PentiumII processor applications requiring 2.5V and 1.5V supplies, eliminating the need for a second regulator re- sulting in lower overall system cost. The IRU1261 is de- signed to take advantage of 5V supply to provide the drive f...

74AHCT109J

Vendor:散新Package Cooled:CDIP

74AHCT123AD

RF output and bias pin. Biasing is accomplished with an external series resistor and choke inductor to VCC. The resistor is selected to set the DC current into this pin to a desired level. The resistor value is deter- mined by the following equation:

74AHCT125

Vendor:PHILIPSPackage Cooled:08+D/C:5000

The Spartan™ and the Spartan-XL families are a high-vol- ume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume, approach and in many cases are equivalent to mask pro- grammed ASIC devices.

74AHCT125D

Vendor:PHIPackage Cooled:SOPD/C:04+

such as a gaussian, or a rectangular pulse then the odd nature of (t-t0) will force < f'(t0) (t-t0), > = 0. Now in order to determine the error generated by the non-zero sampling time we must consider the next term in the Taylor series expansion.

74AHCT125D118

Vendor:NXPPackage Cooled:N/AD/C:08+

This MOSFET is an enhancement-mode silicon-gate power field effect transistor of the vertical DMOS (VDMOS) structure. It is specifically designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, power distribution, motor drives and relay drivers as well as other power control and co...

74AHCT125D118

Vendor:NXPPackage Cooled:N/AD/C:08+

This MOSFET is an enhancement-mode silicon-gate power field effect transistor of the vertical DMOS (VDMOS) structure. It is specifically designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, power distribution, motor drives and relay drivers as well as other power control and co...

74AHCT125PW-118

Vendor:PHILIPSPackage Cooled:TSSOP-14D/C:08+

B. Failure Rate Prediction The failure rate will depend on the junction temperature of the device. The estimated life at different temperatures is calcu- lated, using the Arrhenius plot with activation energy of 1.05 eV, and listed in the following table.

74AHCT125PW-T

Vendor:ＮＸＰ

Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.

74AHCT126

Vendor:150Package Cooled:99/00+D/C:TSSOP14

Note 1: Exceeding the absolute maximum rating may damage the device. Note 2: The device is not guaranteed to function outside its operating rating. Note 3: Off is 0.8V and on is 2.4V for the GM2526-H. Off is 2.4V and on is The enable input has approximately 200mV of hysteresis.

74AHCT126D

n Offset register allows sensing a variety of thermal diodes accurately n On-board local temperature sensing n 10 bit plus sign remote diode temperature data format, 0.125 ˚C resolution n T_CRIT_A output useful for system shutdown n ALERT output supports SMBus 2.0 protocol n SMBus 2.0 compatible interface, supports TIMEOUT n 8-pin MSOP and SOIC packages

74AHCT126DR

74AHCT126N

For example, if the OTG Host were to turn off VBUS, and the USB20H04 were configured in self-powered mode, downstream ports would remain powered. The downstream devices would then go into a suspend state based on inactivity. In the event that one of the downstream devices needed to communicate with the OTG Host, the downstream device would signal a standard USB resume to the Hub, and the Hub would then commun...

74AHCT126PW118

Notes: 1. See test circuit and waveforms. 2. This parameter is guaranteed but not tested on Propagation Delays. 3. The bus switch contributes no propagational delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.25ns for 50pF load. Since this time constant is much smaller than the rise/fall times of typical...

74AHCT132PW

Vendor:PHIPackage Cooled:TSOP-14D/C:1999

If an ADJ-bypass capacitor is use, the amplitude of the output ripple will be independent of the output voltage. If an ADJ- bypass capacitor is not used, the output ripple will be proportional to the ratio of the output voltage to the reference voltage: M = VOUT / VREF Where M = multiplier for the ripple seen when the ADJ pin is optimally bypassed. VREF = Reference Voltage

74AHCT138

Vendor:TI

1. Mounted onto a 2 square FR−4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), t < 10 seconds. 2. Mounted onto a 2 square FR−4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), t = steady state. 3. Minimum FR−4 or G−10 PCB, t = steady state. 4. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.

74AHCT138

Vendor:TI

1. Mounted onto a 2 square FR−4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), t < 10 seconds. 2. Mounted onto a 2 square FR−4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), t = steady state. 3. Minimum FR−4 or G−10 PCB, t = steady state. 4. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.

74AHCT138D

Vendor:PHIPackage Cooled:SOP-3.9/16PD/C:03+

The DS40MB200 is a dual signal conditioning 2:1 multi- plexer and 1:2 fan-out buffer designed for use in backplane redundancy applications. Signal conditioning features in- clude input equalization and programmable output pre- emphasis that enable data communication in FR4 back- planes up to 4 Gb/s. Each input stage has a fixed equalizer to reduce ISI distortion from board traces. All output drivers h...

74AHCT138D

Vendor:PHIPackage Cooled:SOP-3.9/16PD/C:03+

The DS40MB200 is a dual signal conditioning 2:1 multi- plexer and 1:2 fan-out buffer designed for use in backplane redundancy applications. Signal conditioning features in- clude input equalization and programmable output pre- emphasis that enable data communication in FR4 back- planes up to 4 Gb/s. Each input stage has a fixed equalizer to reduce ISI distortion from board traces. All output drivers h...

74AHCT138DGVR

Vendor:SOPD/C:99+

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). Port 2 emits the high order address byte during fetches from external pro- gram memory ...

74AHCT138DGVR

Vendor:SOPD/C:99+

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). Port 2 emits the high order address byte during fetches from external pro- gram memory ...

74AHCT138N

Schmitt trigger inputs on Port G MICROWIRE PLUS serial I O Packages 44 PLCC OTP Emulates COP880C 36 I O pins 40 DIP OTP Emulates COP880C 36 I O pins 28 DIP OTP Emulates COP820C 840C 881C 24 I O pins 20 DIP OTP Emulates COP822C 842C 16 I O pins 28 SO 20 SO OTP 44 LDCC UV Erasable 40 CERDIP 28 CERDIP 20 CERDIP UV Erasable

74AHCT139D

n Deserializes one to six Bus LVDS input serial data streams with embedded clocks n IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test modes n Parallel clock rate 16-66MHz n On chip filtering for PLL n High impedance inputs upon power off (Vcc = 0V) n Single power supply at +3.3V n 196-pin LBGA package (Low-profile Ball Grid Array) package n Industrial temperature range operation: −40...

74AHCT139PW

ECOS2CA221AA ECOS2CA271AA ECOS2CA331AA ECOS2CA391AA ECOS2CA151BL ECOS2CA151BA ECOS2CA221BA ECOS2CA271BA ECOS2CA331BA ECOS2CA391BA ECOS2CA471BA ECOS2CA561BA ECOS2CA681BA ECOS2CA221CL ECOS2CA391CA ECOS2CA471CA ECOS2CA561CA ECOS2CA681CA ECOS2CA821CA ECOS2CA102CA ECOS2CA122CA ECOS2CA331DL ECOS2CA561DA ECOS2CA681DA ECOS2CA821DA ECOS2CA102DA ECOS2CA122DA ECOS2CA152DA ECOS2CA182DA ECOS2CA471EL...

74AHCT139PW118

No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable to the publication date of this document. However, VIA Technologies assumes no responsibility f...

74AHCT14D.118

Vendor:NXP/PhilipsD/C:07+

74AHCT14DR

Vendor:TID/C:06+

Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 200 to 400 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscil...

74AHCT14DR

Vendor:TID/C:06+

Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 200 to 400 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscil...

74AHCT14D-T

• 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 270MHz • Very low skew: 40ps • Very low jitter: 40ps • 1.8V AVDD and 1.8V VDDQ • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode •...

74AHCT14PW.118

Phase adjustment is available to adjust the relative sampling of the converter halves for optimizing convert- er performance. Input clock phasing is also available for interleaving several MAX101s for higher effective sampling rates.

74AHCT14PW.118

Phase adjustment is available to adjust the relative sampling of the converter halves for optimizing convert- er performance. Input clock phasing is also available for interleaving several MAX101s for higher effective sampling rates.

74AHCT14PWR

Vendor:TID/C:06+

The MAX2531 multiband LNA/Mixer IC is optimized for CDMA, GSM, and TDMA applications in cellular band. The MAX2531 IC features a GPS LNA/mixer signal path for E911 and Traveler Assistance applications. The cellular signal can be routed to either IF port. For example, one IF port can be connected to an IF filter with 30kHz band-width, while the other port can drive an IF filter with a wider bandwidth. The G...

74AHCT14PWR

Vendor:TID/C:06+

The MAX2531 multiband LNA/Mixer IC is optimized for CDMA, GSM, and TDMA applications in cellular band. The MAX2531 IC features a GPS LNA/mixer signal path for E911 and Traveler Assistance applications. The cellular signal can be routed to either IF port. For example, one IF port can be connected to an IF filter with 30kHz band-width, while the other port can drive an IF filter with a wider bandwidth. The G...

74AHCT14PWR(HB14)

Vendor:TIPackage Cooled:TSSOPD/C:02+

NOTES: 1Full Scale Range (FSR) is 10V for unipolar mode. 2Guaranteed but not production tested. 3Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4See timing diagram. 5Specified values guarantee functionality. Refer to other parameters for accuracy.

74AHCT157

Vendor:stockPackage Cooled:FAIRD/C:00+

74AHCT157PW

Very Low Dropout Voltage Guaranteed 150mA Output Accurate to within 3% 30µA Quiescent Current Over-Temperature Shutdown Current Limiting Short Circuit Current Fold-back Power Good Output Function Power-Saving Shutdown Mode Space-Saving SOT-25 (SOT-23-5) Low Temperature Coefficient

74AHCT157PW

Very Low Dropout Voltage Guaranteed 150mA Output Accurate to within 3% 30µA Quiescent Current Over-Temperature Shutdown Current Limiting Short Circuit Current Fold-back Power Good Output Function Power-Saving Shutdown Mode Space-Saving SOT-25 (SOT-23-5) Low Temperature Coefficient

74AHCT157PW118

ABA-31563 is fabricated using Agilents HP25 silicon bipolar process, which employs a double- diffused single polysilicon process with self-aligned submi- cron emitter geometry. The process is capable of simulta- neous high fT and high NPN breakdown (25 GHz fT at 6V BVCEO). The process utilizes industry standard device oxide isolation technologies and submicron aluminum multilayer interconnect to achiev...