74ALVCH16245DL

Vendor:PHILIPSD/C:2006

Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Companys quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volat...

74ALVCH16245DT

Vendor:PHILIPSPackage Cooled:TSSOPD/C:1997

• VDD : 2.5V 0.2V, VDDQ : 2.5V 0.2V for DDR266, 333 • VDD : 2.6V 0.1V, VDDQ : 2.6V 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency : DDR266(2, 2.5...

74ALVCH16245PF

Vendor:IDTPackage Cooled:02+D/C:TSSOP-

• Pin compatible with bipolar FAST™ Series at a higher speed and lower power consumption • TTL input and output levels • Low ground bounce outputs • Extremely low static power • Hysteresis on all inputs • Industrial operating temperature range: C40C to +85C • Packaging (Pb-free & Green available): C 20-pin 173-mil wide plastic TSSOP (L) C 20-pin...

74ALVCH162525

Vendor:TIPackage Cooled:TSSOP

Circuit Board Material: .014 Getek, 4 - layer, 1 oz copper, Microstrip line details: width = .026, spacing = .026 The silk screen markers A, B, C, etc. and 1, 2, 3, etc. are used as placemarkers for the input and output tuning Shunt capacitors C C8 and C9. The markers and vias are spaced in .050 increments.

74ALVCH162525

Vendor:TIPackage Cooled:TSSOP

Circuit Board Material: .014 Getek, 4 - layer, 1 oz copper, Microstrip line details: width = .026, spacing = .026 The silk screen markers A, B, C, etc. and 1, 2, 3, etc. are used as placemarkers for the input and output tuning Shunt capacitors C C8 and C9. The markers and vias are spaced in .050 increments.

74ALVCH162601DGG

Vendor:PHIPackage Cooled:TSSOP/56D/C:01+

Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. Th...

74ALVCH16260PA

Vendor:IDTPackage Cooled:NULLD/C:NULL

To program a Leading Edge Blanking period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and the internal 10k resistor will determine the blanked interval. The 10k resistor has a 10% tolerance. For more accuracy, an external 2k 1% resistor, R, can be added, resulting in an equivalent resistance of 1.66k with a tolerance of 2.4%. The design equation is:

74ALVCH16260PV

Vendor:IDTPackage Cooled:SSOP-7.2-56PD/C:6+

Analog RGB-output 41 latin script languages 12 10 character size Parallel display attributes 64 from 4096 colors selectable Enhanced flash modes Dynamically redefinable character set (DRCS, PCS) Pixel graphics Fullscreen display (64 32 or 80 24 character positions) Horizontal and vertical scrolling Graphic cursors 4:3 and 16:9 display Multinorm display (50/60/100/120 Hz)

74ALVCH16270PV

Vendor:IDTPackage Cooled:SSOP-7.2-56PD/C:6+

(1) Electrical characteristics for "L" suffix devices are identical to their corresponding "non-L" suffix devices. (2) Derate linearly 5.71 mW/C for TA > +25C. (3) Derate linearly 3.08 mW/C for TA > +25C, 2N3501UB.

74ALVCH162721GRE4

74ALVCH162721PA

Vendor:IDTPackage Cooled:TSSOP-56D/C:2001+

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. 2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the...

74ALVCH162820PA

Vendor:IDTPackage Cooled:TSSOP

VCC IOUT Short Circuit protected to ground. Maximum reliability is obtained if IOUT does not exceed: Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering 10 sec) ESD (human body model)

74ALVCH162827

Vendor:TIPackage Cooled:TSSOP

The sensor consists of a precision linear Hall IC, which is optimized to an internal magnetic circuit to increase device sensitivity. The combination of a precisely controlled self-aligning assembly process (patents pending), and the factory pro- grammed precision of the linear Hall sensor, result in high-level performance and product uniformity.

74ALVCH162827PV

Vendor:IDTPackage Cooled:SSOP-7.2-56PD/C:6+

The UPC2753GR is a frequency converter manufactured with the NESAT III process. This product consists of an RF input amplifier, Gilbert cell mixer, LO input buffer, IF amplifier with AGC, external filter port, and IF output limiting amplifier. This device was specifically designed for low cost GPS recievers, mobile radios, and PCN applications.

74ALVCH162827PV

Vendor:IDTPackage Cooled:SSOP-7.2-56PD/C:6+

The UPC2753GR is a frequency converter manufactured with the NESAT III process. This product consists of an RF input amplifier, Gilbert cell mixer, LO input buffer, IF amplifier with AGC, external filter port, and IF output limiting amplifier. This device was specifically designed for low cost GPS recievers, mobile radios, and PCN applications.

74ALVCH162835

Vendor:28Package Cooled:99/00+D/C:TSOP56

This device set, along with the supporting firmware and evaluation system, comprises a complete facsimile machineneeding only power supply, scanner, and printer mechanism components to complete the machine. A system-level block diagram is shown in Figure 1.

74ALVCH162836PA

Vendor:IDTPackage Cooled:TSSOP

Provide a well decoupled 5V bias supply for the IC to this pin. This pin also provides the gate bias charge for the lower MOSFET controlled by the PWM section of the IC, as well as the base current drive for the linear regulators external bipolar transistors. The voltage at this pin is monitored for Power-On Reset (POR) purposes.

74ALVCH16334PA

Vendor:IDTPackage Cooled:02+D/C:TSSOP48

The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. Because the internal flip-flop is clocked on the falling edge of the input clock, all associated specification limits are referenced to the ne...

74ALVCH16334PV

Vendor:IDTPackage Cooled:SSOP

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC-VAC, Post Office Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

74ALVCH16344A

Vendor:TSSOP-56Package Cooled:.D/C:04+

The CMOS bq3285E/L is a low- power microprocessor peripheral providing a time-of-day clock and 100-year calendar with alarm fea- tures and battery operation. The bq3285L supports 3V systems. Other bq3285E/L features include three maskable interrupt sources, square-wave output, and 242 bytes of general nonvolatile storage.

74ALVCH16344PA

Vendor:IDTPackage Cooled:N/AD/C:02+

CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on t...

74ALVCH16345PA

Vendor:IDTPackage Cooled:TSSOP

+ : The parameter is measured with the recommended copper heat sink pattern on an 2-layer PCB, 11.7 in2 3.02.4 in2 in PCB, 1oz. copper, 3.01.5 in2 in coverage at Top-layer and Bottom-layer at 100% coverage (7.2in2). ++:The parameter is measured with the JEDEC standard test boards (multi-layer PCB).

74ALVCH16373

Vendor:PHIPackage Cooled:TSSOP48

Indirect addressing options provide addressing flexibility: base address registers for easier implementation of circular buffering, pre-modify with no update, post-modify with update, pre- and post-modify by an immediate 8-bit, twos-complement value.

74ALVCH16373DL

Vendor:PHIPackage Cooled:SSOP-48D/C:2002

Supports PIO mode 4, both at 16.6 Mbytes/second theoretically Sustained write max 1.5 Mbyte/sec (max) in ATA PIO mode 4 (8MB to 48MB) Sustained write max 3.2 Mbyte/sec (max) in ATA PIO mode 4 (64MB to 512MB) Sustained read max 6.5 Mbyte/sec (max ) in ATA PIO mode 4

74ALVCH16373PA

Vendor:IDTPackage Cooled:SSOPD/C:98

2. Stand-by SW function By means of controlling pin(4) (stand-by terminal) to high and low, the power supply can be set to on and off. The threshold voltage of pin(4) is set at 2.1V (3VBE), and the power supply current is about 1µA (typ.) at the stand-by state.

74ALVCH16373T

Vendor:FAIRCHILDD/C:06+

Notes: 3. CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 4. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal tha...

74ALVCH16374DGG

logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level); while OE is in high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. All inputs and outputs are equipped with protection circuits against static discharge, giving the...

74ALVCH16374DGG

logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level); while OE is in high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. All inputs and outputs are equipped with protection circuits against static discharge, giving the...

74ALVCH16374DGGR

Vendor:TI

Notes: 1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in this data sheet. 2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. 3. Guaranteed by design 4. ∆RON = ∆RON max - ∆RON min 5. Flatness is defined as the difference between the maximum and minimum value of on-resistance me...

74ALVCH16374DL

Vendor:PHIPackage Cooled:SSOP/48D/C:01+

Low Cost Complete H-Bridge 8 Amp Capability, 75 Volt Maximum Rating Self-contained Smart Lowside/Highside Drive Circuitry Shoot-through Protection Isolated Case Allows Direct Heatsinking Four Quadrant Operation, Torque Control Capability Logic Level Disable Input Logic Level High Side Enable Input for Special Modulation or Function Internal Divider Reference for Threshold Voltage

74ALVCH16374DL112

The UHPI can also be restricted to accessing a single page (64K bytes) of memory anywhere in the address space of the C672x; this page can be changed, but only by the C672x CPU. This feature allows the UHPI to be used for high-speed data transfers even in systems where security is an important requirement.

74ALVCH16374PV

Vendor:IDTPackage Cooled:SSOP-7.2-48PD/C:6+

The current drive capability of the buffered Tx and Ty outputs exceeds 100 mA. If a wiring fault causes a short from these pins to VCC (or to a buffered bus supply when using different supplies) then high dissipations result when Sx or Sy are driven low. The rated 300 mW dissipation can be exceeded within a very short time.

74ALVCH16409

74ALVCH16500

Vendor:PHIPackage Cooled:TSSOP/56D/C:01+

Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Q Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche EnergyRU Avalanche CurrentQU Repetitive Avalanche EnergyQ Peak Diode Recovery dv/dt SU Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Recommended clip force

74ALVCH16501DGG

The ADP3041 is a fixed frequency, PWM step-up dc-to-dc switching regulator with five buffers capable of 12 V boosted output voltage in a TSSOP 20-lead package. It provides high efficiency, low noise operation, and excellent dynamic response, and is easy to use. The high switching frequency allows for small, cost-saving, external inductive and capacitive components. The ADP3041 operates in PWM current mo...

74ALVCH16501DL

2DESCRIPTION In a 1.4 x 7 x 7mm low-profile Ball Grid Array pack- age, the new modules integrate all of the key func- tions, requiring only a 26MHz crystal and a power amplifier module (PA+antenna switch functions) to build a complete triple-band solution from antenna to base band interface. Two versions are offered: type STw3100 addresses the European EGSM900, DCS1800, and PCS1900 bands while the ...

74ALVCH16501PA

D/C:99+

The Cypress series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industries fastest logic and buffers. The Cypress 74ALVCH16501PA fanout buffer features one input and ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V. Designed for data communications clock management appli- cations, the large fanout from a single input reduces loading on the input c...

74ALVCH16525PA

Vendor:IDTPackage Cooled:N/AD/C:02+

CML outputs have a common-mode voltage near VCC. To avoid changing this optimum common-mode volt- age, all CML outputs are AC-coupled on-board with 0.1µF capacitors. The CML outputs should not be con- nected directly through 50Ω to ground.

74ALVCH16540DGG

Vendor:ＮＸＰ

CAUTIONS:The BiCMOS inherent to the design of this component increases the components susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

74ALVCH16540DGG

Vendor:ＮＸＰ

CAUTIONS:The BiCMOS inherent to the design of this component increases the components susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

74ALVCH16543

Vendor:PHIPackage Cooled:TSSOP/56D/C:01+

HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against inadvertent programs to the AT49BV/LV040 in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhib- ited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not...

74ALVCH16543PA

Vendor:IDTPackage Cooled:99+D/C:TSSOP56

74ALVCH16600

Vendor:10Package Cooled:99/00+D/C:TSOP56

N-channel enhancement mode field-effect power transistor in a plastic envelope. The device is intended for use in Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in automotive and general purpose switching applications.

74ALVCH16601

Vendor:PHIPackage Cooled:TSSOP/56D/C:01+

The A8282SLB output is set to 12, 13, 18, or 20-V by the VSEL terminals. Additionally, it is possible to increase the selected voltage by 1-V to compensate for the voltage drop in the coaxial cable (LLC terminal high). It is supplied in a 24-lead SOIC power-tab package. The power tabs are at ground potential and need no electrical isolation. The A8282SLB is an improved version of the A8283SLB, without a...

74ALVCH16601DGG

Vendor:PHIPackage Cooled:TSSOPD/C:01+

NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPTX selects the operating voltage levels on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and controls will operate...

74ALVCH16601DGG

Vendor:PHIPackage Cooled:TSSOPD/C:01+

NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPTX selects the operating voltage levels on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and controls will operate...

74ALVCH16601PA

Vendor:IDTPackage Cooled:TSSOP

VR is the regulator output voltage setting. Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below its nominal value measured at a 1V differential. Varies with type of pass transistor used. Numbers shown are for the test circuit of Figure 3-1. The product of IEXT X VEXT must be less than the maximum allowable power dissipation.

74ALVCH16601PV

Vendor:SSOPPackage Cooled:IDTD/C:00+

Stresses above those listedunder Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation ofthe device atthese or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratingconditions for external periods may affect device reliability. * Allvoltage values are ...

74ALVCH16623DGG

Vendor:PHIPackage Cooled:TSSOP/56D/C:01+

be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs.

74ALVCH16646

Vendor:PHIPackage Cooled:TSSOP/56

Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: Based on long-term current density limitations.

74ALVCH16646DGG

The symmetry of all waveforms can be adjusted with the external timing resistors. Two possible ways to accomplish this are shown in Figure 3. Best results are obtained by keeping the timing resistors RA and RB separate (A). RA controls the rising portion of the triangle and sine wave and the 1 state of the square wave.

74ALVCH16646PA

Vendor:IDTPackage Cooled:00+D/C:TSSOP56

The EP7311 includes two 16550-type UARTs for RS-232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data. The UARTs support bit rates up to 115.2 kbps. An IrDA SIR protocol encoder/decoder can be optionally switched into the

74ALVCH16652PA

Vendor:IDTPackage Cooled:01+D/C:TSSOP56

Functional I/O The HFBR-5710L accepts industry standard differential signals such as LVPECL and CML within the scope of the SFP MSA. To simplify board requirements, transmitter bias resistors and coupling capacitors are incorporated into the transceiver module. The module is ac- coupled and internally terminated.

74ALVCH16721A

Vendor:TSSOP-56Package Cooled:.D/C:04+

The key parameters of a damper diode are the peak forward voltage (VFP), the forward voltage (VF ) and the recovery time (trr). Reverse recovery time : trr The table in fig.1 gives the maximum reverse recovery time for the three high frequency damper diodes.

74ALVCH16721PF

Vendor:IDTPackage Cooled:TSOP56D/C:2007+

The external bootstrap capacitor is necessary to achieve the fastest gate rise times. The bootstrap capacitor (C3) supplies additional current at a higher voltage to the gate drive regulator as the MOSFET is switched on. When the MOSFET is off, the gate drive regulator voltage is applied to the boost capacitor . As the MOSFET turns on, the MOSFET source-to-ground voltage increases. The increas- ing so...

74ALVCH16821

Vendor:490Package Cooled:99/00+D/C:SOP56

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage ...

74ALVCH16821A

Vendor:PHIPackage Cooled:SSOPD/C:01+

Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD). Used as internal reference output when EXTLO = AGND, requires a 0.1-µF decoupling capacitor to AGND when used as reference output

74ALVCH16821DL

Interfacing to combined audio/video decoders Interfacing to SAA9042 and SAA5270 teletext decoders and SAA7183 EURO-DENC Program clock reference processing Time stamp processing (PTS/DTS) Output buffering for audio and video Microcontroller interfacing Short filter module Long filter module Subtitling filter

74ALVCH16821PA

Vendor:IDTPackage Cooled:TSSOP

The operating system can theoretically shut down an RS-232 port if, after a suitable delay, it sees no incoming data transitions or status-line changes. But the choice of delay period presents a problem-you can miss data if you happen to power down just as a data burst begins, and you'll probably miss some of the data that wakes up the system and initiates power-up. For these reasons, designers seldom go...

74ALVCH16821PA

Vendor:IDTPackage Cooled:TSSOP

The operating system can theoretically shut down an RS-232 port if, after a suitable delay, it sees no incoming data transitions or status-line changes. But the choice of delay period presents a problem-you can miss data if you happen to power down just as a data burst begins, and you'll probably miss some of the data that wakes up the system and initiates power-up. For these reasons, designers seldom go...

74ALVCH16823DGG

Notes 1. DC Current Transfer Ratio (CTRCE) is defined as the transistor collector current (ICE) divided by the input LED current (IF) x 100%, at a specified voltage between the collector and emitter (VCE). 2. The collector base Current Transfer Ratio (CTRCB) is defined as the transistor collector base photocurrent(ICB) divided by the input LED current (IF) time 100%. 3. Referring to F...

74ALVCH16823DGG

Notes 1. DC Current Transfer Ratio (CTRCE) is defined as the transistor collector current (ICE) divided by the input LED current (IF) x 100%, at a specified voltage between the collector and emitter (VCE). 2. The collector base Current Transfer Ratio (CTRCB) is defined as the transistor collector base photocurrent(ICB) divided by the input LED current (IF) time 100%. 3. Referring to F...

74ALVCH16823DL

An incoming RF signal is first filtered by a narrow-band SAW filter, and is then applied to RFA1. The pulse generator turns RFA1 ON for 0.5 µs. The amplified signal from RFA1 emerges from the SAW delay line at the input to RFA2. RFA1 is now switched OFF and RFA2 is switched ON for 0.55 µs, amplifying the RF signal further. The ON time for RFA2 is usually set at 1.1 times the ON time for RFA1, as t...

74ALVCH16823PA

Vendor:IDTPackage Cooled:TSSOP

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD78

74ALVCH16825

Vendor:PHIPackage Cooled:TSSOP/56D/C:01+

The DS1543 has interrupt ( IRQ /FT) and reset ( RST ) outputs which can be used to control CPU activity. The IRQ /FT interrupt output can be used to generate an external interrupt when the RTC register values match user programmed alarm values. The interrupt is always available while the device is powered from the system supply and can be programmed to occur when in the battery backed state to serve ...

74ALVCH16825DGG

Vendor:PHIPackage Cooled:TSSOP/56D/C:01+

74ALVCH16825DGG112

74ALVCH16825PA

Vendor:IDTPackage Cooled:TSSOP

Amplifier gain is controlled by two terminals, UP and DOWN. There are 31 discrete steps covering the range of 20 dB (maximum volume setting) to C40 dB (minimum volume setting) in 2 dB steps. By pressing either button momentarily, the volume steps up or down 2 dB. If a button is held down, the device starts stepping through volume settings at a rate determined by the capacitor on the CLK terminal.

74ALVCH16827DGG

DESCRIPTION The LD1117A is a LOW DROP Voltage Regulator able to provide up to 1A of Output Current, available even in adjustable version (Vref=1.25V). Concerning fixed versions, are offered the following Output Voltages: 1.2V, 1.8V, 2.5V, 2.85V, 3.3V and 5.0V. The 2.85V type is ideal for SCSI-2 lines active termination. The device is

74ALVCH16832

Vendor:TIPackage Cooled:TSSOP

The MC74AC350/74ACT350 is a specialized multiplexer that accepts a 4-bit word and shifts it 0, 1, 2 or 3 places, as determined by two Select (S0, S1) inputs. For expansion to longer words, three linking inputs are provided for lower-order bits; thus two packages can shift an 8-bit word, four packages a 16-bit word, etc. Shifting by more than three places is accomplished by paralleling the 3-state outputs ...

74ALVCH16832DGG

Vendor:PHIPackage Cooled:TSSOP64D/C:2007+

The IS24CXX (IS24C16-2, IS24C16-3, IS24C08-2 and IS24C08-3) family is a low-cost and low voltage 2-wire Serial EEPROM. It is fabricated using ISSIs advanced CMOS EEPROM technology and provides a low power and low voltage operation. The IS24CXX family features a write protection feature, and is available in 8-pin DIP and 8-pin SOIC packages.

74ALVCH16832PA

Vendor:IDTPackage Cooled:03+D/C:TSSOP64

74ALVCH16836PV

Vendor:IDTPackage Cooled:04+D/C:SSOP56

The PT6670 is a series of high-output Integrated Switching Regulators (ISRs) designed to provide a voltage boost function. Housed in a 14-Pin SIP (Single In-line Package), the PT6670 series incorporates regulators for either a +3.3V or +5.0V input and provide output voltages from +5V to +12V. Applications include power for auxilliary circuits requiring up to 20W.

74ALVCH16836PV

Vendor:IDTPackage Cooled:04+D/C:SSOP56

The PT6670 is a series of high-output Integrated Switching Regulators (ISRs) designed to provide a voltage boost function. Housed in a 14-Pin SIP (Single In-line Package), the PT6670 series incorporates regulators for either a +3.3V or +5.0V input and provide output voltages from +5V to +12V. Applications include power for auxilliary circuits requiring up to 20W.

74ALVCH16841

Vendor:PHIPackage Cooled:TSSOP/56D/C:01+

This single-pole, double-throw reflective switch consumes less than 50uA and can operate with positive or negative 3V to 8V supply voltages, making it suitable for use in both infrastruc- ture and subscriber equipment. This switch can be used in all analog and digital wireless communication systems including (but not limited to) AMPS, PCS, DECT, IS-95, IS-136, 802.11, CDPD and GSM.

74ALVCH16841DGG

Vendor:PHIPackage Cooled:TSSOPD/C:01+

RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. The Full Flag (FF) will be reset to HIGH after tRSF. The Empty Flag (EF) will be reset to LOW after tRSF. During reset, the output register is initialized to all...

74ALVCH16843DGG

Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the one volt threshold, the pulse is terminated. The over current comparator, however, is not blanked. It will catch catastrophic over current faults without a blanking delay. Any time the ILIM pin exceeds 1.2V, the fault latch will be set and the outputs driven low. For this rea- son, some noise...

74ALVCH16863

74ALVCH16863PA

Vendor:IDTPackage Cooled:TSSOP-7.2-56PD/C:6+

VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω 1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN 2.5GHz input duty cycle = 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (Note 7)

74ALVCH16863PA

Vendor:IDTPackage Cooled:TSSOP-7.2-56PD/C:6+

VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω 1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN 2.5GHz input duty cycle = 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (Note 7)

74ALVCH16901PA

Vendor:IDTPackage Cooled:TSSOP-7.2-64PD/C:6+

While the busy signal is asserted, the host processor is free to perform other tasks (including running the print spooler). When the time slot is complete, the DS1481 restores both O1/BSY1 and O2/BSY2 to the states of I1 and I2 (see Figure 1).

74ALVCH16952PA

Vendor:IDTPackage Cooled:TSSOP56D/C:2007+

Program Verify Command Following byte program, the programmed byte must be verified. The program-verify is initiated by writing Program Verify Command (C0H) to the command latch. After writing Program Verify Command, programmed data is verified in read mode. Then the address information is not needed.

74ALVCH16952PV

Vendor:SSOPPackage Cooled:IDTD/C:00+

The quad consists of eight differential low noise (0.65nVHz) voltage preamps. Two select lines control two pairs of inputs. Each of the output stages provides a nominal 470Ω-output impedance on each half of the differential output stages. The overall gain of 190V/V may be attenuated by adding an external load resistor between each set of differential out- puts. For example, adding an external 940...

74ALVCH245MTC

74ALVCH32245BF

Vendor:IDTPackage Cooled:BGA96D/C:2007+

In addition, the L1 instruction memory and L1 data memories may be configured as either Static RAMs (SRAMs) or caches. The Memory Management Unit (MMU) provides memory pro- tection for individual tasks that may be operating on the core and may protect system registers from unintended access.

74ALVCH32245ZKER

Vendor:TI

Operating voltage: fSYS=4MHz: 3.3V~5.5V fSYS=8MHz: 4.5V~5.5V 13 bidirectional I/O lines (max.) 1 interrupt input shared with an I/O line 8-bit programmable timer/event counter with overflow interrupt and 7-stage prescaler On-chip crystal and RC oscillator Watchdog Timer 2048´14 program memory PROM 64´8 data memory RAM Supports PFD for sound generation HALT function and wake-up feature r...

74ALVCH32373BF

Vendor:IDTD/C:07+

FUNCTIONAL DESCRIPTION The LS257B and LS258B are Quad 2-Input Multiplexers with 3-state outputs. They select four bits of data from two sources each under control of a Common Data Select Input. When the Select Input is LOW, the I0 inputs are selected and when Select is HIGH, the I1 inputs are selected. The data on the selected inputs appears at the outputs in true (non- inverted) form for the LS257B ...

74ALVCH32501

Vendor:PHILIPSPackage Cooled:02+D/C:BGA

The KM732V589A/L is a 1,048,576-bit Synchronous Static Random Access Memory designed for high performance sec- ond level cache of Pentium and Power PC based System. It is organized as 32K words of 32bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applica- tions; GW, BW, LBO, ZZ. Write cycles are internally self-timed...

74ALVCH32973ZKER

Vendor:TIPackage Cooled:N/AD/C:N/A

Edition 1998-10-08 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 Mnchen © Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information d...

74ALVCH374PG

Vendor:IDTPackage Cooled:TSOP20D/C:2007+

Single Chip With Easy Interface Between UART and Serial-Port Connector of IBM™ PC/AT ™ and Compatibles Meets or Exceeds the Requirements of ANSI Standard TIA/EIA-232-F and ITU Recommendation V.28 Designed to Support Data Rates up to 120 kbit/s Pinout Compatible With SN75C185 and SN75185 ESD Protection to 2 kV on Bus Terminals Package Options Include Plastic Small-Outline (DW), Shrink Small-Ou...

74ALVCHR162245PV

Vendor:IDTPackage Cooled:00+D/C:SSOP-48

Notes : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, v...

74ALVCHR16245ZQLR

Vendor:TID/C:ORIGINAL

Stress in excess of Absolute Maximum Rat- ings may cause permanent damage. Absolute Maximum Ratings, sometimes referred to as no destruction limits, are normally tested with one parameter at a time exceeding the limits of Output data or Electrical Charac- teristics. If exposed to stress above these limits, function and performance may de- grade in an unspecified manner.

74ALVCHS162830DF

Vendor:IDTPackage Cooled:TSSOP-7.2-80PD/C:6+

Max. UnitsConditions CCCSVDS = 15V, ID = 3.8A 57ID = 3.8A nC VDS = 40V VGS = 10V, CCCVDD = 40V CCCID = 3.8A ns CCCRG = 9.1Ω CCCVGS = 10V ƒ CCCVGS = 0V CCCVDS = 25V CCCpFƒ = 1.0MHz CCCVGS = 0V, VDS = 1.0V, ƒ = 1.0MHz CCCVGS = 0V, VDS = 64V, ƒ = 1.0MHz CCCVGS = 0V, VDS = 0V to 64V …

74ALVCHS162830DFG

Vendor:IDTPackage Cooled:TSSOP-7.2-80PD/C:6+

Reduced Threshold Voltages for LVTTL on Control Pine ♦ Eliminates the Need for Translators for Many Applications ♦ TTL Compatibility when VCC is 5.0 V ♦ Can Operate with 1.8 V Inputs, if VCC is 3.0 ♦ Also Meets Full CMOS Specifications

74ALVCHS16283DGB

74ALVCHT16835DGG

The device is compatible with the JEDEC single power-supply Flash command set standard. Com- mands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. Device programming is performed a byte or word at a time by executing the four-cycle Program com- mand. This initia...

74ALVCHT16835DGV

Dead time can be controlled through proper selection of CT and can range from 50 to 200nsec. Internal soft start increases pulse width on power up and maintains equal pulse widths for the high and low outputs throughout the start up cycle. Undervoltage lockout prevents operation if Vcc is less than 7.5 Vdc. Over current shutdown occurs when the voltage on the Cs pin exceeds 200mV. Restart after overcurren...

74ALVF16374DGG

Package Cooled:SOP

74ALVT162244DGG

Vendor:PHILIPSPackage Cooled:TSSOPD/C:05+

The TPS6112x devices provide a complete power supply solution for products powered by either a one-cell Li-Ion or Li-Polymer or a two up to 4 cells Alkaline, NiCd or NiMH batteries. The devices can generate two stable output voltages that are either adjusted by an external resistor divider or fixed internally on the chip. It also provides a simple solution for generating 3.3 V out of a one-cell Li-Io...

74ALVT162244DGG518

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