Index "9"Vendor:NSCPackage Cooled:SOP
Max. UnitsConditions CCCVVGS = 0V, ID = -250µA CCC V/C Reference to 25C, ID = -1mA 21VGS = -10V, ID = -8.0A ‚ mΩ 32VGS = -4.5V, ID = -6.8A -2.5VVDS = VGS, ID = -250µA CCCSVDS = -10V, ID = -8.0A -15VDS = -24V, VGS = 0V µA -25VDS = -24V, VGS = 0V, TJ = 70C -100VGS = -20V nA 100VGS = 20V 78ID = -8.0A CCCnCVDS = -15V CCCVGS = -10V 20VDD = -15V, VGS = -1...
Vendor:NSCPackage Cooled:SOP
Max. UnitsConditions CCCVVGS = 0V, ID = -250µA CCC V/C Reference to 25C, ID = -1mA 21VGS = -10V, ID = -8.0A ‚ mΩ 32VGS = -4.5V, ID = -6.8A -2.5VVDS = VGS, ID = -250µA CCCSVDS = -10V, ID = -8.0A -15VDS = -24V, VGS = 0V µA -25VDS = -24V, VGS = 0V, TJ = 70C -100VGS = -20V nA 100VGS = 20V 78ID = -8.0A CCCnCVDS = -15V CCCVGS = -10V 20VDD = -15V, VGS = -1...
Vendor:NSPackage Cooled:SOP8
• SuperWIDE™ HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 3.3V Power Supply User Selectable 3.3V/2.5V I/O 12000 PLD Gates / 256 Macrocells Up to 192 I/O Pins 256 Registers High-Speed Global Interconnect SuperWide 32 Generic Logic Block (GLB) Size for Optimum Performance Super Wide Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. PCB Eff...
Vendor:STPackage Cooled:SMD8D/C:06+
The circuit of the TSOP344..SB1F is designed in that way that unexpected output pulses due to noise or disturbance signals are avoided. A bandpass filter, an integrator stage and an automatic gain control are used to suppress such disturbances. The distinguishing mark between data signal and dis- turbance signal are carrier frequency, burst length and duty cycle. The data signal should fulfill the f...
Vendor:FPackage Cooled:DIPD/C:05+
The ISR functions normally with pin 1 open-circuit, providing a regulated output whenever a valid source voltage is applied to Vin, (pins 2, 3, & 4). When a low-level2 ground signal is applied to pin 1 the regulator output is disabled, and the input current to the ISR is reduced to about 100µA 3/.
Vendor:FPackage Cooled:DIP
Capacitance : 220µF∼1000µF Rated voltage : 16V or higher, ESR is 0.25Ω max. Ripple current is 0.4Arms above. Output ripple voltage is influenced. Please evaluate it in the actual set. L : 1mH Allowable current : 600mA or higher. Please use the one that is hard to be magnetic saturated even in the high temperature. In the absolute maximum ratings, the reverse peak voltage should b...
Vendor:FPackage Cooled:DIP
Capacitance : 220µF∼1000µF Rated voltage : 16V or higher, ESR is 0.25Ω max. Ripple current is 0.4Arms above. Output ripple voltage is influenced. Please evaluate it in the actual set. L : 1mH Allowable current : 600mA or higher. Please use the one that is hard to be magnetic saturated even in the high temperature. In the absolute maximum ratings, the reverse peak voltage should b...
Vendor:STPackage Cooled:DIP8D/C:06+
Vendor:STPackage Cooled:DIP8D/C:06+
Vendor:STPackage Cooled:SOPD/C:06+
Programs compiled natively on the host can run on the target. Programs need never be cross compiled. Native tools are easy to obtain and are usually supplied as part of the system package, for example GCC on any Linux system. Programs can be tested on the host system before the need to download them for final testing. The host and target both have the same touch and feel, i.e. both are the same architectur...
Vendor:STPackage Cooled:SOPD/C:06+
True single chip FSK/ASK transmitter in a small 8-pin package Adjustable output power up to +10dBm FSK data rate up to 50kbits/s Very few external components On-chip frequency synthesiser gives improved frequency stability compared to SAW solutions Wide power supply range: 2.4 to 3.6 V Low supply current, typical 9mA @ -10dBm output power Power Down and Clock modes makes power saving easy Reference Clo...
Vendor:STPackage Cooled:SOPD/C:06+
True single chip FSK/ASK transmitter in a small 8-pin package Adjustable output power up to +10dBm FSK data rate up to 50kbits/s Very few external components On-chip frequency synthesiser gives improved frequency stability compared to SAW solutions Wide power supply range: 2.4 to 3.6 V Low supply current, typical 9mA @ -10dBm output power Power Down and Clock modes makes power saving easy Reference Clo...
Vendor:STPackage Cooled:DIP-8
EWC: Event and Waveform Controller Compatible with Intels Programmable Counter Array (PCA) Common 16-bit timer/counter reference with four possible clock sources (Fosc/4, Fosc/12, Timer 1 and external input) Five modules, each with four programmable modes:
Vendor:INTELPackage Cooled:SOP8D/C:03+
Vendor:FPackage Cooled:SOP8D/C:96+
Vendor:NSCPackage Cooled:SOP8
Input Termination Center-Tap: Each side of the differential input pair CLK0, /CLK0 terminates to the VT pin. The VT pin provides a center-tap to a termination network for maximum interface flexibility. See CLK0 Input Interface Applications section for more details. For DC-coupled CML or LVDS inputs, the VT pin is left floating.
Vendor:NSPackage Cooled:SOP-8D/C:06+
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.
Vendor:STD/C:0
Vendor:STPackage Cooled:SOP-8D/C:3
Positive And Negative Regulators In One Package Hermetic 6-Pin Metal Package, Surface Mount Isolated Case Output Voltages: 5V, 12V, And 15V Output Voltages Set Internally To 2.0% Built-In Thermal Overload Protection Short Circuit Current Limiting Product Is Available Screened To MIL-PRF-38535, TX, TXV, S Levels
Vendor:STPackage Cooled:SMD8D/C:06+
Guaranteed by measurement of initial offset and sensitivity. Sensitivity varies with VS. At VS = 3 V, sensitivity is typically 28%/g. 3Defined as the output change from ambient-to-maximum temperature or ambient-to-minimum temperature. 4Actual frequency response controlled by user-supplied external capacitor (CX, CY). 5Bandwidth = 1/(2 32 kΩ C). For CX, CY = 0.002 µF, Bandwidth = 2500 Hz....
Vendor:STPackage Cooled:SMD8D/C:06+
Guaranteed by measurement of initial offset and sensitivity. Sensitivity varies with VS. At VS = 3 V, sensitivity is typically 28%/g. 3Defined as the output change from ambient-to-maximum temperature or ambient-to-minimum temperature. 4Actual frequency response controlled by user-supplied external capacitor (CX, CY). 5Bandwidth = 1/(2 32 kΩ C). For CX, CY = 0.002 µF, Bandwidth = 2500 Hz....
Vendor:STPackage Cooled:SOPD/C:07+
Maxwell Technologies' patented RAD-PAK® packaging technol- ogy incorporates radiation shielding in the microcircuit pack- age. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S.
Wiper position of the DS1804 can be stored using the INC and CS inputs. Storage of the wiper position takes place whenever the CS input transitions from low-to-high while the INC is high. Once this condition has occurred the value of the current wiper position will be written to EEPROM memory.
Vendor:N/APackage Cooled:QFP-40PD/C:07+
Vendor:ICSPackage Cooled:05+D/C:TSSOP-7.2-56P
Vendor:ICSPackage Cooled:SSOP-48D/C:05+
They provide transparent enhancements to Intels 8xC251Sx family with an additional Synchronous Serial Link Controller (SSLC supporting I2C, µWire and SPI protocols), a Keyboard interrupt interface, a dedicated Baud Rate Generator for UART, and Power Management features.
Vendor:ICSPackage Cooled:TSSOP-48D/C:2002
Using this configuration, the device will support SVHS mode for four encoder interface formats. The first encoder interface format will receive chroma information from the Enc_C pin and luma information from the Enc_Y pin. This format is designated SVHS, Enc 1. The second format will receive chroma information on the Enc_B input and luma information on Enc_G. This format is designated "SVHS, Enc 2"...
Vendor:ICSPackage Cooled:TSSOP-48D/C:2002
Using this configuration, the device will support SVHS mode for four encoder interface formats. The first encoder interface format will receive chroma information from the Enc_C pin and luma information from the Enc_Y pin. This format is designated SVHS, Enc 1. The second format will receive chroma information on the Enc_B input and luma information on Enc_G. This format is designated "SVHS, Enc 2"...
Vendor:NSPackage Cooled:SOPD/C:2007+
See the functional block diagram and Figure 1 for this discussion. Using the Spreetat sensor to measure the refractive index of a liquid requires the proper application of signals to the pins. See Figure 1 for a diagram of the measurement cycle. A pulse is applied to the START pin. On the subsequent positive edge of the CLOCK, the start pulse is clocked into the internal shift register initiating a reset ...
Vendor:PLCC-20Package Cooled:AMDD/C:04+
Active low signal used to reset the IrDA-SIR Decode state machine. Normally this line is tied to the POR (power on reset) line of the circuit or simply to Vcc. In addition to resetting the circuitry, this signal can be asserted to disable any data reception.
Vendor:PLCC-20Package Cooled:AMDD/C:04+
Active low signal used to reset the IrDA-SIR Decode state machine. Normally this line is tied to the POR (power on reset) line of the circuit or simply to Vcc. In addition to resetting the circuitry, this signal can be asserted to disable any data reception.
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential Nonlinearity2 Resistor Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Wiper Resistance Nominal Resistance Match
Vendor:FPackage Cooled:DIP24陶瓷D/C:89+
Non-inverting 3-state outputs 2-way asynchronous data bus communication Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from −40 C to +80 C and from −40 C to +125 C.
Vendor:FPackage Cooled:DIP24陶瓷D/C:83+
Vendor:FPackage Cooled:DIP24陶瓷D/C:83+
Vendor:FSC
Three RealTek RTL8100 10/100 Based LAN Fast PCI ATA/33/66/100 IDE controller Four COM, two USB connectors PC/104 Bus connector DiskOnChip socket supporting memory sizes of up to 288MB Supports Single +5V power in Supports Hardware Monitor
Vendor:NSCD/C:03+04+
Vendor:NSPackage Cooled:CDIP
Using the latest high voltage technology based on a patented strip layout, STMicroelectronics has designed an advanced family of IGBTs, the PowerMESH™ IGBTs, with outstanding performances. The built in collector-gate zener exhibits a very precise active clamping while the gate-emitter zener supplies an ESD protection.
Vendor:FPackage Cooled:33D/C:N/A
power consuming, high-precision LCD panel display can be assembled using the 93Z59DMQB. In the segment mode, the data input is selected 4bit parallel input mode or as 8bit parallel input mode by a mode (MD) pin. In common mode, the data input/output pins are bi-directional and the four data shift directions are pin-selectable.
Vendor:IRPackage Cooled:MODULED/C:07+
Vendor:INT
Vendor:n/aPackage Cooled:SOPD/C:06+
Package Cooled:08+D/C:800
Products designated as Not Recommended for New Design may become obsolete as dictated by poor market acceptance, or a technology or package that is reaching the end of its life cycle. Devices in this category have an uncertain future and do not represent a good selection for new device designs or long term usage.
Package Cooled:08+D/C:800
Products designated as Not Recommended for New Design may become obsolete as dictated by poor market acceptance, or a technology or package that is reaching the end of its life cycle. Devices in this category have an uncertain future and do not represent a good selection for new device designs or long term usage.
Vendor:TELEDYNEPackage Cooled:DIP
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications.
Vendor:TELEDYNEPackage Cooled:DIP
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications.
Package Cooled:DIP镀金
NOTES : 1. VIH (max) = 5.3V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 4. Dout is disabled, 0V VOUT VDDQ.
Vendor:TSC
Vendor:FAIRCHILDPackage Cooled:SOP-24D/C:03+
The first character of the part number suffix determines the device operating temperature range. Suffix EC is for -40C to +85C, and suffix LC is for -40C to +150C. Three package styles provide a magnetically optimized package for most applications. Suffix CLT is a miniature SOT- 89/TO-243AA transistor package for surface-mount applications; suffix CU is a three-lead plastic mini-SIP, while suffix CUA is a th...
Vendor:FAIRCHILDPackage Cooled:SOP-24D/C:03+
The first character of the part number suffix determines the device operating temperature range. Suffix EC is for -40C to +85C, and suffix LC is for -40C to +150C. Three package styles provide a magnetically optimized package for most applications. Suffix CLT is a miniature SOT- 89/TO-243AA transistor package for surface-mount applications; suffix CU is a three-lead plastic mini-SIP, while suffix CUA is a th...
Vendor:MPPackage Cooled:CDIP18D/C:——
Specifications are for the differential output (OUTA C OUTA or OUTB C OUTB) of a single 2nd order section (A or B), gain = C2, RFIL = R11 = R21 = R31 = R12 = R22 = R32. All voltages are with respect to VGND = VGNDA = VGNDB. The q denotes the specifications which apply over the full operating temperature range, otherwise specifications and typical values are at TA = 25C. VS = single 5V, EN pin to logic low, RL...
A gear-tooth sensing system consists of the sensor IC, a back- biasing magnet, an optional pole piece, and a target (Figure 1). The system requirements are usually specified in terms of the effective working air gap between the package and the target (gear teeth), the number of switching events per rotation of the target, temperature and speed ranges, minimum pulse duration or duty cycle, and switch poi...
Two concurrently operating 2 Gbps capable Fibre Channel nodes Supports up to 400 MBps sustained Fibre Channel data transfer rate Supports SCSI initiator, initiator/target, and target modes Onboard, enhanced RISC processor Onboard 2-Gb serial transceivers Automatically negotiates the Fibre Channel bit rate (1 or 2 Gb) Supports PCI dual-address cycle and cache commands
Vendor:n/aPackage Cooled:SMD28D/C:06+
Vendor:SINGAPOREPackage Cooled:DIP-14D/C:8235+
switch either ac or dc loads. Connection B, with the polarity and pin configuration as indicated in the schematic, allows the relay to switch dc loads only. The advantage of Connection B is that the on-resistance is significantly reduced, and the output current capability increases by a factor of two.
Vendor:FPackage Cooled:DIP/14
In the Bellcore SR-TSV-002476 Issue 1 off-hook protocol, the CPE should not ACK if it detected an off-hook extension. The FSK will not be sent and the customer will not receive the Call Waiting ID. Bellcore, together with the TIA (Telecommunications Industry Association) TR41.3.1 working group, has defined a CPE capability called Multiple Extension Interworking (MEI) which overcomes this problem.
Vendor:n/aPackage Cooled:SMD28D/C:06+
Vendor:MICROCHIPPackage Cooled:TQFP44D/C:06+
Vendor:n/aPackage Cooled:SOPD/C:06+
Vendor:InfineonPackage Cooled:QFP-80
Vendor:QFP-44Package Cooled:.D/C:04+
Single supply: 1.8 V to 5.5 V Two-wire serial interface (I 2C TM serial bus*1) Clock frequency: 400 kHz Power dissipation: Standby: 3 µA(max) Active (Read): 1 mA(max) Active (Write): 3 mA(max) Automatic page write: 32-byte/page Write cycle time: 10 ms (2.7 V to 5.5 V)/15ms (1.8 V to 2.7 V) Endurance: 105 Cycles (Page write mode) Data retention: 10 Years
D/C:08+
When the CAT24FC02 begins a READ mode, it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24FC02 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.
D/C:08+
When the CAT24FC02 begins a READ mode, it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24FC02 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.
Vendor:IDTPackage Cooled:DIP20陶瓷D/C:86+
Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated...
Package Cooled:120
Vendor:FPackage Cooled:DIP24陶瓷D/C:84+
The general purpose memory portion of the device is a CMOS serial EEPROM array with Xicors Block LockTM protection. This memory may be used to store fiber optic module manufacturing data, serial numbers, or various other system parameters.
Vendor:NSCD/C:99
Vendor:NSPackage Cooled:CDIP24D/C:8318
The ?C?A/S/L and ?C?A/S?H inputs internally generate a ?C?A/S signal functioning in a similar manner to the single ?C?A/S input of other DRAMs. The key difference is each ?C?A/S input ( ?C?A/S/L and ?C?A/S?H ) controls its corresponding 8 DQ inputs during WRITE accesses. ?C?A/S/L controls DQ1 through DQ8 and ?C?A/S?H controls DQ9 through DQ16. The two ?C?A/S controls give the MT4LC1M16E5(S) both BYTE...
Vendor:NS
Vendor:AM
Vendor:FPackage Cooled:DIP24陶瓷D/C:83+
This technique of supplying a small voltage effectively in series with the input is also used for adjusting non-inverting amplifiers. As is shown in Figure 3, divider R1, R2 reduces the voltage at the arm of the pot to 7.5 mW for offset adjustment. Since R2 appears in series with R4, R2 should be considered when calculating the gain. If R4 is greater than 10 kΩ the error due to R2 is less than 1%.
Vendor:FPackage Cooled:DIP24陶瓷D/C:83+
This technique of supplying a small voltage effectively in series with the input is also used for adjusting non-inverting amplifiers. As is shown in Figure 3, divider R1, R2 reduces the voltage at the arm of the pot to 7.5 mW for offset adjustment. Since R2 appears in series with R4, R2 should be considered when calculating the gain. If R4 is greater than 10 kΩ the error due to R2 is less than 1%.
Vendor:MOTPackage Cooled:CDIP8D/C:00+
Package Cooled:DIP-8D/C:03+
The 940424-61/T Flash memory with SmartVoltage technology is a high-density, cost-effective, nonvolatile, read/write storage solution for a wide range of applications. It operates off of VDD = 2.7V and VPP = 2.7V. This low voltage operation capability realize battery life and suits for cellular phone application. Its Boot, Parameter and Main-blocked architecture, as well as low voltage and extended cycling...
Vendor:NSCD/C:O9+
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01F should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch.
Vendor:FAIRCHILDPackage Cooled:PDIPD/C:8401
Vendor:LTPackage Cooled:06+D/C:500
90C. Dynamic performances (di/dt and response time) are best with a primary bar in low position in the through-hole. In order to achieve the best magnetic coupling, the primary windings have to be wound over the top edge of the device. This is a standard model. For different versions (supply voltages, turns ratios, unidirectional measurements...), please contact us.
90C. Dynamic performances (di/dt and response time) are best with a primary bar in low position in the through-hole. In order to achieve the best magnetic coupling, the primary windings have to be wound over the top edge of the device. This is a standard model. For different versions (supply voltages, turns ratios, unidirectional measurements...), please contact us.
Vendor:SILICONIXPackage Cooled:SOP8D/C:N/A
SUMMARY DESCRIPTION The M29W400D is a 4 Mbit (512Kb x8 or 256Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be per- formed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is po...
Vendor:N/APackage Cooled:612D/C:565