90794-008

908.5MHZ

908-065

908-075

90814-0010

Vendor:MolexPackage Cooled:connectorD/C:06+

908140026

90814-0026

Vendor:MOLEXD/C:07+

The LH1532 dual 1 Form A relays are SPST normally open switches that can replace electromechanical relays in many applications. They are constructed using a GaAIAs LED for actuation control and an integrated monolithic die for the switch output. The die, fabricated in a high-voltage dielectrically isolated technology is comprised of a photodiode array, switch control cir- cuitry, and MOSFET switches. In addi...

90841UI27Z

Vendor:7500Package Cooled:英特锡尔D/C:06+

90863-110

D/C:07+

Note 1: All voltages are with respect to GND. All currents are positive into the specified terminal. Consult Unitrode Integrated Circuits databook for information regarding thermal specifica- tions and limitations of packages. Note 2: In normal operation VCC is powered through a current limiting resistor. Absolute maximum of 12V applies when VCC is driven from a low impedance source such that ICC does ...

909 6162800

Vendor:VTECHPackage Cooled:PQFP-208D/C:1

909 6162800

Vendor:VTECHPackage Cooled:PQFP-208D/C:1

90902L3T

Vendor:INTERSILPackage Cooled:SOP16D/C:00+

A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and o...

90902L3T

Vendor:INTERSILPackage Cooled:SOP16D/C:00+

A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and o...

9091-05-00C070-0114-MN

909-235

909-235-BK

909359

Vendor:FPackage Cooled:DIP14陶瓷D/C:71+

9093-5D

Vendor:ITTPackage Cooled:DIP陶瓷

9093DC

Vendor:FPackage Cooled:DIP14陶瓷D/C:84+

Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2005 Hamamatsu Photonics K.K.

90947564-PCB

9094DC

Vendor:FPackage Cooled:DIP14陶瓷D/C:74+

909501

9095997

Vendor:PHIPackage Cooled:30D/C:N/A

Even Parity. Parity is even parity across AD31-0 and nC/BE3-0. PAR is stable and valid one clock after the address phase. For data phase, PAR is stable and valid one clock after either nIRDY is asserted on a write transaction, or nTRDY is asserted on a read transaction.

9099DM

Vendor:NS

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC C 0.6V at rated current.

90A025-313

Vendor:TOSPackage Cooled:SOP16MD/C:2007+

90A24

The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and con- trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will...

90A25-410

D/C:00

90A25-410

D/C:00

90A841

D/C:93

Test results from the Intersil ISL6271A Customer Reference Board (CRB). Output filter on switcher made up of a 4.7µH drumcore with 100mΩ of DCR and an output capacitance of 10µF. X5R; Rcomp = 50kΩ, Vin = 3.6V unless otherwise noted.

90B036

Vendor:MOTOROLAPackage Cooled:2005D/C:500

Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory. Locations in the Connect Memory, which is split into HIGH and LOW parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input (connection mode) or it can be originated from the micro...

90B20S

Vendor:PanasonicPackage Cooled:SOP16SD/C:2007+

90B854/AVS1BC

Vendor:STPackage Cooled:90

Hynix HYMD216M646A(L)6-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden- tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

90C041N

Vendor:TOSHIBAPackage Cooled:DIP

The voice-band audio processor (VBAP) is designed to perform the transmit encoding analog/digital (A/D) conversion and receive decoding digital/analog (D/A) conversion, together with transmit and receive filtering for voice-band communications systems.

90C136SC1A-LF

Case: JEDEC TO-247AD molded plastic body Terminals: Lead solderable per MIL-STD-750, Method 2026 High temperature soldering guaranteed: 250C/10 seconds, 0.17 (4.3 mm) from case Polarity: As marked Mounting Position: Any Mounting Torque: 10 in-lbs max. Weight: 0.2 oz., 5.6 g

90C22

Vendor:PANASANIPackage Cooled:SIP

90C220TB504

Package Cooled:07+D/C:800

3-wire FSK Interface Data (CMOS Output). Mark frequency corresponds to logical 1. Space frequency corresponds to logical 0. In mode 0 (when the CB0 pin is logic low) the FSK serial bit stream is output to the DATA pin directly. In mode 1 (when the CB0 pin is logic high) the start bit is stripped off, the data byte and the trailing stop bit are stored in a 9 bit buffer. At the end of each word signalled by ...

90C26-E

Vendor:ONSPECINCPackage Cooled:QFPD/C:98+

The purpose of the LVI circuit is to prevent the corruption of nonvolatile memory during voltage drops. A lower value of trip point voltage decreases the likelihood of the LVI tripping due to noise on VDD. A lower setting is therefore recommended for circuits with a lot of noise on the power supply. In circuits that do not have excessive noise it is recommended that the LVI trip point be increased which resu...

90C26-E1

Vendor:KawasakiPackage Cooled:QFP/100D/C:99+

Output driver for the high side power MOSFET. This pin should not go negative (below ground), this may cause problem for the gate drive circuit. It can happen when the inductor current goes negative (Source/Sink), soft-start at no load and for the fast load transient from full load to no load. To prevent negative voltage at gate drive, a low forward voltage drop diode might be connected between this pin and...

90C26-LC1

Vendor:ONSPECPackage Cooled:QFP-64D/C:9916+

Only four external capacitors are needed to build a complete low-ripple dc/dc converter. The push-pull operating mode of two single-ended charge pumps assures the low output voltage ripple as charge is continuously transferred to the output. All the devices can start with full load current. The devices include a low-battery detector that issues a warning if the battery voltage drops below a user-defined t...

90C36LC1B-LF

Vendor:ONSPECLN..Package Cooled:SOP

Magnitude of Common Emitter Small-Signal Short Circuit Forward Current Transfer Ratio IC = 0.5 Adc, VCE = 10 Vdc, f = 100 kHz C 1.0 MHz Forward Current Transfer Ratio IC = 0.5 Adc, VCE = 10 Vdc, f = 1.0 kHz Output Capacitance VCB = 10 Vdc, IE = 0, f = 1.0 MHz

90C36LC1B-LF

Vendor:ONSPECLN..Package Cooled:SOP

Magnitude of Common Emitter Small-Signal Short Circuit Forward Current Transfer Ratio IC = 0.5 Adc, VCE = 10 Vdc, f = 100 kHz C 1.0 MHz Forward Current Transfer Ratio IC = 0.5 Adc, VCE = 10 Vdc, f = 1.0 kHz Output Capacitance VCB = 10 Vdc, IE = 0, f = 1.0 MHz

90C46

90C46D-LF

Vendor:ONSPECPackage Cooled:QFPD/C:741

Terminate outputs with 50Ω to VCC - 2V or use an equiv- alent Thevenin termination. Use the same terminate on each output for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q is used as a single-ended output, terminate both Q and Q.

90C54-BG189

90C54-GB189

D/C:00+

The ALVCH16374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus ori- ented applications. The device is byte controlled. A buff- ered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 16-bit opera- tion.

90C54-GB189KYE

90C56P

Vendor:CSIPackage Cooled:DIP-8D/C:06+

1.1 Scope. This specification covers the performance requirements for NPN, Darlington, silicon, power transistors. Two levels of product assurance are provided for each device type as specified in MIL-PRF-19500. For JAN quality assurance level (see 6.3).

90C60

4.3.2.1 Thermal impedance (ZTJX ) for measurements initial qualification or requalification. The ZTJX measurements shall be performed in accordance with MIL-STD-750, method 3131 (read and record date ZTJX). ZTJX shall be supplied on one lot (500 devices minimum and a thermal response curve shall be submitted). Twenty two of these samples shall be serialized and provided to the qualifying activity for corr...

90C660EF004

Package Cooled:N/AD/C:08+

the current drain to a low quiescent (9 µA maximum) current. This is very useful for low power applications. The SHDN input should be driven with a CMOS logic level signal since the input threshold is 0.3 V. In TTL systems, an open collector driver with a pull-up resistor may be used.

90C660EF004

Package Cooled:N/AD/C:08+

the current drain to a low quiescent (9 µA maximum) current. This is very useful for low power applications. The SHDN input should be driven with a CMOS logic level signal since the input threshold is 0.3 V. In TTL systems, an open collector driver with a pull-up resistor may be used.

90C802AM-4081

Vendor:AZTECHPackage Cooled:SMDD/C:03+

The no-correction window size is 324 ns for DPLL #1 and 32 µs for DPLL #2. It is possible for the relative phase of the reference signal to swing inside the no-correction window depending on its jitter and the relative drift of the master clock. As a result, the phase relationship between the input signal and the output clocks (and frame pulse in case of DPLL #2) may vary up to a maximum of window size....

90CH02M-4204

Vendor:CREATIVEPackage Cooled:SOP40WD/C:2007+

Data flow from A to Y is controlled by Output Enable (OE). The device operates in the transparent mode when LE is HIGH. The A data is latched if CLK is held at a high or low logic level. If LE is LOW, the A-bus is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is HIGH, the outputs are in the high- impedance state.

90CH44F-1A62

Vendor:n/aPackage Cooled:QFPD/C:06+

or Powered-Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Ω Typical) Rail-to-Rail Switching on Data I/O Ports − 0- to 5-V Switching With 3.3-V VCC − 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow, With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical) Fast...

90CH44F-1A62

Vendor:n/aPackage Cooled:QFPD/C:06+

or Powered-Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Ω Typical) Rail-to-Rail Switching on Data I/O Ports − 0- to 5-V Switching With 3.3-V VCC − 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow, With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical) Fast...

90CH44F-6305

90CH44N-6307

The CMPWR161 is a micropower, low noise regulator designed specifically to filter out noise from a 5V digital supply making it ideal for noise-sensitive analog appli- cations. The CMPWR161 delivers up to 150mA at a fixed 4.75V output. A bandgap reference bypass pin (BYP) provides low noise operation when an external capacitor is connected between this pin and ground. In addition, the CMPWR161 feature...

90CLQ100

The AH58 die type has been found to have all pins able to withstand a transient pulse of 400V, per Mil- Std-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of 100mA and/or 20V.

90CM38F-3A78

Indicates to the IA21140AF that access to the bus has been granted. Used as a chip select by the host to indicate configuration read and write cycles. When one of the appropriate bits in CSR5 gets set, interrupt request gets asserted if the corresponding mask bit in CSR7 is not set. If more than one interrupt bit in CSR5 is set and all input bits are not cleared, interrupt request gets deasserted for one clo...

90G02T0021

Vendor:TELTRENDINCD/C:08+

90G0423

Vendor:HITACHIPackage Cooled:98+D/C:QFP

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

90G0423EB

Vendor:HITPackage Cooled:N/AD/C:1998

Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150C (@ Tf 100C). However, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125C (@ Tf 100C).

90G0423EB

Vendor:HITPackage Cooled:N/AD/C:1998

Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150C (@ Tf 100C). However, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125C (@ Tf 100C).

90G0653EB

Vendor:HITACHIPackage Cooled:QFPD/C:0

(18) System clock divider • Low power consumption operation is available • Minimum instruction cycle time (300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be switched by program (when using 10MHz main clock)

90G06CF7050

Package Cooled:07+D/C:800

Notes: 6. For I/O ports, Input Leakage Current (II) includes the 3-state Output Leakage Current. Unused pins are at VCC or GND. 7. This applies in the disabled state only. 8. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

90G0866

D/C:38000

Enhanced N channel FET with no inherent diode to Vcc 5Ω bidirectional switches connect inputs to outputsΩ Zero propagation delay, zero ground bounce TTL-compatible input and output levels Undershoot clamp diodes on all switch and control inputs Available in SSOP and TSSOP packages

90G0866

D/C:38000

Enhanced N channel FET with no inherent diode to Vcc 5Ω bidirectional switches connect inputs to outputsΩ Zero propagation delay, zero ground bounce TTL-compatible input and output levels Undershoot clamp diodes on all switch and control inputs Available in SSOP and TSSOP packages

90G08F0022

Package Cooled:N/AD/C:08+

90G12F0004

Package Cooled:07+D/C:800

Under and over temperature alert thresholds can be programmed to cause the ALERT output to indicate when the on-chip or remote temperature is out of range. This output may be used as a system interrupt or SMBus alert. The T_CRIT output is activated when the on-chip or remote temperature measurement rises above the programmed T_CRIT threshold register value. This output may be used to activate a cooling...

90G1420

Vendor:HITACHIPackage Cooled:QFPD/C:99

Analog-to-Digital Converters − 24-Bit Linear PCM or 1-Bit Direct Stream Digital (DSD) Output Data − Supports PCM Output Sampling Rates up to 216kHz − Supports 64fS and 128fS DSD Output Data Rates Dynamic Performance: PCM Output − Dynamic Range: 118dB − THD+N: −105dB Dynamic Performance: DSD Output − Dynamic Range: 115dB − THD+N: −103dB Audio Se...

90G16F0025

90G16F0025

90G2001EB

Vendor:n/aPackage Cooled:QFPD/C:06+

Converts Y, Cr, Cb data to analog RGB and composite or S-video and composite video Supports CCIR recommendations 601 and 656 All digital video encoding Selectable master/slave mode for sync signals Switchable chrominance bandwidth CCIR 624 PAL SMPTE or 170M NTSC compatible outputs GENLOCK mode I2C bus serial microprocessor interface Only VP5313 supports Macrovision anti-taping Rev. 7.01 Line 21...

90G2018

Vendor:HITD/C:O9+

256-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Compact MSOP-10 (3 mm 4.9 mm) package Pin selectable SPI/I2C compatible interface Extra package address decode pin AD0 Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/C Low power, IDD = 8 µA Wide operating temperature C40C to +125C...

90G2018

Vendor:HITD/C:O9+

256-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Compact MSOP-10 (3 mm 4.9 mm) package Pin selectable SPI/I2C compatible interface Extra package address decode pin AD0 Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/C Low power, IDD = 8 µA Wide operating temperature C40C to +125C...

90G20EF0008

Vendor:NATIONALPackage Cooled:TQFP176D/C:04/05+

Architecture of the MSP 34x5D Demodulator and NICAM Decoder Section Analog Sound IF C Input Section Quadrature Mixers Low-pass Filtering Block for Mixed Sound IF Signals Phase and AM Discrimination Differentiators Low-pass Filter Block for Demodulated Signals High Deviation FM Mode FM-Carrier-Mute Function in the Dual Carrier FM Mode DQPSK-Decoder (MSP 3415D only) NICAM-Decoder (MSP 3415D only)...

90G20F0009

90G20F003

90G2351EB

Vendor:TQFPPackage Cooled:20000D/C:HITACHI

• Vary the gain of a voltage amplifier • Provide programmable dc reference voltages for comparators and detectors • Control the volume in audio circuits • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, charact...

90G56F0002

Vendor:TOYOCOMPackage Cooled:QFP100D/C:06+

90G56F0002

Vendor:TOYOCOMPackage Cooled:QFP100D/C:06+

90G62F0009

Vendor:LUENTPackage Cooled:100D/C:07+

The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW. Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e. SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time is stored in the ser...

90G64TB7003

Package Cooled:07+D/C:800

Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recom- mended Operating Conditions table will define the conditions for actual device operation.

90G64TB7003

Package Cooled:07+D/C:800

Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recom- mended Operating Conditions table will define the conditions for actual device operation.

90G74TB7003

Vendor:3COMD/C:9

The SSTs ATA-Disk Module (ADM) contains a controller, embedded firmware, and Flash Media with a 40-pin or 44- pin female connector. Refer to Figure 1-1 for SSTs ADM block diagram. The controller interfaces with the host sys- tem allowing data to be written to and read from the Flash Media.

90HBW02PR

C Correlated Double Sampling (CDS) C Programmable Black Level Clamping Programmable Gain Amplifier (PGA) C6-dB to 42-dB Gain Ranging 12-Bit Digital Data Output: C Up to 28-MHz Conversion Rate C No Missing Codes 77-dB Signal-To-Noise Ratio Portable Operation: C Low Voltage: 2.7 V to 3.6 V C Low Power: 94 mW (Typ) at 3 V C Stand-By Mode: 6 mW

90HBW02SR

D/C:07+

UART channel B Transmit Data or infrared encoder data. Standard transmit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.

90HBW08

The record path of the 90HBW08 contains integrated microphone bias, digitally controlled stereo microphone pre- amp, and automatic gain control (AGC), with mix/mux capability among the multiple analog inputs. The playback path includes mix/mux capability from the stereo DAC and selected inputs, through programmable volume controls, to the various outputs.

90HBW10

The thermally efficient package measures only 2mm x 2mm x 0.75mm. Its backside metalization provides excellent thermal dissipation as well as visual evidence of solder reflow. The device has a Point MTTF of over 300 years at a mounting temperature of +85ºC. All devices are 100% RF & DC tested.

90HBW10P

An output capacitor is required to maintain regulator loop stability. Unlike many other LDO regulators, the FAN2502/ 03 family of products are nearly insensitve to output capaci- tor ESR. Stable operation will be achieved with a wide variety of capacitors with ESR values ranging from 10mΩ to 10Ω or more. Tantalum or aluminum electrolytic, or multi- layer ceramic types can all be used. A nom...

90J034

Vendor:MOTOROLAPackage Cooled:SMD

RTCF: Real Time Clock Fail BitVolatile This bit is set to a 1 after a total power failure. This is a read only bit that is set by hardware when the device powers up after having lost all power to the device. The bit is set regardless of whether VCC or VBACK is applied first. The loss of one or the other supplies does not result in setting the RTCF bit. The first valid write to the RTC (writing one byt...

90LS2343

Vendor:ATPackage Cooled:SOP-8

90LS2343T

Vendor:N/APackage Cooled:SMD

(1)Pulse generator (PG) characteristics : PRR=1kHz, tw = 10µs, tr = 6ns, tf = 6ns, Zo = 50Ω, VP = 3VP-P (2)Input-output conditions : RL = 500Ω, Vo = 10V, VCC = 6V (3)Electrostatic capacity CL includes floating capacitance at connections and input capacitance at probes

90LS4433

Vendor:ATPackage Cooled:127D/C:N/A

The 90LS4433 offers 20 or 28 I/O ports, depending on package choice. These can be applied to a variety of combinations of different display types, for example: seven, 7-segment digits (Figure 7). This example requires two 90LS4433s, with one digit being driven by both devices, half by one 90LS4433, half by the other (digit 4 in this example). The two drivers are static, and therefore do not need to be synchr...

90LS4433-4AI

Vendor:ATMEL

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when op...

90LS8535

DESCRIPTION The EMIF06-VID01C1 is a 6 lines highly integrat- ed array designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interfer- ences. The EMIF06-VID01C1 Flip-Chip packaging means the package size is equal to the die size. Additionally, this filter includes an ESD protection circuitry which prevents the protected device from destruction when subjected to ESD surges ...

90LV0

MAX 3000A devices use CMOS EEPROM cells to implement logic functions. The userCconfigurable MAX 3000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debugging cycles, and can be programmed and erased up to 100 times.

90LV017AUE

Package Cooled:SSOP8D/C:07+

90LV018ATM

Vendor:NSPackage Cooled:SOP-8

I/O performance is increased to 622 Mb/s using Source Synchronous data transmission architectures and synchro- nous system performance up to 240 MHz using sin- gled-ended SelectI/O technology. Additional I/O standards are supported, notably LVPECL, LVDS, and BLVDS, which use two pins per signal. Almost all signal pins can be used for these new standards.

90LV027M

Vendor:NSPackage Cooled:SOP-8D/C:20058

8 kinds of time base/WDT clock sources 32´4 LCD driver Built-in 32´4 bit display RAM 3-wire serial interface Internal LCD driving frequency source Software configuration feature Data mode and command mode instructions R/W address auto increment Three data accessing modes VLCD pin for adjusting LCD operating voltage

90LV028

Vendor:NSPackage Cooled:SOP8D/C:06+

Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance