A2761I

Vendor:N/APackage Cooled:TO220D/C:4

A276308A-70/W

A276308L

Vendor:AMICPackage Cooled:PLCC32D/C:03+

A276308L-90

Vendor:AMICPackage Cooled:PLCC-32D/C:98+

A277308-70

Vendor:903Package Cooled:AMICD/C:N/A

Like all members of the FLASH370i family, the CY7C371i is rich in I/O resources. Each macrocell in the device features an associated I/O pin, resulting in 32 I/O pins on the CY7C371i. In addition, there are three dedicated inputs and two input/clock pins.

A277308L-70

Vendor:AMI

• High Reliability - NEL HALT/HASS qualified for crystal oscillator start-up conditions • High Q Crystal actively tuned oscillator circuit • No internal PLL avoids cascading PLL problems • High frequencies due to proprietary design • Metal lid electrically connected to ground to reduce EMI • Gold plated pads

A277308L-70

Vendor:AMI

• High Reliability - NEL HALT/HASS qualified for crystal oscillator start-up conditions • High Q Crystal actively tuned oscillator circuit • No internal PLL avoids cascading PLL problems • High frequencies due to proprietary design • Metal lid electrically connected to ground to reduce EMI • Gold plated pads

A27748CT-ND

D/C:06+

A2774B/VG

A2774BVG

A278308-70

Vendor:1994Package Cooled:AMICD/C:N/A

NOTES: 1. Dimensions are in inches. 2. Metric equivalents are given for general information only. 3. Symbol TL is measured from HD maximum. 4. Details of outline in this zone are optional. 5. Symbol CD shall not vary more than 0.010 inch (0.25 mm) in zone P. This zone is controlled for automatic handling. 6. Leads at gauge plane 0.054 inch (1.37 mm) +0.001 inch (0.03 mm) -0.000 inch (0.00 mm) below ...

A278308-90

Vendor:AMICPackage Cooled:N/AD/C:00+

A synchronous request/acknowledge handshake facility is provided at each port for FIFO data access. This request/ acknowledge handshake resolves FIFO full and empty boundary conditions, when the two ports are op- erated asynchronously relative to each other.

A278308AL-70

Vendor:AMICPackage Cooled:07+D/C:800

Notes: 1. TC is defined as case temperature, the temperature of the underside of the duplexer where it makes contact with the circuit board. 2. Specifications are given at operating temperature limits and room temperature. To estimate performance at some intermediate temperature, use linear interpolation.

A278308L

Vendor:AMICPackage Cooled:PLCC32

The interconnect structure (GRP) is very similar to Lattices existing ispLSI 1000, 2000 and 3000 families, but with an enhanced interconnect structure for optimal pin locking and logic routing. This eliminates the need for registered I/O cells or an Output Routing Pool.

A2790

Serial address/data input to the internal 12-bit shift register: The address/data format is that upper 4 bits (D11 to D8) indicate an address and lower 8 bits (D7 to D0) indicate data. The D11 (MSB) is the first-in bit and D0 (LSB) is the last-in bit.

A2790C

Vendor:CEMPackage Cooled:SMD8D/C:06+

Although not required for standard floppy operation, provisions for 16K bytes of external buffer SRAM, in addition to that included in the USB97C102 core, is also provided for extended applications, such as tape drives and for other special applications.

A2794BVGVR

A2799W

Output enable terminal: no matter in what phase MBI5170 operates, the signal OE /SW can always enable output drivers to sink current. When its level is (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). Mode switching trigger terminal: a one-clock-wide short signal pulse of OE /SW could put MBI5170 into the Mode Switching phase. (See Operation Principle)

A2799W

Output enable terminal: no matter in what phase MBI5170 operates, the signal OE /SW can always enable output drivers to sink current. When its level is (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). Mode switching trigger terminal: a one-clock-wide short signal pulse of OE /SW could put MBI5170 into the Mode Switching phase. (See Operation Principle)

A27C256-200DC

A2-7E

A27HC642R-35DC

A2801

Vendor:FUJITSUPackage Cooled:38D/C:N/A

FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or2. A critical component is any component of a life systems which, (a) are intended for surgical implant intosupport device or system whose failure to perform can ...

A2803LW

Vendor:MITELPackage Cooled:SMDD/C:N/A

After initialization and synchronization, the serializer accepts parallel data from inputs DIN0 C DIN9. The serializer uses the TCLK input to latch the incoming data. The TCLK_R/F pin selects which edge the serializer uses to strobe incoming data. If either of the SYNC inputs is high for six TCLK cycles, the data at DIN0 C DIN9 is ignored regardless of the clock edge selected and 1026 cycles of SYNC pattern...

A2803LW

Vendor:MITELPackage Cooled:SMDD/C:N/A

After initialization and synchronization, the serializer accepts parallel data from inputs DIN0 C DIN9. The serializer uses the TCLK input to latch the incoming data. The TCLK_R/F pin selects which edge the serializer uses to strobe incoming data. If either of the SYNC inputs is high for six TCLK cycles, the data at DIN0 C DIN9 is ignored regardless of the clock edge selected and 1026 cycles of SYNC pattern...

A2810

The Harris CD74HC32, CD74HCT32 contain four 2-input OR gates in one package. Logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally pin compatible with the standard 74LS logic family.

A2812-D1G

A283XCXC1-24D

A283XCXC-24

A284148S

Reset. M and N bits are all set HIGH. Data on M and N inputs passed directly to M divider and N output divider. TEST mode 000. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N ...

A2878W

OTP The second section of memory consists of two 64-byte arrays, each writable only once. These arrays are always password protected. Reading from either of these arrays requires the use of an OTP Read password. Both arrays can be read with a single operation. Writing either array requires an OTP Write Password. Writing more than 64 bytes to each array results in the data wrapping around and over-wr...

A2885SLW

Vendor:ALLEGROPackage Cooled:SSOPD/C:99+

A2891

Vendor:HITACHIPackage Cooled:模块D/C:N/A

A2891

Vendor:HITACHIPackage Cooled:模块D/C:N/A

A290011TL-70

D/C:03+

A290011TL-70F

Vendor:AMICPackage Cooled:PLCCD/C:1090

A290011TL-90

A290011TL-90F

A290011TV-70

The device has several operating modes dependent on the applied voltages to the S1 and S0 pins as shown in Table 1. In all the modes listed the channel multiplexers, D/A Register, LFO, and the output pulse dividers will always be powered up as long as there is a voltage source connected to the VDD pin.

A290011TX-55F

A290011TX-70

A290011TX-70F

A290011U-55F

A290011UA-70UF

A290011UV-70

The DS1267 Dual Digital Potentiometer Chip consists of two digitally controlled, solid-state potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the wiper on the resistive array is set by an 8-bit value that controls which tap point is connected to the wipe...

A290011UV-70F

A290011UV-90

A290011UV-90F

A29001TL-55F

A29001TL-70

Vendor:AMICPackage Cooled:PLCC

A29001TL-70

Vendor:AMICPackage Cooled:PLCC

A29001U-90F

A29001UL-55F

A29001UV-55

A29001UX-55F

A29001UX-70F

A290021

Vendor:AMICPackage Cooled:PLCC32

OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The precision 0.8V reference and power good output indicator are compatible with future microproces- sor generations, and a wide 3.5V to 30V (36V maximum) input supply range encompasses all battery chemistries.

A290021T-120

A290021T-55

A290021T-70

Vendor:AMICPackage Cooled:DIP

A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x100P) to retain data. This can be achieved by strobing each of the 1024 rows (A0 C A9). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffer remains in the high-impedance state. External...

A290021T-70F DIP-32 2MB P1014

A290021TL-55

A290021TL-70

Package Cooled:PLCCD/C:0031+

This device contains protection circuitry to guard against damage due to high static volt- ages or electric fields. However, precautions must be taken to avoid applications of any volt- age higher than maximum rated voltages to this highCimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an ap- pro...

A290021TL70F PB FREE70NS P0804

A290021TV-70F

A290021UL-70

Vendor:AMICPackage Cooled:N/AD/C:01+

• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Enhanced Pin Locking Capability Five Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control to Minimize Switching Noise Flexible Pin Pla...

A29002TL-120

A29002TL-55

A29002TL-90

A29002TV-150

A29002U-150

A29002U-70

A29002U-90

A29002UL-90

A29002UV-55

A29002UV-70

Package Cooled:TSOP

A29002UV-70

Package Cooled:TSOP

A29010-70

A29010V-55

A29010V-70

A290119

Vendor:N/APackage Cooled:200D/C:N/A

NOTES 1. Data, Clock and Enable inputs are high impedance Schmitt buffers without pull-up resistors; they are therefore not TTL compatible. 2. All counters have outputs directly synchronous with their respective clock rising edges. 3. The finite output resistance of the internal voltage follower and on resistance of the sample switch driving this pin will add a finite time constant to the loop. An externa...

A29011TL-70

Vendor:AMICPackage Cooled:PLCC-32D/C:2002+

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8152 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid perfo...

A29011TL-70

Vendor:AMICPackage Cooled:PLCC-32D/C:2002+

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8152 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid perfo...

A29040

The EWEN/EWDS instruction will enable or disable the programming capabilities. At both the power on and power off state the device auto- matically entered the disable mode. Before a WRITE, ERASE, WRAL or ERAL instruction is given, the programming enable instruction EWEN must be issued, otherwise the ERASE/WRITE instruction is invalid. After the EWEN instruction is issued, the programming enable condition r...

A29040-120

A29040A-70

Vendor:N/APackage Cooled:N/AD/C:08+09+

SUMMARY DESCRIPTION The M29F080D is a 8 Mbit (1Mb x8) non-volatile memory that can be read, erased and repro- grammed. These operations can be performed us- ing a single low voltage 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into 16 uniform blocks of 64Kbytes (see Figure 5, Block Addresses) that can be er...

A29040AL-70

Note 8: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond whic...

A29040AL-90

A29040AV-90

A29040B-55UF

A29040B-70

Vendor:N/APackage Cooled:N/AD/C:08+09+

There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC − VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figures 5 and 6 is based on TJ(pk) = 150_C; TC is var...

A29040B-70F

Vendor:AMICAPackage Cooled:DIPD/C:07+

A29040B-70F/T DIP32 4M P0961

A29040B-70FLASH DIP32 5V H5146

A29040B-70P

Vendor:LINKAGEPackage Cooled:DIP32D/C:05+

A29040B-90F

A29040BL-55UF

A29040BL-70

Vendor:AMICPackage Cooled:08+D/C:2400

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.02 / Apr. 2002Hynix Semiconductor

A29040BL-70F

Vendor:AMICPackage Cooled:PLCC/32D/C:05+

CML Differential Output Pairs: Differential buffered output copy of the selected input signal. The CML single-ended output swing is typically 400mV into 50Ω or 100Ω across the pair. Unused output pairs may be left floating with no impact on jitter. See CML Output Termination section.

A29040BL-70F

Vendor:AMICPackage Cooled:PLCC/32D/C:05+

CML Differential Output Pairs: Differential buffered output copy of the selected input signal. The CML single-ended output swing is typically 400mV into 50Ω or 100Ω across the pair. Unused output pairs may be left floating with no impact on jitter. See CML Output Termination section.