A0612JKNPO9BN181

Vendor:YAGEOPackage Cooled:181-0612

A0612JKNPO9BN470

D/C:07+

The RAMified Timekeeper provides full functional capability when VCC is greater than 4.5 volts and write-protects the register contents at 4.25 volts typical. Data is maintained in the absence of VCC without any additional support circuitry. The DS1386 constantly monitors VCC. Should the supply voltage decay, the RAMified Timekeeper will automatically write-protect itself and all inputs to the registers become...

A0612JRNPO470

D/C:07+

The TO-220 is offered in a 3-pin is universally preferred for all commercial-industrial applications at power dissipation level to approximately to 50 watts. Also, available in a D2 surface mount power package with a power dissipation up to 2 Watts

A0612KKNP09BN101

A0612KKNPO9BN101

D/C:07+

An address block is completed when the number of addresses generated since the beginning of the address block equals the value stored in the Block Size register. When the last address of the block is generated, BLOCK- DONE is asserted to signal the end of the address block (see Application Note 9205). On the following CLK, the mul- tiplexers are configured to pass the contents of the Block Start Addre...

A0612KKNPO9BN271

D/C:07+

When the voltage of the battery cell exceeds the overcharge protection voltage (V OCP) beyond the overcharge delay time (TOC ) period, charging is inhibited by the turning-off of the charge control MOSFET M2. The overcharge delay time is fixed to 100mS by IC internal circuit. The overcharge condition is released in two cases: 1. The voltage of the battery cell becomes lower than the overcharge release vol...

A0612KKNPO9BN470

D/C:07+

Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, J-A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using:

A0612KKNPO9BN471

D/C:232000

The MAX1165/MAX1166 are ideal for high-perfor- mance, battery-powered, data-acquisition applications. Excellent dynamic performance and low power con- sumption in a small package make the MAX1165/ MAX1166 ideal for circuits with demanding power con- sumption and space requirements. The 16-bit wide MAX1165 is available in a 28-pin TSSOP package and the byte wide MAX1166 is avail- able in a 20-pin TSSOP packa...

A0612KKNPO9BN680

D/C:07+

Unless otherwise specified, the following specifications apply over the operating ambient temperature 0C TA 70C except where otherwise noted and the following test conditions: VIN = 3.0V, VADJ = 0V, SHDN = VIN, VFB = 1.0V, Pin 8 = (not connected), Pin 1 = (+5V through 39.2Ω).

A0612KRNPO09BN102

D/C:44000

4. Low-level off state leakage current The SSR has an off state leakage current of several milliamperes, whereas the Pho- toMOS relay has only 100 pA even with the rated load voltage of 400 V (AQV414E). 5. Reinforced insulation 5,000 V type also available. More than 0.4 mm internal insulation dis- tance between inputs and outputs. Con- forms to EN41003, EN60950 (reinforced insulation).

A0612KRNPO9BB101

D/C:576000

Important Note: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA.

A0612KRNPO9BN100

Vendor:YAGEOPackage Cooled:10P-0612

A0612KRNPO9BN120

Vendor:YAGEOPackage Cooled:12P-0612

A0612KRNPO9BN221

Vendor:YAGEOPackage Cooled:221-0612

A0612KRNPO9BN270

Vendor:YAGEOPackage Cooled:27P-0612

A0612KRNPO9BN561

Vendor:YAGEOPackage Cooled:561-0612

A0612KRNPO9BN680

Vendor:YAGEOPackage Cooled:68P-0612

A0612KRX7R7BN104

D/C:07+

Table 5−43, HPI Read and Write Timing Requirements: − H13 [tw(DSL)]: deleted K = 1, K = 2, and K = 4 column − H14 [tw(DSH)]: − deleted K = 1, K = 2, and K = 4 column − changed MIN value from 3P, P, and 1.75P to 2P (ns) − deleted K = divider ratio ... footnote − added A host must not initiate transfer requests ... footnote

A0612KRX7R9BB103

Vendor:YAGEOPackage Cooled:103-0612

A0612KRX7R9BB222

Vendor:YAGEOPackage Cooled:222-0612

A0612MRX7R8BN153

Vendor:YAGEOPackage Cooled:153-0612

A0612MRX7R9BB102

Vendor:YAGEOPackage Cooled: 102-0612

A0612MRX7R9BN221

Vendor:YAGEOPackage Cooled:221-0612

A0616095

Package Cooled:94D/C:PLCC

In normal mode (LPWR = 0, MCLK = 2.048 MHz), power consumption is 25 mW per channel, and in low power mode (LPWR = 1, MCLK = 1.024MHz), power consump- tion is 15 mW per channel. Each modulator can be independently powered down to 1 mW per channel, and by halting the input clock the modulators enter a mi- cropower state using only 10 µW per channel.

A0649259

Package Cooled:N/AD/C:08+

A0649880

Vendor:TPackage Cooled:SOP-18D/C:N/A

The internal circuit is composed of 4 stages including buffer output, which provide high noise immunity and stable out- put. Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with VCC0V. These circuits prevent device destruction due to mismatched supply and input/ output voltages. This device can be used to interface 3...

A0652167

Vendor:STPackage Cooled:QFP

The LM4980 is a stereo headphone audio amplifier, which when connected to a 3.0V supply, delivers 42mW to a 16Ω load with less than 1% THD+N. With the LM4980 packaged in the SD package, the customer benefits include low profile and small size. This package minimizes PCB area and maxi- mizes output power. The LM4980 features circuitry that significantly reduces out- put transients (clicks and po...

A0653255

A0657028

Vendor:STPackage Cooled:36D/C:N/A

A0659548

A065GW01

A0660601

Vendor:PHILIPSPackage Cooled:SOP28D/C:2007+

As shown in the block diagram, the TV-SAM comprises 64 memory arrays which are accessed in parallel. Each memory array has a size of 212 rows by 64 columns. The rows and columns of the 64 (= 16 x 4) arrays can be randomly addressed, reading or writing 16 x 4 bits at a time. To obtain the extremely high data rate at the 4-bit wide data input (SDC) and outputs (SQA, SQB), a parallel to serial conversion i...

A06704

Vendor:ALPS

GHz TECHNOLOGY INC. RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE. GHz RECOMMENDS THAT BEFORE THE PRODUCT(S) DESCRIBED HEREIN ARE WRITTEN INTO SPECIFICATIONS, OR USED IN CRITICAL APPLICATIONS, THAT THE PERFORMANCE CHARACTERISTICS BE VERIFIED BY CONTACTING THE FACTORY.

A0676505

Package Cooled:N/AD/C:08+

Features • 8 LVCMOS outputs for processor and other circuitry • Crystal oscillator or external reference input • 25 or 33 MHz Input reference frequency • Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66, 50, 33, or 16 MHz • Buffered reference clock output (2 copies) • Low cycle-to-cycle and period jitter • 100-lead PBGA package • ...

A0678436

Package Cooled:QFP

A0678733

Vendor:STPackage Cooled:N/AD/C:99+

This pin is the non-inverting analog input that trans- fers the signal to the device for recording. The an- alog input amplifier can be driven single ended or differentially. In the single-ended input mode, a 32 mVp-p (peak-to-peak) maximum signal should be capacitively connected to this pin for optimal signal quality. This capacitor value, together with the 3 KΩ input impedance of ANA IN+, is ...

A0679002NMC AMNU V1

Vendor:TEKELECPackage Cooled:PLCC68D/C:08+

A0679002NMC AMNU V1

Vendor:TEKELECPackage Cooled:PLCC68D/C:08+

A0679002NMC/AMNUV1

Vendor:TEKELEC

A06B-0123-B577 A3/3000

Package Cooled:FANUC

A06B-0127-B077 A6/2000

Package Cooled:FANUC

A06B-0127-B177 A6/2000

Package Cooled:FANUC

A06B-0152-B075 A30/2000

Package Cooled:FANUC

A06B-0314-B032 5S

Package Cooled:FANUC

A06B-0359-B356 3-OS

Package Cooled:FANUC

A06B-0367-B356 4-OF

Package Cooled:FANUC

A06B-0371-B043 2-OSP

Package Cooled:FANUC

A06B-0371-B071 2-OSP

Package Cooled:FANUC

A06B-0371-B077 A1/3000

Package Cooled:FANUC

A06B-0372-B144 1-OSP

Package Cooled:FANUC

A06B-0373-B010 1-OSP/3000

Package Cooled:FANUC

A06B-0373-B075 A2/3000

Package Cooled:FANUC

A06B-0373-B077 A2/3000

Package Cooled:FANUC

A06B-0373-B169 1-OSP/3000

Package Cooled:FANUC

A06B-0374-B175 A2.5/3000

Package Cooled:FANUC

A06B-0513-B001 0

Package Cooled:FANUC

A06B-0513-B003 0

Package Cooled:FANUC

A06B-0513-B031 0

Package Cooled:FANUC

A06B-0533-B551 3-OS

Package Cooled:FANUC

A06B-0564-B005 6L

Package Cooled:FANUC

A06B-0855-B 00 A8/9000

Package Cooled:FANUC

A06B-0869-B900 A2/20000

Package Cooled:FANUC

A06B-6058-H223

Package Cooled:FANUC

A06B-6058-H334

Package Cooled:FANUC

A06B-6066-H244

Vendor:FANUCPackage Cooled:60

A06B-6077-H111

Vendor:300

The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide by two counter This counter is used to drive all internal phase clocks and the exter- nal CLKOUT signal CLKOUT is a 50% duty cycle processor clock and can be used to drive other sys- tem components All AC Timings are referenced to CLKOUT

A06B-6078-H202H500

Vendor:FANUCPackage Cooled:60

A06B-6079-H102

Package Cooled:FANUC

A06B-6079-H106

Package Cooled:FANUC

NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 W to VCC−2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR...

A06B-6079-H203

Package Cooled:FANUC

A06B-6079-H205

Package Cooled:FANUC

A06B-6079-H208

Package Cooled:FANUC

A06B-6096-H102

Package Cooled:FANUC

To determine the need for and value of the crystal adjustment capacitors, you will need a PC board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, CL.

A06B-6096-H203

Vendor:FANUCPackage Cooled:99

• VCC = 2.3V to 3.6V • Hysteresis on all inputs • Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25C • Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25C • Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors • Industrial operation at –40C to +85C • Packages available: ...

A06B-6096-H208

Package Cooled:FANUC

A06B-6114-H206

Vendor:FANUCPackage Cooled:99

A06B-6124-H106

Package Cooled:FANUC

A06FW

Vendor:0Package Cooled:07＋D/C:923

A06MW

Vendor:0Package Cooled:07＋D/C:114

A06S60080131

A0701227

Vendor:3MPackage Cooled:01+D/C:405

Reference Acknowledgement (REF_ACK) Output The REF_ACK (reference acknowledgement) pin outputs the value of the reference clock input that is routed to the phase detector. Logic 1 indicates input pair 1 (nDIF_REF1, DIF_REF1); logic 0 indicates input pair 0 (nDIF_REF0, DIF_REF0). The REF_ACK indicator is an LVCMOS output.

A070FW02

A070FW03

Vendor:44

A0723515

Package Cooled:07+D/C:800

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absoluteCmaximumCrated conditions is not implied.

A0729986

Vendor:STPackage Cooled:PQFP-160D/C:3

Ground pin. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP# . 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / 3.3V PCI free running clock output. 3.3V tolerant input for CPU frequency selection. Refer to input electr...

A073260177FF

Vendor:PHILIPSPackage Cooled:PLCC44D/C:06+

A0735498

Vendor:TIPackage Cooled:PBGA

A07401L

Package Cooled:SOT-323

The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter- nally pipelined and 2-bit prefetched to achieve very high ...

A07405

Vendor:ALPHAPackage Cooled:SOT363D/C:06PBF

NOTES: 1. All timing and jitter tolerances apply for FNOM > 25MHz. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. 4. tSKEW0 is the skew between outputs when they ...

A0744516

Vendor:PHILIPSPackage Cooled:PLCC44D/C:02+03+04

A tunable delay cell (controlled via CLKDACTRL) is integrated between the ADC and the DMUX on the clock path to fine-tune the data according to the clock alignment at the interface between the ADC and the DMUX. This delay can be tuned from -250 to 250 ps around a default center value, featuring a 500 ps typical tuning range. No tuning should be necessary for operating frequencies up to 1.5 Gsps.

A0744516

Vendor:PHILIPSPackage Cooled:PLCC44D/C:02+03+04

A tunable delay cell (controlled via CLKDACTRL) is integrated between the ADC and the DMUX on the clock path to fine-tune the data according to the clock alignment at the interface between the ADC and the DMUX. This delay can be tuned from -250 to 250 ps around a default center value, featuring a 500 ps typical tuning range. No tuning should be necessary for operating frequencies up to 1.5 Gsps.

A0762776

A0765279

Package Cooled:07+D/C:800

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, TA = 25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Measured by the voltage drop between A and B pin at indicated current through the s...

A0765A08PSC

A0774725

Vendor:1Package Cooled:AMISD/C:05+

A0778078

These N-Channel power MOSFETs are manufactured using the innovative UltraFET™ process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in...

A078FOA

Vendor:n/aPackage Cooled:QFPD/C:06+

WP is the Write Protect pin. If the WP pin is tied to Vcc, the entire array becomes Write Protected, and software write- protection cannot be initiated. When WP is tied to GND or left floating, normal read/write operations are allowed to the device. If the device has already received a write-protection command, the memory in the range of 00h-7Fh is read -only regardless of the setting of the WP pin.

A0796582

Package Cooled:SOP36

A0799876

Vendor:NETWORKSPackage Cooled:07+D/C:800

PDISS = (45 / 85) C 45 = 7.95 watts From Figure 1 we can see that this situation will require thermal resistance of approximately 4.5C / watt. Conversely we may also find the maximum ambient temperature which can be tolerated if we know the heat sink thermal resistance. Example: Converter = HR701-2805, VIN = 28 VDC, POUT = 45 W.

A079AF