A3280ELHLT

Vendor:ALLEGROPackage Cooled:SMDD/C:08+ROHS

VIN=1Vrms, f=1kHz Master=0dB, Balance=0dB Trimmer=0dB VIN=1Vrms, f=1kHz Master=0dB f=1kHz, VIN=1Vrms Master=-79dB f=1kHz, VIN=1Vrms Mute f=1kHz, VIN=1Vrms Master=-50dB Trimmer=-10dB f=1kHz,THD=1% Master=0dB Master=0dB, Rg=0,A-weight f=1kHz,Vo=1Vrms, Master=0dB,Trimmer=0dB f=1kHz,Vo=1Vrms Master=0dB,A-weight

A3280EUA

Vendor:ALLEGROPackage Cooled:SMDD/C:08+ROHS

5.2.5 Interface to Management Entities The ST20196 also runs the communication protocol to interface with external management entities. A spe- cific ADSL modem control interface has been defined to ease the integration with both systems hardware and firmware. This control communication channel is used to transfer information and commands between modem and management entities. These commands/responses are...

A3280EUA

Vendor:ALLEGROPackage Cooled:SMDD/C:08+ROHS

5.2.5 Interface to Management Entities The ST20196 also runs the communication protocol to interface with external management entities. A spe- cific ADSL modem control interface has been defined to ease the integration with both systems hardware and firmware. This control communication channel is used to transfer information and commands between modem and management entities. These commands/responses are...

A3280LLHLT

Vendor:ALLEGROPackage Cooled:N/AD/C:0502+

POWER SUPPLY Supply Voltages AVDD5 DVDD Analog Supply Current (IAVDD ) Digital Supply Current (IDVDD)6 Supply Current Sleep Mode (IAVDD) Power Dissipation6 (5 V, IOUTFS = 20 mA) Power Dissipation7 (5 V, IOUTFS = 20 mA) Power Dissipation7 (3 V, IOUTFS = 2 mA) Power Supply Rejection RatioAVDD Power Supply Rejection RatioDVDD

A3280LUA(REPLACEA88L)

Vendor:ALLEGROPackage Cooled:4-pin SIPD/C:08+

A3281

A3281LLTTR

Vendor:ALLEGROPackage Cooled:3-lead SOTD/C:05+

DCLK 3-wire FSK Interface Data Clock (Schmitt Input/CMOS Output). In mode 0 (when the CB0 pin is logic low) this is a CMOS output which denotes the nominal mid-point of a FSK data bit. In mode 1 (when the CB0 pin is logic high) this is a Schmitt trigger input used to shift the FSK data byte out to the DATA pin.

A3281LUA

The AVR uses a Harvard architecture concept C with separate memories and buses for program and data. The program memory is executed with a single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is programmable Flash memory.

A32864 STU32864

Vendor:PHILIPSPackage Cooled:BGAD/C:06+

A32864 STU32864

Vendor:PHILIPSPackage Cooled:BGAD/C:06+

A3291SLHLT

Vendor:ALLEGROPackage Cooled:SOT23D/C:2002

By taking advantage of Analog Devices high-performance complementary Si bipolar process, these gain blocks provide excellent stability over process, temperature, and power supply. This amplifier is single-ended and internally matched to 50 Ω with a return loss of greater than 10 dB over the full operating frequency range.

A3317N

Vendor:SONYPackage Cooled:40D/C:N/A

n Serial data input / output n Low dynamic current, 5 µA max. n Low standby current, 1 µA max. n Separate input and display voltages n Wide power supply range: VDD (logic) 2 to 8 V, VLCD (display) VDD to 12 V n On-chip latches separate control and display sections n Drives up to 40 LCD segments in direct drive n Crossfree cascadable n Schmitt Trigger on the inputs n 30 ns (typ.) glitch filte...

A331J15C0GF5TAA

A3-32/32

Package Cooled:99D/C:TQFP

n Versatile easy to use instruction set n 1 µs instruction cycle time n Eight multi-source vectored interrupts servicing External interrupt Idle Timer T0 One Timer (with 2 interrupts) MICROWIRE/PLUS Serial Interface Multi-Input Wake Up Software Trap Default VIS (default interrupt) n 8-bit Stack Pointer SP (stack in RAM) n Two 8-bit Register Indirect Data Memory Pointers n True b...

A3-32/32

Package Cooled:99D/C:TQFP

n Versatile easy to use instruction set n 1 µs instruction cycle time n Eight multi-source vectored interrupts servicing External interrupt Idle Timer T0 One Timer (with 2 interrupts) MICROWIRE/PLUS Serial Interface Multi-Input Wake Up Software Trap Default VIS (default interrupt) n 8-bit Stack Pointer SP (stack in RAM) n Two 8-bit Register Indirect Data Memory Pointers n True b...

A3-32/32-10VC48-12VI48

Vendor:LATTICEPackage Cooled:TQFP0707-48D/C:00+

Strap:see Note 4 Notes: 1. DQ-to-I/O wiring may be changed within a byte 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections(for memory device VDD, VDDQ); Strap out :(open) : VDD=VDDQ Strap In (Vss) : VDD=VDDQ 5. SDRAM placement alternates btw the back and front sides for the DIMM 6. Address and control resistors should be...

A3-32/32-10VI48

Vendor:ISPLSIPackage Cooled:N/AD/C:08+

A3-32/32-7VC48

Vendor:ISPLSIPackage Cooled:N/AD/C:08+

A33267

Package Cooled:00D/C:1253

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to V S0. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 50 through 53.

A33267

Package Cooled:00D/C:1253

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to V S0. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 50 through 53.

A33373

The IP117M Series are three terminal positive adjustable voltage regulators capable of supplying in excess of 0.5A over a 1.25V to 60V output range. These regulators are exceptionally easy to use and require only two external resistors to set the output voltage. In addition to improved line and load regulation, a major feature of the A series is the initial output voltage tolerance, which is guaranteed to...

A333M15Z5UF5TAA

A334-1

Vendor:HP

4: Regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is tested over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating effects are covered by the thermal regulation specification. 5: Dropout voltage is defined as the input-to-output differential at which the output voltage drops 2% below its...

A3361ELHLT

The Hyundai HYM71V631601 H-Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 16Mx8bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.

A3375-70M

Vendor:APACPackage Cooled:DIP/28D/C:98+

A339C

• 100,000 erase/write cycle Enhanced Flash program memory typical • 1,000,000 erase/write cycle Data EEPROM memory typical • Flash/Data EEPROM Retention: > 40 years • Self-programmable under software control • Priority levels for interrupts • 8 x 8 Single-Cycle Hardware Multiplier • Extended Watchdog Timer (WDT): - Programmable period from 41 ms to 131...

A34/16ZJ

Vendor:TIPackage Cooled:TSSOP

Output voltage can be programmed using the on-chip DAC or an external precision reference. A two bit code programs the DAC reference to one of 4 possible values (0.6V, 0.9V, 1.2V and 1.5V). A unity gain, differential amplifier is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. The output voltage can also be offset through the use of single exter...

A3402SJ

Vendor:N/APackage Cooled:SOPD/C:N/A

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications m...

A3402SJ(TR)

Vendor:合邦Package Cooled:9918/9920D/C:20727

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

A3402SZ

Vendor:ALLEGROPackage Cooled:SOP24D/C:00+

An excitation voltage is applied to the thermistor (RTHERM) and precision resistor (RSET), creating currents I1 and I2. The current conveyor circuit produces an output current, IO, equal to I1 C I2, which flows through the external gain-setting resistor. A buffered voltage output proportional to IO is also provided.

A3402SZ

Vendor:ALLEGROPackage Cooled:SOP24D/C:00+

An excitation voltage is applied to the thermistor (RTHERM) and precision resistor (RSET), creating currents I1 and I2. The current conveyor circuit produces an output current, IO, equal to I1 C I2, which flows through the external gain-setting resistor. A buffered voltage output proportional to IO is also provided.

A3406UC6

Vendor:1508Package Cooled:Teccor/LittelfuseD/C:N/A

Hynix HYMD264G7268-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous opera- tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelin...

A3406UC6LRP

Vendor:LF(TEC)Package Cooled:MS-013D/C:06+

The VP-1000A is an advanced CMOS LSI chip for general purpose voice/sound record and playback applications. It can be interfaced with external SRAM to construct a realtime recording circuitry, or with external ROM or EPROM for playback only applications. When ROM or EPROM is used, the sound must be digitized by using Eletech's VP-880 Voice Development System or VW- 1000A Voice EPROM Writer.

A3406UC6RP

Vendor:1508Package Cooled:Teccor/LittelfuseD/C:N/A

1. For Schottky barrier diodes thermal run-away has to be considered, as in some applications the reverse power losses PR are a significant part of the total power losses. Nomograms for determination of the reverse power losses PR and IF (AV) rating will be available on request.

A3406UC6RP

Vendor:1508Package Cooled:Teccor/LittelfuseD/C:N/A

1. For Schottky barrier diodes thermal run-away has to be considered, as in some applications the reverse power losses PR are a significant part of the total power losses. Nomograms for determination of the reverse power losses PR and IF (AV) rating will be available on request.

A3410V

Vendor:agilentPackage Cooled:08+D/C:15000

AMDs products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMDs product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to disc...

A3410V

Vendor:agilentPackage Cooled:08+D/C:15000

AMDs products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMDs product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to disc...

A3422LKA-T

Vendor:ALLEGROPackage Cooled:5-pin SIPD/C:08+ROHS

The pre-heat time is determined by an RC combination formed by R3 and C3 and the voltage of zener diode D1. When the voltage across C3 reaches the magnitude of the zener diode D1 + the turn-on threshold of Q1, capacitor C6 is shorted out and the frequency shifts to the final running frequency. The final running frequency is given by the formula:

A3425

Vendor:ALLEGROPackage Cooled:SOP-8D/C:07+

Maximum Average Forward Rectified Current . 375 (9.5mm) Lead Length @TA = 75C Peak Forward Surge Current, 8.3 ms Single Half Sine-wave Superimposed on Rated Load (JEDEC method ) Maximum Instantaneous Forward Voltage @ 3.0A Maximum DC Reverse Current @ TA=25C at Rated DC Blocking Voltage @ TA=100C

A-34252

Vendor:STPackage Cooled:QFP

Low Drive Reset. This bidirectional signal is either driven low or tri-stated, an external pull-up is required to supply the high state. The with STI RC32355 drives RSTN low during a reset (to inform the external system that a reset is taking place) and then tri-states it. The external system can drive RSTN low to initiate a warm reset, and then should tri-state it.

A3425LL-T

Vendor:ALLEGROPackage Cooled:8-LEAD SOICD/C:08+ROHS

HY57V28420A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

A3446

Vendor:PHIPackage Cooled:BGAD/C:04+

A3-4741-5

Vendor:HARRISPackage Cooled:DIP/14

These synchronous, presettable counters feature an internal carry look ahead for application in high-speed counting designs. The LV163A devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation elim...

A3-5002-5

Vendor:HARPackage Cooled:DIP

Calibration Cycle Initiate. A minimum 80 input clock cycles logic low followed by a minimum of 80 input clock cycles high on this pin initiates the self calibration sequence. See Section 2.4.2 for an overview of self-calibration and Section 2.4.2.2 for a description of on-command calibration.

A35002-5

Vendor:HARRISD/C:DIP

A3-5020-5

Vendor:HARPackage Cooled:DIP

Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to power-up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high impedance.

A35020-5

Vendor:HARRISPackage Cooled:DIP-8

Supports Fibre Channel protocol SCSI (FCP-SCSI) and Fibre Channel IP protocols Compliance with PCI Bus Power Management Interface Specification Revision 1.0 (PC98) Supports up to 200 Mbytes/sec sustained Fibre Channel data transfer rate Supports SCSI initiator, initiator/target, and target modes Onboard, enhanced RISC processor Onboard gigabit serial transceivers Supports PCI dual-address cycle and ca...

A3503

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input ...

A35033-5

Vendor:HARRISPackage Cooled:DIP-8

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltag...

A35033-5

Vendor:HARRISPackage Cooled:DIP-8

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltag...

A3-5104-5

Vendor:HARRISPackage Cooled:DIP/14

The MAX5942A/MAX5942B integrate a complete power IC for powered devices (PD) in a power-over-ethernet (PoE) system. The MAX5942A/MAX5942B provide a PD interface and a compact DC-DC PWM controller suitable for flyback and forward converters in either isolated or nonisolated designs. The MAX5942A/MAX5942B PD interface complies with the IEEE 802.3af standard, providing the PD with a detec- tion signature, a cl...

A35112-5

Vendor:HARRISD/C:DIP

A35112-5

Vendor:HARRISD/C:DIP

A3516

Vendor:PHILIPSPackage Cooled:BGA0505D/C:03+

VCC (Pin 2): Positive Input Supply Voltage (4.5V VCC 13.2V). Bypass this pin with a 1µF capacitor in series with a 4.7Ω resistor. An RC network from the VCC pin to the GATE pin is also required. The capacitor controls the slew rate at the VCC pin, while the resistor limits the inrush current when the input voltage is first applied. When the pass transistor turns on, VCC ramps down in a controlle...

A3516

Vendor:PHILIPSPackage Cooled:BGA0505D/C:03+

VCC (Pin 2): Positive Input Supply Voltage (4.5V VCC 13.2V). Bypass this pin with a 1µF capacitor in series with a 4.7Ω resistor. An RC network from the VCC pin to the GATE pin is also required. The capacitor controls the slew rate at the VCC pin, while the resistor limits the inrush current when the input voltage is first applied. When the pass transistor turns on, VCC ramps down in a controlle...

A3525R

Vendor:SONYPackage Cooled:QFP48D/C:00+

A3529MUVV

Vendor:EPSONPackage Cooled:SOPD/C:2007+

The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may c...

A3-5340-5

Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes n...

A3538S

Vendor:98

The DM9601 is a fully integrated and cost-effective single chip USB to Fast Ethernet MAC controller with 10/100 PHY. It is designed with the low power and high performance process. It is a 3.3V device with 5V tolerance and it supports 3.3V and 5V signaling.

A353BCH-2866ESARP3

D/C:6000

Calibrated directly in degrees Fahrenheit Linear a 10 0 mV F scale factor 1 0 F accuracy guaranteed (at a 77 F) Rated for full b50 to a 300 F range Suitable for remote applications Low cost due to wafer-level trimming Operates from 5 to 30 volts Less than 90 mA current drain Low self-heating 0 18 F in still air Nonlinearity only g0 5 F typical Low-impedance output 0 4X for 1 mA load

A3545

D/C:02+

The LatticeECP/EC family of FPGA devices has been optimized to deliver mainstream FPGA features at low cost. For maximum performance and value, the LatticeECP (EConomy Plus) FPGA concept combines an efficient FPGA fabric with high-speed dedicated functions. Lattices first family to implement this approach is the LatticeECP-DSP (EConomy Plus DSP) family, providing dedicated high-performance DSP...

A3546 PHI 0433+ QFN

A3548

Vendor:EPSONPackage Cooled:SOP

The IDTQS74FCT2245T is an 8-bit non-inverting transceiver that has three-state outputs, ideal for bus-oriented applications. The Transmit/ Receive (T/R) input determines the direction of data flow, either from A to B or B to A, and the Output Enable (OE) input enables the selected port for output. The QS74FCT2245 has a 25Ω resistor output that is useful for driving transmission lines and reducing ...

A3548MCVV

Vendor:EPSONPackage Cooled:SMDD/C:07+

Mode Select Table A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP A LOW signal on PE overrides counting and allows informa- tion on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP With PE and MR (LS...

A3549

Vendor:ALLEGROPackage Cooled:40D/C:N/A

speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. The device requires the 3-STATE control input G to be set high to place the output in to the high impedance state. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static dischar...

A3549

Vendor:ALLEGROPackage Cooled:40D/C:N/A

speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. The device requires the 3-STATE control input G to be set high to place the output in to the high impedance state. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static dischar...

A3559

Vendor:PHILIPSD/C:03+

The EB-2100x is an all-digital amplifier evaluation board that demonstrates Apogees DDX-2000/2100 chip set solution. The board features coaxial and optical S/PDIF digital interfaces, volume and balance controls, expansion headers for off-board processing, and local power regulation enabling single supply operation from 10 to 36VDC. The all-digital amplifier board may be configured as either 2 x 50W into 8&...

A3564

The buffers wide input dynamic range enables them to receive dif- ferential signals from LVPECL and LVDS sources. The devices can be used as compact high-speed serial translators between LVPECL and LVDS data lines. The differential translation provides a simple way to mix and match Optical Transceiver ICs from various vendors without redesigning the interfaces.

A3568

Package Cooled:QFPD/C:00+

A review of these data shows that the HSMS-280x family has the highest breakdown voltage, but at the expense of a high value of series resistance (Rs). In applica- tions which do not require high voltage the HSMS-282x family, with a lower value of series

A3568C

• VPPLK has been lowered to 1.5 V to support 2.7 V, 3.3 V and 5 V block erase and word write operations. Designs that switch VPP off during read operations should make sure that the VPP voltage transitions to GND. • To take advantage of SmartVoltage technology, allow VPP connection to 2.7 V, 3.3 V or 5 V.

A3587

Package Cooled:SMD-8D/C:05+

A358F

Vendor:N/APackage Cooled:SOP8D/C:N/A

28F3208W30 product references removed (product was discontinued) 28F640W30 product added Revised Table 2, Signal Descriptions (DQ15C0, ADV#, WAIT, S-UB#, S-LB#, VCCQ) Revised Section 3.1, Bus Operations Revised Table 5, Command Bus Definitions, Notes 1 and 2 Revised Section 4.2.2, First Latency Count (LC2C0); revised Figure 6, Data Output with LC Setting at Code 3; added Figure 7, First Access Latency...

A358S

• Generation 4 IGBTs offer highest efficiencies available maximizing the power density of the system • IGBT's optimized for specific application conditions • HEXFREDTM diodes optimized for performance with IGBTs. Minimized recovery characteristics reduce noise EMI • Designed to exceed the power handling capability of equivalent industry-standard IGBT

A3595CUG1

Package Cooled:04+

A3600R

D/C:05+

A36102216

Vendor:SOP-16Package Cooled:.D/C:2004+

Note 1: Power delivered to IF SA36102216A connector of A36102216A EV kit. Power delivered to A36102216A IC is approximately 1.0dB less due to balun losses. Note 2: Guaranteed by design and characterization. Note 3: Two tones at 1.9GHz and 1.901GHz at -32dBm per tone. Note 4: Two tones at 1.9GHz and 1.901GHz at -22dBm per tone. Note 5: A36102216ixer operation guaranteed to this frequency. For optimum gain, a...

A3625

A3626

A3630

Fully differential Low noise 2.25 nV/Hz 2.1 pA/Hz Low harmonic distortion 98 dBc SFDR @ 1 MHz 85 dBc SFDR @ 5 MHz 72 dBc SFDR @ 20 MHz High speed 410 MHz, 3 dB BW (G = 1) 800 V/µs slew rate 45 ns settling time to 0.01% 69 dB output balance @ 1 MHz 80 dB dc CMRR Low offset: 0.5 mV max Low input offset current: 0.5 µA max Differential input and output Differential-to-differential o...

A3661AT

Vendor:PHIPackage Cooled:SOP8SD/C:2007+

A3663AT

D/C:03+

Complies with USB Specification Rev 1.1 & 2.0 Supports Full Speed Mode (12Mbit/sec.) Integrated 5V to 3.3V regulator Used as a USB device transceiver VBUS disconnection indication through VP, VM Two single-ended receivers with hysteresis USB Detection of VBUS via level translator Stable RCV output during SE0 condition Low power operation Supports 1.65V to 3.3V I/O voltage levels Full industr...

A3668AT

Vendor:PHIPackage Cooled:03+D/C:SOP-3.9-8P

FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset register programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load from Port A, and serial load. When serial load is selected for flag offset register prog...

A3668AT

Vendor:PHIPackage Cooled:03+D/C:SOP-3.9-8P

FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset register programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load from Port A, and serial load. When serial load is selected for flag offset register prog...

A3700-000E

Vendor:AVAGOD/C:07无铅

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. (2) All typical values are at 25C and with a 3.3-V supply voltage. (3) HP4194A impedance analyzer (or equivalent)

A3700-300E

Vendor:AVAGOD/C:07无铅

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.

A3700-500E

Vendor:AVAGOD/C:07无铅

The A3700-500E is a low dropout voltage regulator with reset function. It provides up to 150mA of logic supply, and the reset function monitors either input or output voltage of the regulator with 2% accuracy. It is suitable for local power supply and reset for small micro controller and other logic chips.

A3701A

All DATEL sampling A/D converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70C and C55 to +125C. All room temperature (TA = +25C) production testing is performed without the use of heat sinks or forced air cooling. Thermal impedance figures for each device are listed in their respective specification tables.

A371-22GD

Vendor:LUCNTPackage Cooled:N/AD/C:N/A

A37127I

CHRG (Pin 3): Open-Drain Charge Status Output. When a depleted battery is being charged, the CHRG pin is pulled to ground by an N-MOSFET capable of driving an LED. Once the duty cycle at the GATE pin drops below 10%, the N-MOSFET turns off and a weak 40µA current source to ground turns on to indicate a near end-of-charge (C/10) condition. When a time-out occurs or the input supply is removed, the CHRG ...

A372NSR

Vendor:TIPackage Cooled:SOP8D/C:02+

The CLC425's combination of ultra-low noise, wide gain-band- width, high slew rate and low dc errors will enable applications in areas such as medical diagnostic ultrasound, magnetic tape & disk storage, communications and opto-electronics to achieve maximum high-frequency signal-to-noise ratios.

A372NSR

Vendor:TIPackage Cooled:SOP8D/C:02+

The CLC425's combination of ultra-low noise, wide gain-band- width, high slew rate and low dc errors will enable applications in areas such as medical diagnostic ultrasound, magnetic tape & disk storage, communications and opto-electronics to achieve maximum high-frequency signal-to-noise ratios.

A3760-000E

Vendor:AVAGOD/C:07无铅

(1) All typical values are at TA = +25C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for CH x+ = −2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V). (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the f...

A3760-000E

Vendor:AVAGOD/C:07无铅

(1) All typical values are at TA = +25C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for CH x+ = −2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V). (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the f...

A3760-300E

Vendor:AVAGOD/C:07无铅

A3760-500E

Vendor:AVAGOD/C:07无铅

Hynix HYMD264726B(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris- ing and falling edges of it. The data paths are internally pi...

A3760-500E

Vendor:AVAGOD/C:07无铅

Hynix HYMD264726B(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris- ing and falling edges of it. The data paths are internally pi...

A3766P3

Vendor:CALMOSPackage Cooled:3.9mm

A memory cycle is initiated by bringing RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensure proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.

A37A-9

A37A-S

Vendor:NECD/C:07+

Dimensions are in inches. Metric equivalents are given for general information only. Beyond r (radius) maximum, TL shall be held for a minimum length of .011 inch (0.28 mm). Dimension TL measured from maximum HD. Body contour optional within zone defined by HD, CD, and Q. Leads at gauge plane .054 +.001 -.000 inch (1.37 +0.03 -0.00 mm) below seating plane shall be within .007 inch (0.18 mm) radius of ...

A38006

Vendor:MOTOROLAPackage Cooled:9018D/C:DIP16

The first step in choosing the right product is to select the diode type. All of the products in the HSMS-282x family use the same diode chip C they differ only in package configuration. The same is true of the HSMS-280x, -281x, 285x, -286x and -270x families. Each family has a different set of characteristics, which can be compared most easily by consult- ing the SPICE parameters given on each da...