A3959SLPT

Vendor:ALLEGROPackage Cooled:N/AD/C:6

All communications must be terminated by a stop condi- tion. The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. As with starts, stops are inhibited when outputting data and while a write is in progress.

A3959SLPTR

Vendor:ALLEGROPackage Cooled:04D/C:50

A3961SLB

Vendor:177Package Cooled:AQD/C:N/A

A3961SLV

Vendor:ALLEGROPackage Cooled:SOP24D/C:00+

GHA/GHB/GHC High-side, gate-drive outputs for external NMOS drivers. External series-gate resistors (as close as possible to the NMOS gate) can be used to control the slew rate seen at the power-driver gate, thereby controlling the di/dt and dv/dt of the SA/SB/SC outputs. Each output is designed and specified to drive a 1000 pF load with a rise time of 100 ns.

A3962SLB

Vendor:ALLEGROPackage Cooled:SOPD/C:N/A

In an NTSC composite video signal, horizontal sync pulses are followed by the back porch interval. The GS4882 and GS4982 generate a negative going pulse on pin 5 during this time. It is delayed typically 525 ns from the rising edge of sync and has a typical width of 2.5 µs.

A3964SLBTR

Vendor:ALLEGROPackage Cooled:7.2mm

The light-to-frequency converter reads an 8 x 8 array of photodiodes. Sixteen photodiodes have blue filters, 16 photodiodes have green filters, 16 photodiodes have red filters, and 16 photodiodes are clear with no filters. The four types (colors) of photodiodes are interdigitated to minimize the effect of non-uniformity of incident irradiance. All 16 photodiodes of the same color are connected in parallel...

A3964STB

Vendor:N/APackage Cooled:200

A3965

Vendor:ROHMPackage Cooled:40D/C:N/A

Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to ef- fectively execute within one cycle. If an instruc- tion changes the program counter, two cycles are required to complete the instruction.

A3966

Vendor:ALLEGROPackage Cooled:SOP

Each flip-flop can be triggered on either the rising or falling clock edge. The CLB clock line is shared by both flip-flops. However, the clock is individually invertible for each flip-flop (see CK path in Figure 3). Any inverter placed on the clock line in the design is automatically absorbed into the CLB.

A3966SA

Vendor:ALLEGROPackage Cooled:DIP/16

AL,BL,CL - Are the lowside logic level digital inputs. These three inputs control the three lowside bridge transistors. If the highside inputs are low, then the lowside inputs will control both the lowside and the highside of the bridge, with deadtime set by the SWR resistor. EN will override these inputs, forcing all outputs low. These inputs can be driven by logic up to 15V (less than VBIAS). An inter...

A3966SLB

Vendor:ALLEGROPackage Cooled:SOP-16D/C:N/A

The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltage- mode control with fast transient response. The switching regulator provides a maximum static regulation tolerance of 2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V.

A3966SLB-T

Vendor:in stockPackage Cooled:ALLEGROD/C:06+

Reset Output (RESET) RESET is an active LOW, open drain output which goes active whenever Vcc falls below the minimum Vtrip sense level. It will remain active until Vcc rises above the mini- mum Vtrip sense level for 150ms. RESET goes active if the Watchdog Timer is enabled and there is no start bit before the end of the selectable Watchdog time-out period. A serial start bit will reset the Watchdog T...

A3966SLBTR-P6

Vendor:ALLEGROPackage Cooled:SOPD/C:00+

The mounting area was reduced by mak- ing the two low-pass filters integrated in the two Tx paths into one component using LTCC technology. Also, etching technology can be used to perform com- plicated machining on the lead frame, which plays the role of interface between the internal components. That technology is used for the connections for the inter- nal low-pass filters in these products. Fur-...

A3966SLBTR-T

Vendor:ALLEGROPackage Cooled:SMDD/C:08+ROHS

Cycle-by-cycle current limiting, under-voltage lockout with hyster- esis, over-voltage protection, and thermal shutdown protects the power supply during the normal overload and fault conditions. Over-voltage protection and thermal shutdown are latched after a short delay. The latch may be reset by cycling the input supply. Low-current startup and a low-power standby mode selected from the secondary circ...

A3966SLBTR-XH

Vendor:ALLEGROPackage Cooled:SOPD/C:07+

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGHCtoCLOW edge of the S_LOAD input. See the programming section for more in...

A3966SLW

Vendor:ALLPPackage Cooled:SOP-16D/C:02+

FEATURES Single-Supply Operation: 7 V to 16 V Dual-Supply Operation: 3.5 V to 8 V Supply Current: 13 mA Max Upper/Lower Buffers Swing to VDD/GND Continuous Output Current: 10 mA VCOM Peak Output Current: 250 mA Offset Voltage: 15 mV Max Slew Rate: 6 V/ s Fast Settling Time with Large C-Load

A3966SLW

Vendor:ALLPPackage Cooled:SOP-16D/C:02+

FEATURES Single-Supply Operation: 7 V to 16 V Dual-Supply Operation: 3.5 V to 8 V Supply Current: 13 mA Max Upper/Lower Buffers Swing to VDD/GND Continuous Output Current: 10 mA VCOM Peak Output Current: 250 mA Offset Voltage: 15 mV Max Slew Rate: 6 V/ s Fast Settling Time with Large C-Load

A3967SLB-T

Vendor:ALLEGROPackage Cooled:SOP24D/C:08+

VCXOs are usually used as a narrowband local frequency source that is locked to some external frequency reference. The VCXO must have sufficient accuracy and pullability to be able to lock to that reference, and Absolute Pull Range is the measure of that ability. All the frequency errors of the VCXO are subtracted from the nominal pull range, and the remaining range can be guaranteed over all conditi...

A3967SLBTR

D/C:07+

In case of over-/undervoltage at Pin VS, an internal timer is started. When the overvolt- age delay time (tdOV) programmed by the SCT Bit, or the undervoltage delay time (tdUV) is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the S...

A3967SLBTR-T

Vendor:ALLEGROPackage Cooled:SMDD/C:08+ROHS

Notes: 1. Unless otherwise specified, these specifications apply for (VIN - VOUT) = 5.0V and IOUT = 1.5A. Although power dissipation is internally limited, these characteristics are applicable for power dissipation up to 30W. 2. Regulation is measured at a constant junction temperature using a pulse technique. Changes in output voltage due to heating effects are covered under the specification for therm...

A3967SLBTR-T

Vendor:ALLEGROPackage Cooled:SMDD/C:08+ROHS

Notes: 1. Unless otherwise specified, these specifications apply for (VIN - VOUT) = 5.0V and IOUT = 1.5A. Although power dissipation is internally limited, these characteristics are applicable for power dissipation up to 30W. 2. Regulation is measured at a constant junction temperature using a pulse technique. Changes in output voltage due to heating effects are covered under the specification for therm...

A3968SLBT

Vendor:ALLEGROPackage Cooled:SOPD/C:N/A

The Hitachi HN29W51214S Series is stacked 2 chips Hitachi 256-Mbit Flash memory (HN29W25611S) that are CMOS Flash Memory with AND type memory cells. It has fully automatic programming and erase capabilities with a single 3.3 V power supply. The functions are compatible with HN29W25611S Series and controlled by simple external commands. To fit the I/O card applications, the unit of programming and erase ...

A3968SLBT

Vendor:ALLEGROPackage Cooled:SOPD/C:N/A

The Hitachi HN29W51214S Series is stacked 2 chips Hitachi 256-Mbit Flash memory (HN29W25611S) that are CMOS Flash Memory with AND type memory cells. It has fully automatic programming and erase capabilities with a single 3.3 V power supply. The functions are compatible with HN29W25611S Series and controlled by simple external commands. To fit the I/O card applications, the unit of programming and erase ...

A3968SLBTR-T

Vendor:ALLEGROPackage Cooled:SOIC-16D/C:0644+

DISCUSSION OF TILT APPLICATIONS AND RESOLUTION Tilt Applications: One of the most popular applications of the MEMSIC accelerometer product line is in tilt/inclination measurement. An accelerometer uses the force of gravity as an input to determine the inclination angle of an object.

A3969SLP

Vendor:N/APackage Cooled:N/AD/C:08+09+

TSTG PD IOUT TSOLDER Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect ...

A3969SLP

Vendor:N/APackage Cooled:N/AD/C:08+09+

TSTG PD IOUT TSOLDER Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect ...

A3972SBT

Vendor:ALLEGROPackage Cooled:SMDD/C:07+

Together with separate aerials and tuners for each device, the combined performance of the connected demodulators will normally exceed a single device, especially in mobile applications or in areas where the signal is prone to echoes and/or fading.

A3972SBT

Vendor:ALLEGROPackage Cooled:SMDD/C:07+

Together with separate aerials and tuners for each device, the combined performance of the connected demodulators will normally exceed a single device, especially in mobile applications or in areas where the signal is prone to echoes and/or fading.

A3972SB-T

Vendor:ALLEGROPackage Cooled:SMDD/C:08+ROHS

Most of our DC tachometer generators aredesignedforcontinuousoperation inambienttemperaturesrangingfrom -55ºC to +100ºC. Voltage output at 25ºC will not deviate by more than 0.01% per degree of change within the range of -20ºC to +75ºC. All units are temperature compensated, with the exception of D-Series and E-Series tach generators.

A3974EDTR-T

D/C:08+/09+

The HT99C410 is an 8-bit high performance RISC-like microcontroller which combines HT48C50 8-bit microcontroller and 8-bit D/A converter in one chip. It is specifically designed for multiple I/O product applications. It also provides UV-erasable CERDIP window type version HT99C411C and OTP type version HT99C411, both support designers in making

A3974SED

Vendor:ALLEGROPackage Cooled:PLCC

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

A3974SEDT

Vendor:ALLEGROPackage Cooled:PLCC44D/C:05+

Each XC5200 CLB contains four independent 4-input func- tion generators and four registers, which are configured as four independent Logic Cells™ (LCs). The registers in each XC5200 LC are optionally configurable as edge-triggered D-type flip-flops or as transparent level-sensitive latches.

A3974SEDT

Vendor:ALLEGROPackage Cooled:PLCC44D/C:05+

Each XC5200 CLB contains four independent 4-input func- tion generators and four registers, which are configured as four independent Logic Cells™ (LCs). The registers in each XC5200 LC are optionally configurable as edge-triggered D-type flip-flops or as transparent level-sensitive latches.

A3975

Vendor:PLCCPackage Cooled:ALLEGROD/C:06+

A3975ED

Package Cooled:04+D/C:8

VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2A, IOUT2B = 0 V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP1177, ac performance with AD9631, unless otherwise noted. Temperature range for Y version is −40C to +125C.

A3976

Vendor:ALLEGROD/C:06+

INPUT CAPACITOR To improve load transient response and noise rejection an input bypass capacitor of at least 2.2µF is required. Generally it is recommended that a 20µF ceramic/tantalum or 22µF electrolytic capacitor be used.

A3976

Vendor:ALLEGROD/C:06+

INPUT CAPACITOR To improve load transient response and noise rejection an input bypass capacitor of at least 2.2µF is required. Generally it is recommended that a 20µF ceramic/tantalum or 22µF electrolytic capacitor be used.

A3976SLB

Vendor:ALLEGRPackage Cooled:07+D/C:800

A3977

Package Cooled:04+D/C:1

Wait or Transfer Acknowledge. When configured as wait, this signal is asserted low during a memory and peripheral device bus transaction to extend the bus cycle. When configured as transfer acknowledge, this signal is asserted low dur- ing a memory and peripheral device bus transaction to signal the completion of the transaction.

A3977KED-T

Vendor:ALLEGROPackage Cooled:44-lead PLCCD/C:07+

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate...

A3977SED-T

Vendor:in stockPackage Cooled:SMDD/C:06+

3. The turn-off time of Q1, or rise time of the standby input is not critical with these regulators. Turning Q1 off slowly, over periods up to 100ms, will not affect regulator operation. A slow turn-off time will merely increase both the initial delay and rise-time of the output voltage.

A3977SEDTR-T

Vendor:ALLEGROPackage Cooled:SMDD/C:08+ROHS

Rail-to-Rail Input and Output Small SOT-23 Package Gain Bandwidth Product: 10MHz C40C to 85C Operation Slew Rate: 2.25V/µs Low Input Offset Voltage: 1.5mV Max High Output Current: 25mA Min Specified on 3V, 5V and 5V Supplies High Voltage Gain: 1000V/mV 10k Load High CMRR: 88dB Min High PSRR: 80dB Min Input Bias Current: 300nA Max Input Offset Current: 25nA Max

A3977SEDTR-T

Vendor:ALLEGROPackage Cooled:SMDD/C:08+ROHS

Rail-to-Rail Input and Output Small SOT-23 Package Gain Bandwidth Product: 10MHz C40C to 85C Operation Slew Rate: 2.25V/µs Low Input Offset Voltage: 1.5mV Max High Output Current: 25mA Min Specified on 3V, 5V and 5V Supplies High Voltage Gain: 1000V/mV 10k Load High CMRR: 88dB Min High PSRR: 80dB Min Input Bias Current: 300nA Max Input Offset Current: 25nA Max

A3977SL

A3977SLPT

Vendor:ALLEGROPackage Cooled:07+D/C:800

While the busy signal is asserted, the host processor is free to perform other tasks (including running the print spooler). When the time slot is complete, the DS1481 restores both O1/BSY1 and O2/BSY2 to the states of I1 and I2 (see Figure 1).

A3977SLP-T

Vendor:N/APackage Cooled:SMDD/C:08+09+

The analog input RGB signals are first sampled by three channels of 8-bit A/D converters, and the 24-bit RGB data are then fed into the SD1010A. The SD1010A is capable of performing automatic detection of the display resolution and timing of input signals generated from various PC graphic cards. No special driver is required for the timing detection, nor any manual adjustment. The SD1010A then automaticall...

A3978LSP

Vendor:N/APackage Cooled:N/AD/C:08+09+

Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is refer- enced to the crossings of CK and /CK (both directions of crossing).

A3978SLP

Vendor:ALLEGROD/C:4

fOSC(tc)Oscillator frequency over line and temperature Trimmed for 360 kHz (1) Ensured by design. Not production tested. (2) Maximum 450-kHz frequency can be achieved when both channels are enabled. (3) 270 kHz is the default frequency during start-up for both channels. (4) See Table 1. (5) See PWM detailed description

A3978SLPT

Vendor:ALLEGROPackage Cooled:TSSOP28D/C:04+

Dynamically Adjustable Output from 0.3V to 3.5V 600mA Output Current Internal 0.08Ω P-Channel MOSFET Bypass Transistor High Efficiency: Up to 96% 1.5MHz Constant Frequency Operation No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle 2.5V to 5V Input Voltage Range Shutdown Mode Draws < 1µA Supply Current Current Mode Operation for Excellent Line and Load Transient Response O...

A3979SLPT

Vendor:ALLEGROPackage Cooled:0734+D/C:TSOP

VBIAS (VCC, VBS) = 12V, CL = 1000 pF, CT = 1 nF and TA = 25C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.

A397M

n Sector Protection C Any combination of sectors may be locked to prevent program or erase operations within those sectors n Temporary Sector Unprotect C Allows changes in locked sectors (requires high voltage on RESET# pin) n Internal Erase Algorithm C Automatically erases a sector, any combination of sectors, or the entire chip n Internal Programming Algorithm C Automatically programs ...

A397PA

A397PB

The device is designed to accept video signals from an auxiliary SCART connector, TV SCART connector, and an external video encoder/DAC device. The devices include a set of analog multiplexers that receive video signals from these sources and allow routing of the signals to the various video outputs. The video output drivers have a nominal gain of 2.0 V/V to allow for a series resistance of 62 ohms prior to...

A397TSLP

Vendor:ALLEGROPackage Cooled:TSSOP-28D/C:2004

A3980KLP

Vendor:ALLEGROPackage Cooled:TSSOP-28D/C:N/A

Internal registers include available capacity, temperature, scaled avail- able energy, battery ID, battery status, and programming pin set- tings. To support subassembly test- ing, the outputs may also be con- trolled. The external processor may also overwrite some of the bq2050 power gauge data registers.

A3982SLBT

Vendor:ALLEGROPackage Cooled:SOPD/C:N/A

(1) All typical values are at TA = +25C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the transfer curve for VIN = 0V to VREF or 0.1V to VDD − 0.2V, expressed either as the number of LSBs or as a percent of measured input range. (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the full specified temperatu...

A3983LPT

Vendor:ALLEGROPackage Cooled:TSSOP24D/C:04+

A3983LPT

Vendor:ALLEGROPackage Cooled:TSSOP24D/C:04+

A3983SLPT

Vendor:ALLEGROPackage Cooled:TSSOP

The MX803A is an audio signaling processor that provides inband tone signaling capabilities for LMR and other Radio systems. A low-power CMOS device, the MX803A is a member of the DBS800 (Digitally integrated Baseband Sub- system) IC family (See section 4.2). Supported Signaling systems include SelCall (CCIR, EEA, ZVEI I, II, and III) 2-Tone SelCall and DTMF encode. The use of a non-predictive decoder and...

A3985SLD-T

Vendor:ALLEGROD/C:08+ROHS

LOGIC INPUTS (CLK, PDWN) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance DIGITAL OUTPUTS (D0CD11, OTR)1 DRVDD = 3.3 V High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOH = 1.6 mA) Low Level Output Voltage (IOH = 50 µA) DRVDD = 2.5 V High Level Outpu...

A3986SLDT

Vendor:300Package Cooled:SMD

"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.

A3988SEV-TR-T

A3992SB-T

Vendor:ALLEGROD/C:08+ROHS

The MLX90247DSG sensor IC is integrated together with a PTC thermistor. The thermopile sensor is grounded at the middle point, so that the output common-mode voltage is at ground potential. Using grounded thermopile sensor gives improved EMC susceptibility in some applications.

A3992SB-T

Vendor:ALLEGROD/C:08+ROHS

The MLX90247DSG sensor IC is integrated together with a PTC thermistor. The thermopile sensor is grounded at the middle point, so that the output common-mode voltage is at ground potential. Using grounded thermopile sensor gives improved EMC susceptibility in some applications.

A3993

Vendor:N/APackage Cooled:40D/C:N/A

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.

A39TTSLPT

D/C:08+/09+

A3B2841-5

Built-in H and V driving circuit (built-in input level conversion circuit, TTL drive possible) High quality picture representation with RGB delta arranged color filters Full-color representation NTSC/PAL/WID compatible Up/down and/or right/left inverse display function Side-black function 16:9 and 4:3 aspect switching function

A3B2850-5

The ISL6434 provides the power control and protection for four output voltages in high-performance, graphics intensive gateway microprocessor applications. The IC integrates two PWM controllers and two linear controllers, as well as the monitoring and protection functions into a 28-lead SOIC package. One PWM controller regulates the microprocessor core voltage with a synchronous-rectified buck converte...

A3CA259C

Vendor:QFP-32Package Cooled:.D/C:2004+

s Intended for Radio Frequency (RF) front end applications in the GHz range, such as: x analog and digital cellular telephones x cordless telephones (Cordless Telephone (CT), Personal Communication Network (PCN), Digital Enhanced Cordless Telecommunications (DECT), etc.) x radar detectors x pagers x Satellite Antenna TeleVision (SATV) tuners

A3CA295A

D/C:02

This device is designed with discrete diodes for complete isolation. Each diode can be individually tested according to the electrical characteristics. For transient voltage protection, two diodes are configured in series with the anode of one connect to the cathode of the other diode (See Rail Clamp Circuit).

A3CA322A

Vendor:ALPSPackage Cooled:TQFP32D/C:1998

CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block 1, Parameter Block 2, Main Memory Block 1, and Main Mem- ory Block 2 but not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any command during chip erase will be...

A3CL-3A

A3DA292B

Vendor:ALPS

A3DL-3A1

A3-DWC010

Vendor:TOSHIBAPackage Cooled:SOT-23D/C:08+

Low-power consumption modes (standby modes) Stop mode (As all oscillations halt in sub-clock mode, current consumption falls to almost zero.) Sleep mode (The CPU stops to reduce the current consumption to approximately 1/3 of normal.) Clock mode (All operation halts other than the clock prescaler resulting in very low power consumption.)

A3-DWC010-TE

Vendor:TOSHIBAPackage Cooled:SOT-143D/C:08+

Hynix HYMD264646B(L)8J-J series is designed for high speed of up to 166MHz and offers fully synchronous opera- tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelin...

A3G2-9

A3KR16-8

A3P060-FGG144

Vendor:ACTELPackage Cooled:N/AD/C:06+

The Hynix HYM71V16M655B(L)T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The Hynix HYM71V16M655B(L)T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

A3P1000-FG256I

Vendor:ActelPackage Cooled:FBGA256LD/C:06+

A3P250PQG208

Vendor:ActelPackage Cooled:PQFP208LD/C:06+

A3P250-PQG208

Vendor:100

The Si9712 operates off the 5-V supply and has built-in level shifting for gate drive. Internal logic protects against an external control input error that would short 5 V to the 3.3-V supply. This protection logic also allows the Si9712 to be configured for positive or negative control logic for compatibility with a variety of PC Card controllers. These control inputs are CMOS logic compatible and can...

A3P250-PQG208

Vendor:100

The Si9712 operates off the 5-V supply and has built-in level shifting for gate drive. Internal logic protects against an external control input error that would short 5 V to the 3.3-V supply. This protection logic also allows the Si9712 to be configured for positive or negative control logic for compatibility with a variety of PC Card controllers. These control inputs are CMOS logic compatible and can...

A3P600PQ208I

A3PA5702-12E

A3PA5702-24E

A3PJ-4102

A3RS624

A3RS628

A3V400IP

A3W-K

Vendor:TAKAMISAWAPackage Cooled:relayD/C:09+

A3XH06

A3Y01618

A3Y02411

A-4.000-20

A4000

Vendor:300

A400056C

Vendor:UEMPackage Cooled:SOPD/C:N/A

The UCC1800/1/2/3/4/5 family of high-speed, low-power integrated cir- cuits contain all of the control and drive components required for off-line and DC-to-DC fixed frequency current-mode switching power supplies with minimal parts count.

A400056C

Vendor:UEMPackage Cooled:SOPD/C:N/A

The UCC1800/1/2/3/4/5 family of high-speed, low-power integrated cir- cuits contain all of the control and drive components required for off-line and DC-to-DC fixed frequency current-mode switching power supplies with minimal parts count.

A-400056-C

Package Cooled:05+D/C:SMD

True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Frequency select pin, see Frequency table for functionality This pin establishes the reference current for the differential current- mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the stan...

A-400056-C

Package Cooled:05+D/C:SMD

True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Frequency select pin, see Frequency table for functionality This pin establishes the reference current for the differential current- mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the stan...