B39440X6866D100

Vendor:EPCOSPackage Cooled:N/AD/C:03PB

Host Bus Address Bit [15:1] : In 32 bit mode, H16_32=0, all host accesses are 32 bit wide. When H16_32=1, all host accesses are 16 bit wide. (Internal pull-up). A11, A10, A9, A8 has other definition in MII mode. Host Bus Address Bit11, when on-chip tranceiver is used, it is used in A[15:1], when in MII mode, it is defined as receive clock RXC (25MHz or 2.5MHz) When this pin is used as address bit, it...

B39440-X6866-D100

Vendor:EPCOSPackage Cooled:N/AD/C:03PB

• Industry Standard Size • Industry Standard Pinout 7.62 mm (0.300 inch) DIP Leads on 2.54 mm (0.100 inch) Centers • Choice of Colors Red, AlGaAs Red, High Efficiency Red, Yellow, Green • Excellent Appearance Evenly Lighted Segments Gray Package Gives Optimum Contrast 50 Viewing Angle • Design Flexibility Common Anode or Common Cathode Single Digits ...

B39440-X6866-D100

Vendor:EPCOSPackage Cooled:N/AD/C:03PB

• Industry Standard Size • Industry Standard Pinout 7.62 mm (0.300 inch) DIP Leads on 2.54 mm (0.100 inch) Centers • Choice of Colors Red, AlGaAs Red, High Efficiency Red, Yellow, Green • Excellent Appearance Evenly Lighted Segments Gray Package Gives Optimum Contrast 50 Viewing Angle • Design Flexibility Common Anode or Common Cathode Single Digits ...

B39458-M1967-D100 SIP5D

B39481B710B510

B39609.1

Vendor:AMISPackage Cooled:QFP100D/C:06+

B39841-B4132-U410

Vendor:EPCOSD/C:01+

This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

B39841-B7723-C610

Vendor:EPCOSPackage Cooled:08+D/C:1619

No Auxiliary Winding Operation Internal Output Short−Circuit Protection Extremely Low No−Load Standby Power Current−Mode with Skip−Cycle Capability Internal Leading Edge Blanking 250 mA Peak Current Source/Sink Capability Internally Fixed Frequency at 40 kHz, 60 kHz and 100 kHz Direct Optocoupler Connection Built−in Frequency Jittering for Lower EMI SPICE Models Available...

B39850-B4914-Z510

Vendor:EPCOSPackage Cooled:00+D/C:15000

address is wrapped around to point to the beginning of that page. If the master transmits more than 16 bytes prior to generating the STOP condition, no acknowledge will be given on the 17th (and following) data bytes and the whole transmission will be ignored and no programming will be done. As in the byte write operation, all inputs are disabled until completion of the internal write cycles.

B39850-B4914-Z510

Vendor:EPCOSPackage Cooled:00+D/C:15000

address is wrapped around to point to the beginning of that page. If the master transmits more than 16 bytes prior to generating the STOP condition, no acknowledge will be given on the 17th (and following) data bytes and the whole transmission will be ignored and no programming will be done. As in the byte write operation, all inputs are disabled until completion of the internal write cycles.

B39860-B4858Z710

Vendor:EPCOSD/C:0+

The SSM2120 contains two independent level detection circuits. Each circuit contains a wide dynamic range full-wave rectifier, logging circuit and a unipolar drive amplifier. These circuits will accurately detect the input signal level over a 100 dB range from 30 nA to 3 mA peak-to-peak.

B39860-B4858-Z710

Vendor:EPCOSPackage Cooled:02D/C:41629

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input ...

B39871B3571U310

B39871B3715U410

B39881B4125U410

Vendor:epcosPackage Cooled:epcosD/C:dc01

CAUTION: Stress above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied.

B39881-B7630-D710

Vendor:EPCOSPackage Cooled:05+D/C:SMD

B39881-B7630-D710(4.84.8)

B39881-B7701-K910

Vendor:EPCOSPackage Cooled:05+D/C:8790

FEATURES D Data Rate: 1.25MSPS D Signal-to-Noise Ratio: 93dB D Total Harmonic Distortion: −101dB D Spurious-Free Dynamic Range: 103dB D Linear Phase with 615kHz Bandwidth D Passband Ripple: 0.0025dB D Adjustable FIFO Output Buffer (ADS1626 only) D Selectable On-Chip Reference D Directly Connects to TMS320C6000 DSPs D Adjustable Power Dissipation: 150 to 515mW D Power Down Mode D Supplies: Analog +5V

B39881-B7842-C710

Vendor:EPCOSPackage Cooled:50224D/C:7840

The device offers a highly integrated solution for a satellite tuner incorporating a low phase noise PLL frequency synthesizer, the quadrature down converter, a fully integrated local oscillator, and programmable baseband channel filters. A minimal number of additional peripheral components are required. The crystal reference source can be also used as the reference for the demodulator.

B39901-B4015-Z610

Vendor:EPCOSPackage Cooled:CLCC

B39921B3588U410

B39921B3705Z810

B39921R2706U310

B39931B4029Z810

B39941-B4104-2610

Vendor:EPCOSPackage Cooled:N/AD/C:6

Dir (pin 3) This pin determines the sequence that the outputs will be energized in. A high input on the Dir pin while the step input is pulsed will cause a single clockwise step, while a low level will cause a counter-clockwise step. (Refer to Figures 1 & 2). Dir must be at a stable level prior to the low to high transition of Step in order to be recognized (refer to the Tsu specification).

B39941-B4104-Z610

Vendor:EPCOSD/C:.

Note 10: VIN is compared to the programmed output voltage (VOUT). When VINCVOUT falls below VBYPASS− for longer than TBYP the Bypass FET turns on and the switching FETs turn off. This is called the Bypass mode. Bypass mode is exited when VINCVOUT exceeds VBYPASS+ for longer than TBYP, and PWM mode returns. The hysterisis for the bypass detection threshold VBYPASS+ C VBYPASS− will always be pos...

B39941-B4104-Z610

Vendor:EPCOSD/C:.

Note 10: VIN is compared to the programmed output voltage (VOUT). When VINCVOUT falls below VBYPASS− for longer than TBYP the Bypass FET turns on and the switching FETs turn off. This is called the Bypass mode. Bypass mode is exited when VINCVOUT exceeds VBYPASS+ for longer than TBYP, and PWM mode returns. The hysterisis for the bypass detection threshold VBYPASS+ C VBYPASS− will always be pos...

B39941-B4115-U510

Vendor:EPCOSPackage Cooled:00+D/C:21993

The output of these devices (pin 3) switches low when the magnetic field at the Hall sensor exceeds the operate point threshold (BOP). At this point, the output voltage is VOUT(SAT). When the magnetic field is reduced to below the release point (BRP) the device output goes high. Note especially that release can occur when the magnetic field is removed but to ensure release, a field reversal is requir...

B39941-B4116-U410

Vendor:EPCOSD/C:0243

Using a CT by itself normally introduces a current lag, typically observed at between 2 to 3. Introducing a capacitor across the CT, as was done in this design, provides a current lead that is correctable with timing adjustment. It is not necessary to quantify the amount of lead; as long as it is present, it can be measured indirectly through meter error and compensated.

B39941-B4119-U510

B39941-B4127-U10

Vendor:EPCOSD/C:00+

Bits D7 and D6 in the register must be set low, and bits D5 through D0 control the gain range in 64 increments. See fig- ure for a graph of the PGA gain versus PGA register code. The coding for the PGA register is straight binary, with an all zero words corresponding to the minimum gain setting (1x) and an all one word corresponding to the maximum gain setting (5.85x).

B39941B4127U410

Vendor:EPCOSPackage Cooled:2005D/C:500

The DS1809 will also support a command-initiated wiper storage operation during powered conditions. For command initiated storage the STR pin should be held in a low state on power-up; otherwise the part will assume an autostore configuration. As shown in Figure 5, a low-to-high pulse lasting at least 1 µs on the STR input will cause the DS1809 to initiate the storage of the current wiper position into...

B39941-B4127-U410

Vendor:EPCOSPackage Cooled:00+D/C:18913

Each port has a current-limited 100-mΩ N- channel MOSFET high-side power switch for 500 mA self-powered operation. Each port also has a current-limited 500-mΩ N-channel MOS- FET high-side power switch for 100-mA bus- powered operation. All the N-channel MOSFETs are designed without parasitic diodes, preventing current backflow into the inputs.

B39941-B4127-U410

Vendor:EPCOSPackage Cooled:00+D/C:18913

Each port has a current-limited 100-mΩ N- channel MOSFET high-side power switch for 500 mA self-powered operation. Each port also has a current-limited 500-mΩ N-channel MOS- FET high-side power switch for 100-mA bus- powered operation. All the N-channel MOSFETs are designed without parasitic diodes, preventing current backflow into the inputs.

B39941-B7611-A310

Vendor:EPCOSPackage Cooled:BGAD/C:N/A

Parameter TEC CURRENT MEASUREMENT ITEC Gain ITEC Output Range ITEC Input Range ITEC Bias Voltage ITEC Output Current TEC VOLTAGE MEASUREMENT VTEC Gain VTEC Output Range VTEC Bias Voltage VTEC Output Current VOLTAGE LIMIT VLIM Gain VLIM Input Range VLIM Input Current, cooling VLIM Input Current, heating VLIM Input Current Accuracy, heating CURRENT LIMIT ILIMC Input Voltage Range ILIMH Input Volt...

B39941-B7611-A310

Vendor:EPCOSPackage Cooled:BGAD/C:N/A

Parameter TEC CURRENT MEASUREMENT ITEC Gain ITEC Output Range ITEC Input Range ITEC Bias Voltage ITEC Output Current TEC VOLTAGE MEASUREMENT VTEC Gain VTEC Output Range VTEC Bias Voltage VTEC Output Current VOLTAGE LIMIT VLIM Gain VLIM Input Range VLIM Input Current, cooling VLIM Input Current, heating VLIM Input Current Accuracy, heating CURRENT LIMIT ILIMC Input Voltage Range ILIMH Input Volt...

B39941B7612A110

Vendor:EPCOSPackage Cooled:SMDD/C:2004

B39941-B7705-B610

Vendor:EPCOSPackage Cooled:02+D/C:13800

NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 13. All loading with 50 Ω to VCC−2.0 volts....

B39941-B7705-B610(942.500MHZ)

Vendor:EPCOSPackage Cooled:2005 PBD/C:6000

The matte tin finish on Sirenzas lead-free package utilizes a post annealing process to mitigate tin whisker formation and is RoHS Product Features compliant per EU Directive 2002/95. This package is also manu- • Now available in Lead Free, RoHS factured with green molding compounds that contain no antimony Compliant, & Green Packaging trioxide nor halogenated fire retardants.

B39941-B7705-N610

Vendor:EPCOS ?Package Cooled:N/A?D/C:7062

Supply current and output power are a function of the voltage input on the PC (power control) pin. All specifications in the Electrical Charac- teristics table applies for condition VPC = 350mV. Increasing the voltage on the PC pin will increase transmit power and also increase MARK supply current. Refer to the graphs "Output Power Versus PC Pin Voltage" and "Mark Current Versus PC Pin Voltag...

B39941-B7706-B610

Vendor:EPCOSPackage Cooled:04+D/C:5050

The Ultra37000 devices operate with a 5V supply and can support 5V or 3.3V I/O levels. VCCO connections provide the capability of interfacing to either a 5V or 3.3V bus. By connecting the VCCO pins to 5V the user insures 5V TTL levels on the outputs. If VCCO is connected to 3.3V the output levels meet 3.3V JEDEC standard CMOS levels and are 5V tolerant. These devices require 5V ISR programming.

B39941-B7706-B610

Vendor:EPCOSPackage Cooled:04+D/C:5050

The Ultra37000 devices operate with a 5V supply and can support 5V or 3.3V I/O levels. VCCO connections provide the capability of interfacing to either a 5V or 3.3V bus. By connecting the VCCO pins to 5V the user insures 5V TTL levels on the outputs. If VCCO is connected to 3.3V the output levels meet 3.3V JEDEC standard CMOS levels and are 5V tolerant. These devices require 5V ISR programming.

B39941-B7706-B610(2.02.5 5P)

B39941B7820C710

Vendor:EPCOS

An interface to low-cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables.

B39941-B7820-C710

D/C:279

manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM. These pins are de-multi- plexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet.

B39941-B7820-C710

D/C:279

manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM. These pins are de-multi- plexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet.

B39941-B7833-C710

Vendor:EPCOSPackage Cooled:05+D/C:6205

With the XC9105 series, the CE pin also serves as a PWM/PFM switching pin. In operation, PWM control is selected when the voltage at the CE pin is more than VDD -0.2V. On the other hand, PWM/PFM automatic switching control at a duty = 25% is selected when the voltage at the CE pin is less than VDD -1.0V and more than VCEH.

B39941-B7833-C710

Vendor:EPCOSPackage Cooled:05+D/C:6205

With the XC9105 series, the CE pin also serves as a PWM/PFM switching pin. In operation, PWM control is selected when the voltage at the CE pin is more than VDD -0.2V. On the other hand, PWM/PFM automatic switching control at a duty = 25% is selected when the voltage at the CE pin is less than VDD -1.0V and more than VCEH.

B39951-B4647-Z610

B39951-B4678-Z810

The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter- nally pipelined and 2-bit prefetched to achieve very high ...

B39A12C19.44MHZ

B3A-1.24-1-2W

B3BB2

Package Cooled:TSSOP8D/C:04+

The DRV593 and DRV594 are high-efficiency, high-current power amplifiers ideal for driving a wide variety of thermoelectric cooler elements in systems powered from 2.8 V to 5.5 V. The operation of the device requires only one inductor and capacitor for the output filter, saving significant printed-circuit board area. Pulse-width modulation (PWM) operation and low output stage on-resistance significan...

B3BB3

Package Cooled:MSOP8D/C:04+

• Measures local and remote temperature • Highly accurate remote sensing 1C max., 60C to 100C • Superior noise immunity for reduced temperature guard- bands • 9-bit to 12-bit temperature resolution for remote zone • Fault queues to further reduce nuisance tripping • Programmable high, low, and over-temperature thresh- olds for each zone • SMBus 2 compatible ser...

B3BB5

Package Cooled:MSOP8D/C:06+

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C

B3BB8

Package Cooled:MSOP8D/C:04+

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and arenot referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3. /WE is high for the read cycle.

B3BBB

PG# (15) The PG# pin is an open-drain, active-low output with no internal pull-up resistor. It can be used to switch a load or enable a DC/DC converter. PG# is enabled immediately after VGATE reaches VDD C VGT and the DRAIN SENSE voltage is less than 2.5V. Voltage on these pins cannot exceed 12V, as referenced to VSS.

B3BBC

Temperature coefficients Silicon resistors are very temperature dependent. The overall drift of the resistors is not of interest to most users (The bridge resistors are located on the same die). The temperature coefficients of the offset and span, however, are very important. All the temperature coefficients are given in percentage of full-scale range (FS) and over a temperature range of 100 C.

B3BBD

The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on- resistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application.

B3BBD

The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on- resistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application.

B3BBF

15) Sweep the power supply to 5.5V. Verify that the LED module remains off, VOUT is approximately 23.5V, and VPOK tracks VVIN. 16) Set the power supply to 3.3V. 17) Push the button on the bottom of the EV kit. This enables a strobe/flash. 18) Verify that the LED module flashes.

B3BBG(D)

The PCI subsystem is a bus master interface that performs the memory accesses to keep the Audio cache buffers full and empties the A/D Converter (or I2S input) buffer to main memory as required. The fundamental concept of AudioPCI 97 is that the PCI interface controller has a sufficiently large internal (on-chip) memory cache to meet the memory bandwidth requirements. There is a Sound Cache block of 64 b...

B3BBH

Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay DAC Register Load Pulse Width PRESET Pulse Width Clock Edge to Load Rising Edge Clock Edge to Load Falling Edge Load Falling Edge to SDO Tri-state Enable Load Rising Edge to SDO Tri-state Disable Load Falling Edge to CLK Disable Load Rising Edge to CLK Enable LD Set-up Time with Respect to CLK

B3BBJ

The most important connection to make to the MAX2601/MAX2602 is the back side. It should connect directly to the PC board ground plane if it is on the top side, or through numerous plated through-holes if the ground plane is buried. For maximum gain, this con- nection should have very little self-inductance. Since it is also the thermal path for heat dissipation, it must have low thermal impedance, and the g...

B3BBK

The SN74LVT16646 is available in TIs shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

B3BBL

Features 1) Detection voltage: 0.1V step line-up 2.3~6.0V (Typ.) 2) High-accuracy detection voltage:1.5% (Max.) 3) Ultra low current consumption: 0.95µA (Typ.) 4) Nch open drain output (BD52XXG/FVE series), CMOS output (BD53XXG/FVE series) 5) Small VSOF5(EMP5), SSOP5(SMP5C2) package

B3BBM

The B3BBM consists of 4 independent low noise, low current inverting operational amplifiers utilizing Gennum's low voltage bipolar JFET technology. Each amplifier has a minimum open loop gain of 46 dB with the closed loop gain set by the ratio of a feedback (RF) resistor to the source impedance (RS) . For a well controlled gain tolerance from amplifier to amplifier, it is recommended that the closed loop gain...

B3BBN

• Low current consumption by CMOS process with high dielectric strength (30V) • Standby current of 2µA or less (at Vcc=14V), and operating current of 1.5mA (typ) • Overvoltage protection function detecting the Vcc voltage • A drive circuit for connecting a power MOSFET directly • Output peak current: 1.5A • Pulse-by-pulse overcurrent limiting function •...

B3BBQ

Up to 10-A Output Current 12-V Input Voltage Wide-Output Voltage Adjust (1.2 V to 5.5 V)/(0.8 V to 1.8 V) Efficiencies up to 95% 225 W/in3 Power Density On/Off Inhibit Output Voltage Sense Margin Up/Down Controls Undervoltage Lockout Auto-Track™ Sequencing Output Overcurrent Protection (Non-latching, Auto-Reset) Operating Temperature: C40C to 85C Safety Agency Approvals: UL 60950, cUL 600950, E...

B3BBR

Thermal Ground FBAR resonators have a negative temperature coefficient of frequency as temperature goes up, the frequency response of the filter shifts down in frequency. See Figure 12. Typical coeffi- cients are 57 KHz/ C for the Tx filter and 40 KHz/ C for the Rx filter. In Figure 13, the same data are presented with the scale narrowed down to the upper end of the Tx band. Note that all these data a...

B3BBS

Vendor:N/APackage Cooled:8D/C:02/03+

The TMS4x100 and TMS4x100P are offered in a 20- / 26-lead plastic surface-mount small-outline ( TSOP) package (DGA suffix) and a 300-mil 20- / 26-lead plastic surface-mount SOJ package (DJ suffix). Both packages are characterized for operation from 0C to 70C.

B3BBS

Vendor:N/APackage Cooled:8D/C:02/03+

The TMS4x100 and TMS4x100P are offered in a 20- / 26-lead plastic surface-mount small-outline ( TSOP) package (DGA suffix) and a 300-mil 20- / 26-lead plastic surface-mount SOJ package (DJ suffix). Both packages are characterized for operation from 0C to 70C.

B3BBT

Vendor:N/APackage Cooled:20D/C:02/03+

VREF_ = 20Vp-p, 10kHz sine wave, latches loaded with all 0s VREF = 100mVp-p sine wave, DAC latch loaded with all 1s VREF = 20Vp-p Sine wave, DAC latch loaded with all 1s VREF = 6VRMS, 1kHz, DAC latch loaded with all 1s Code transition from all 0s to all 1s; see Typical Operating Characteristics graphs

B3BBV

Vendor:N/APackage Cooled:30D/C:02/03+

The low-cost ADS-950 is an 18-bit, 500kHz sampling A/D converter. This device accurately samples full-scale input signals up to Nyquist frequencies with no missing codes. This feature, combined with excellent signal-to-noise ratio (SNR) and total harmonic distortion (THD), makes the ADS-950 the ideal choice for both time-domain (medical imaging, scanners, process control) and frequency-domain (radar, t...

B3BBV

Vendor:N/APackage Cooled:30D/C:02/03+

The low-cost ADS-950 is an 18-bit, 500kHz sampling A/D converter. This device accurately samples full-scale input signals up to Nyquist frequencies with no missing codes. This feature, combined with excellent signal-to-noise ratio (SNR) and total harmonic distortion (THD), makes the ADS-950 the ideal choice for both time-domain (medical imaging, scanners, process control) and frequency-domain (radar, t...

B3BBW

Package Cooled:TSSOP8D/C:04+

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAC, 3990 East Broad St., Columbus, OH 43216-5000, by using the addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

B3BBW

Package Cooled:TSSOP8D/C:04+

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAC, 3990 East Broad St., Columbus, OH 43216-5000, by using the addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

B3BBX

Package Cooled:TSSOP8D/C:04+

This is a family of products based on the most advance CMOS mixed signal technology. It inte- grates image array, signal processing, timing and control circuitry, all on a single chip, enabling all aspects of B/W video camera applications. It is ideal for applications requiring a small footprint, low power and low cost.

B3BBX

Package Cooled:TSSOP8D/C:04+

This is a family of products based on the most advance CMOS mixed signal technology. It inte- grates image array, signal processing, timing and control circuitry, all on a single chip, enabling all aspects of B/W video camera applications. It is ideal for applications requiring a small footprint, low power and low cost.

B3BBZ

Package Cooled:TSSOP8D/C:04+

Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

B3BCB

Vendor:N/APackage Cooled:12D/C:02/03+

When applying signals to RECIN (rectifier input) an input series resistor should be followed by a low leakage blocking capacitor since RECIN has a dc voltage of approximately 2.1 V above ground. Choose RIN for a 1.5 mA peak signal. For 15 V operation this corresponds to a value of 10 kΩ.

B3BCC

Vendor:N/APackage Cooled:29D/C:02/03+

The MAX2640/MAX2641 are low-cost, ultra-low-noise amplifiers designed for applications in the cellular, PCS, GPS, and 2.4GHz ISM frequency bands. Operating from a single +2.7V to +5.5V supply, these devices consume only 3.5mA of current while providing a low noise fig- ure, high gain, high input IP3, and an operating fre- quency range that extends from 400MHz to 2500MHz. The MAX2640 is optimized for 400MHz t...

B3BCF

The MAX186/MAX188 provide a hard-wired SHDN pin and two software-selectable power-down modes. Accessing the serial interface automatically powers up the devices, and the quick turn-on time allows the MAX186/MAX188 to be shut down between every conversion. Using this technique of powering down between conversions, supply current can be cut to under 10µA at reduced sampling rates.

B3BCF

The MAX186/MAX188 provide a hard-wired SHDN pin and two software-selectable power-down modes. Accessing the serial interface automatically powers up the devices, and the quick turn-on time allows the MAX186/MAX188 to be shut down between every conversion. Using this technique of powering down between conversions, supply current can be cut to under 10µA at reduced sampling rates.

B3BCG

The standard device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to oper- ate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

B3BCH

The Agilent 54830D Series Mixed-Signal Oscilloscopes unique- ly combine the detailed signal analysis of a high-performance scope with the 16-channel timing measurements of a logic analyzer, plus the benefits of fast, usable, and affordable MegaZoom deep memory.

B3BCJ

Input coupling capacitor which blocks the DC voltage at the amplifiers input terminals. Also creates a high-pass filter with Ri at fc = 1 / (2RiCi). Refer to the section Proper Selection of External Components, for an explanation of how to determine the value of Ci.

B3BCK

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance3-stateandincreased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly a...

B3BCL

The SD1010A also provides distinguished system features to the TFT LCD monitor solution. The first one is plug-and-play, and the second one is cost-effective system solution. To be truly plug-and-display, the SD1010A performs automatic input mode detection and auto phase calibration, so the LCD monitor can ensure that the A/D converters sample clock is precisely synchronized with the input video data, and to...

B3BCL

The SD1010A also provides distinguished system features to the TFT LCD monitor solution. The first one is plug-and-play, and the second one is cost-effective system solution. To be truly plug-and-display, the SD1010A performs automatic input mode detection and auto phase calibration, so the LCD monitor can ensure that the A/D converters sample clock is precisely synchronized with the input video data, and to...

B3BCP

Interfaces 8 E1/T1/J1 ports UTOPIA Interfaces (level 1 and 2, ATMF AF-PHY 0017.000, 0039.000) - Line side 155 Mbit/s throughput, ATM device - Backplane side 622 Mbit/s throughput, Multi Phy device 16/32-bit Microcontroller Interface (Intel or Motorola type)

B3B-PH-K

Vendor:JST

RF input pin. This pin is NOT internally DC blocked. A DC blocking capacitor, suitable for the frequency of operation, should be used in most applications. DC coupling of the input is not allowed, because this will override the internal feedback loop and cause temperature instabil- ity. Same as pin 1.

B3B-PH-SM3-TB

Vendor:JSTPackage Cooled:08+D/C:1000

CMOS Technology Low Power Consumption 4-Bit or 8-Bit MPU Interface High Speed MPU Interface: 2MHz (VDD =5V) 80 x 8-Bit Display RAM (80 characters max.) Auto Reset Function 5 x 8 and 5 x 10 Dot Matrix Built-in Oscillator with External Resistors Programmable Duty Cycle: - 1/8 Duty: (1 Display Line, 5 x 8 Dots with Cursor) - 1/11 Duty: (1 Display Line, 5 x 10 Dots with Cursor) - 1/16 Duty: (2 Display Lines,...

B3B-ZR-SM3F-TF-A

Vendor:JSTD/C:05+

B3B-ZR-SM3-TF

Vendor:JSTD/C:.

The ceramic resonator of the stereo decoder PLL circuit is used as a stop signal detector for AM signals. For this purpose, the parallel resonance frequency of the resonator, which is unloaded about 456 kHz, is reduced by an internal load capacitor down to 455 kHz. Therefore, the AM IF must be 455 kHz. The internal loading capacitor is defined by the current through AMSADJ (Pin 9) to GND. An external ...

B3B-ZR-SM4-TF(Z)

Vendor:JSTPackage Cooled:08+D/C:1000

B3-ES

Vendor:InfineonPackage Cooled:06+

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, TA = 25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Measured by the voltage drop between A and B pin at indicated current through the switc...

B3F-1000

Vendor:OMRONPackage Cooled:switch

This simple measurement arrangement is suited to many applications. There are, however, limitations to this basic approach. Input current continues to flow through S2 during the reset period. This leaves a small voltage on C INT equal to the input current times R S2, the on-resistance of S2, approximately 1.5kΩ.

B3F-1005

Vendor:OMRONPackage Cooled:switch

2. Powerful instruction set (129 instructions). Binary addition, subtraction, BCD adjust, logical operation in direct and index addressing mode. Single-bit manipulation (set, reset, decision for branch). Various conditional branch. 16 working registers and manipulation. Table look-up. LCD driver data transfer.

B3F-1005

Vendor:OMRONPackage Cooled:switch

2. Powerful instruction set (129 instructions). Binary addition, subtraction, BCD adjust, logical operation in direct and index addressing mode. Single-bit manipulation (set, reset, decision for branch). Various conditional branch. 16 working registers and manipulation. Table look-up. LCD driver data transfer.