BUS-1209

Vendor:GROUP-TEKPackage Cooled:DIP23D/C:93+

BUS12A

Vendor:国产/进口Package Cooled:TO-3D/C:09

Differential output for the synthesizer. LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low, and the inver ted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial ...

BUS131A

Vendor:availPackage Cooled:STD/C:05+

VERTICAL SYNC OUTPUT A vertical sync output is derived by internally integrating the composite sync waveform (Figure 2). To understand the generation of the vertical sync pulse, refer to the lower left hand section Figure 2. Note that there are two comparators in the section. One comparator has an internally generated voltage reference called V1 going to one of its inputs. The other comparator has an ...

BUS132(H)

Vendor:PHIL/ST/MOTPackage Cooled:TO-3D/C:07+

Chip Center: X=0µm, Y=0µm Chip Size: X=7.54mm, Y=2.09mm Chip Thickness: 400µm30µm Bump Size: 78.16µm x 48.10µm Pad Pitch: 70µm(Min.) Bump Height: 15µm(Typ.) Bump Material: Au Voltage boosting polarity : Negative Voltage(VDD Common) Substrate:N

BUS132A

Vendor:MOTPackage Cooled:TO-3

Output frequency range: 1450 MHz to 1750 MHz Divide-by-2 output 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable dual-modulus prescaler 8/9, 16/17, 32/33 Programmable output power level 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode

BUS133

Vendor:MOTPackage Cooled:TO-3

DESCRIPTION This Power Mosfet is the latest development of STMicroelectronics unique Single Feature Size™ strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalance characteristics and less critical alignment steps thereforearemarkablemanufacturing reproducibility.

BUS133A

Vendor:MOTPackage Cooled:TO-3

Note 3: Shut Down (SD) to transmit enable is the time required for the transmit bias circuits to stabilize. Applying a transmit pulse before this time has elapsed will reduce the transmit pulse width. Note 4: Transmit VCC Transient Immunity measures the transmitter circuitry immunity from large VCC and ground return inductive transients arising from the action of large transmitter di/dt currents o...

BUS21

Vendor:availPackage Cooled:STD/C:05+

TxDAC AC CHARACTERISTICS Fundamental Signal-to-Noise and Distortion Signal-to-Noise Ratio THD SFDR IAMP DC CHARACTERISTICS IOUTN Full-Scale Current = IOUTN+ + IOUTN− IOUTG Full-Scale Current = IOUTG+ + IOUTG− AC Voltage Compliance Range IAMPN AC CHARACTERISTICS3 Fundamental IOUTN SFDR (Third Harmonic) IAMP GAIN CONTROL CHARACTERISTICS Minimum Gain Maximum Gain Gain Step Size...

BUS21A

Vendor:availPackage Cooled:STD/C:05+

The DC/DC power module shall be installed in an end-use equip- ment and considerations should be given to measuring the pin tem- perature to comply with TPmax when in operation. Abnormal compo- nent tests are conducted with the input protected by an external 3 A fuse. The need for repeating these tests in the end-use appliance shall be considered if installed in a circuit having higher rated devices.

BUS21B

Vendor:availPackage Cooled:STD/C:05+

1Cwire communication using the DS1481 is impossible in transparent mode. To toggle to normal mode four consecutive overdrive toggle commands must be issued. If this sequence has been issued and the ENI pin remains high for at least 10 ms the part will enter its normal mode of operation. Note that any other 1Cwire time slot command issued during the sequence resets the sequence. The steps needed to re...

BUS21C

Vendor:availPackage Cooled:STD/C:05+

Note Differential gain and differential phase measured for four series LM6362 op amps con- figured with gain of a 2 each in series with a 1 16 attenuator and an LM6321 buffer Error added by LM6321 is negligible Test performed using Tektronix Type 520 NTSC test system

BUS22

Vendor:MOTPackage Cooled:TO-3

NOTES: 1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL combinations. 2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies

BUS22A

Vendor:availPackage Cooled:STD/C:05+

Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Zero Gate Voltage Drain Current Static Drain-to-Source ➃ On-State Resistance (TO-39) Static Drain-to-Source ➃ On-State Resistance (MO-036AB) Diode Forward Voltage ➃

BUS22B

Vendor:MOTPackage Cooled:TO-3

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is intended to be functional, but does not guarantee specfic performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.

BUS22B

Vendor:MOTPackage Cooled:TO-3

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is intended to be functional, but does not guarantee specfic performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.

BUS22C

Vendor:MOTPackage Cooled:TO-3

The TLV320AIC32 is a low-power stereo-audio codec with a stereo headphone amplifier, as well as multiple inputs and outputs, programmable in single-ended or fully-differentialconfigurations.Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 14 mW from a 3.3-V analog supply, making it ideal for portable, battery-powered audio and telephony applications.

BUS23

Vendor:MOTPackage Cooled:TO-3

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

BUS23A

Vendor:MOTPackage Cooled:TO-3

Notes a. CSTRAY < 5 pF on COSC. After Start-Up, VDD of w 3 V. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Guaranteed by design, not subject to production testing.

BUS23B

Vendor:MOTPackage Cooled:TO-3

A wide input voltage range and integrated thermal and overcurrent protection enhance overall system reliability. Reference accuracy and excellent temperature characteristics are provided. A chip-enable input gives the designer complete control over power up, standby, or power down. This device is supplied in a 16-lead surface-mount plastic SOIC with exposed pad to provide a low-resistance path for max...

BUS23C

Vendor:MOTPackage Cooled:TO-3

Output Bus Select. With this pin at a logic high, both the I and the Q data are present on their respective 10-bit output buses (Parallel mode of operation). When this pin is at a logic low, the I and Q data are multiplexed onto the I output bus and the Q output lines all remain at a logic low (multiplexed mode).

BUS24B

Vendor:availPackage Cooled:STD/C:05+

6. Multifunctional, high-precision analog-to-digital converter The family devices include a high-precision 10-bit analog-to-digital converter with four channels and are ideal for such analog control functions as processing audio signals, processing sensor inputs, detecting key switch states, and controlling battery use in portable equipment. Each channel has its own result register readily accessible fr...

BUS24C

Vendor:availPackage Cooled:STD/C:05+

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

BUS24C

Vendor:availPackage Cooled:STD/C:05+

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

BUS25679F

Vendor:DDC

If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase-locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode.

BUS27765E

Vendor:DDCPackage Cooled:DIPD/C:05+

The AT40KALs patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra fast array multipliers without using any busing resources. The AT40KALs Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than convent...

BUS27765E

Vendor:DDCPackage Cooled:DIPD/C:05+

The AT40KALs patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra fast array multipliers without using any busing resources. The AT40KALs Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than convent...

BUS29854 E

Vendor:DDCPackage Cooled:DIPD/C:97+

BUS29854C

Vendor:DDC

The devices come in 8- and 10-bit resolution versions (see Figure 2 for data alignment between 8- and 10-bit versions). Within each resolution version there are three models, offer- ing three-line adaptive comb filtering, two-line adaptive

BUS29854C

Vendor:DDC

The devices come in 8- and 10-bit resolution versions (see Figure 2 for data alignment between 8- and 10-bit versions). Within each resolution version there are three models, offer- ing three-line adaptive comb filtering, two-line adaptive

BUS41429C

Vendor:DDCPackage Cooled:DIPD/C:05+

BUS41429C

Vendor:DDCPackage Cooled:DIPD/C:05+

BUS47

Vendor:availPackage Cooled:MOTD/C:05+

Immediately upon entering the GS4882/GS4982 the video signal is passed to the devices dual mode input clamp in order to clamp the sync tip of the input video waveform to 1.55 Volts. The GS4882/GS4982s dual mode input clamp, with both Hard Clamp and Soft Clamp capabilities, has been specifically designed for use in high performance sync sepa- ration. The dual mode input clamp aids in maintaining the accuracy ...

BUS47A

Vendor:availPackage Cooled:MOTD/C:05+

The standard device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus conten- tion the device contains separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

BUS47P

Like other ChipCorder products, the ISD5008 inte- grates the sampling clock, anti-aliasing and smoothing filters, and the multi-level storage array on a single-chip. For enhanced voice features, the ISD5008 eliminates external circuitry by also in- tegrating automatic gain control (AGC), a power amplifier/speaker driver, volume control, sum- ming amplifiers, analog switches, and a car kit in- terfac...

BUS48

Vendor:availPackage Cooled:MOTD/C:05+

S1 Pin The S1 pin is used to select the mode of operation, as shown in Table 1. The S1 pin contains an internal Schmitt trigger as part of its input to improve noise immunity. This pin has an internal pull-down device to provide a low level when the pin is left unconnected. The S1 pin also serves the purpose of enabling factory trim and test of the device. The higher VPP programming voltage for the ...

BUS48A

Vendor:availPackage Cooled:MOTD/C:05+

NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 16. All loading with 50 W to VCC−2.0 volts. 17. ...

BUS48AP

Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operationg junction temperature (TJ-MAX-OP = 120oC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part...

BUS48AP

Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operationg junction temperature (TJ-MAX-OP = 120oC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part...

BUS48P

For the adjustable output controller, the VREF pin allows great flexibility for the designer. Taking a simple resistor divider tied to an external voltage source and connecting the divider to the VREF pin allows the controller to regulate an output voltage that is some fraction of the external voltage source. And, because any changes in the external voltage source are sensed by the voltage divider, the re...

BUS50

Vendor:MOTD/C:０４＋

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT ...

BUS51

Vendor:MOTD/C:０４＋

Enhanced Page-Mode Operation for Faster Memory Access CAS-Before-RAS ( CBR) Refresh Long Refresh Period C 1024-Cycle Refresh in 16 ms C 128 ms (Max) for Low-Power, Self-Refresh Version ( TMS4x100P) 3-State Unlatched Output Texas Instruments EPIC™ CMOS Process Operating Free-Air Temperature Range 0C to 70C

BUS51

Vendor:MOTD/C:０４＋

Enhanced Page-Mode Operation for Faster Memory Access CAS-Before-RAS ( CBR) Refresh Long Refresh Period C 1024-Cycle Refresh in 16 ms C 128 ms (Max) for Low-Power, Self-Refresh Version ( TMS4x100P) 3-State Unlatched Output Texas Instruments EPIC™ CMOS Process Operating Free-Air Temperature Range 0C to 70C

BUS512

Package Cooled:MODULE

In Figure 14, the trace of Figure 13 has been expanded (100mV/Div. and 100ns/Div.) to show the response of the sample-and-hold circuit with respect to the sampling signal. After the sampling interval, the amplifier overshoots the signal level and settles (within the amplifier offset voltage) in approximately 1µs. The resistor in series with the 300pF phase-compensation capacitor was adjusted to 6...

BUS52

Vendor:MOTD/C:０４＋

NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to C0.5 V. 7. All loading with 50 W to VCCC2.0 volts. 8. VIHCMR min vari...

BUS61553/883B

The Hynix HYM7V75AS1601B N-Series are 16Mx72bits ECC Synchronous DRAM Modules. The modules are composed of eighteen 16Mx4bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, two 18bits driver ICs in 56pin TSSOP package, one PLL clock driver in 24pin TSSOP package and one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. A 0.22uF and a 0.0022uF decoupling capacitors per ...

BUS61553II-140

BUS61554

BUS61554-140

BUS61554-600

Vendor:DDCPackage Cooled:DIP青面镀金 大D/C:92

BUS61554V-110

BUS61555

Vendor:DDCPackage Cooled:DIPD/C:05+

BUS61555/883B

Vendor:DDCPackage Cooled:四列直插78

BUS61555/883B

Vendor:DDCPackage Cooled:四列直插78

BUS61555-140

BUS-61559-110

BUS61560

D/C:08+/09+

The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.

BUS61560-883B

BUS61563V-140

BUS61565II-140

BUS61569-601

BUS61570-883B

BUS63017 883B

Vendor:BUSPackage Cooled:DIP

BUS63101-609

Vendor:DDCPackage Cooled:钢面四方24脚

5V TOLERANT INPUTS HIGH SPEED: tPD = 5.2ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 05 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM...

BUS63101-720

D/C:08+

BUS63101-720

D/C:08+

BUS-63102-637

BUS63102-637

Vendor:DDCPackage Cooled:DIP

BUS63102-637

Vendor:DDCPackage Cooled:DIP

BUS63102II-637

BUS63104-600/883B

Vendor:DDCPackage Cooled:钢面四方24脚

BUS63104II

BUS63105

Vendor:DDCD/C:90

The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The SecSi Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been customer locked, permanently set to 0 if the part has been factory locked, and is 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part.

BUS63105-110

Vendor:DDCPackage Cooled:DIPD/C:05+

BUS63105-617

Vendor:N/APackage Cooled:N/AD/C:N/A

BUS-63106II

BUS63125

Vendor:DDCPackage Cooled:DIPD/C:05+

To reset the new VTRIP voltage, apply the desired VTRIP threshold voltage to the Vcc pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of data 00h to address 03h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to com- plete the operation.

BUS63125/883B

Vendor:DDC

Operating Temperature Range (Note 2) LM136−55˚C to +150˚C LM236−25˚C to +85˚C LM3360˚C to +70˚C Soldering Information TO-92 Package (10 sec.)260˚C TO-46 Package (10 sec.)300˚C SO Package Vapor Phase (60 sec.)215˚C Infrared (15 sec.)220˚C See AN-450 Surface Mounting Methods and Their Effect on Product Reliability (Appendix D) for ot...

BUS63125-636 5962-87579-02XC

Vendor:ADPackage Cooled:DIP钢面D/C:90

BUS63125-647

BUS63125883B

Vendor:ddcPackage Cooled:ddcD/C:dc89

• System Integration Module (SIM07), Incorporating Many Functions Typically Relegated to External Pro- grammable Array Logic (PALs), Transistor-Transistor Logic (TTL), and ASICs, such as: System configuration, programmable address mapping System protection by hardware watchdog logic Power-down mode control, programmable processor clock driver Four programmable chip selects with wait state ...

BUS63126

BUS63127

D/C:08+/09+

2. The ADS-944 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this

BUS-63128II

BUS63147

Vendor:DDCPackage Cooled:DIPD/C:og stock

BUS64101-602/883B

Vendor:DDC

BUS65101

Vendor:12D/C:N/A

The blanking control input on the hexadecimal displays blanks (turns off) the displayed information without disturbing the contents of display memory. The display is blanked at a minimum threshold level of 2.0 volts. When blanked, the display standby power is nominally 250 mW at TA = 25C.

BUS65101/883B

Vendor:DDCPackage Cooled:DIPD/C:28

BUS65101-B

Vendor:DDCPackage Cooled:DIPD/C:2

BUS65106-883B

Vendor:DDCPackage Cooled:9107D/C:1

BUS65112/883B

Vendor:DDCD/C:95+

BUS65112883B

Vendor:DDCD/C:02+

BUS65142-604

Vendor:DDCPackage Cooled:DIPD/C:05+

BUS-65143

BUS65201-602-883B

Vendor:DDC

BUS65600-603/883B

BUS65612

Vendor:DDCPackage Cooled:CPGA

BUS66101/883B

Vendor:DDC

BUS66105/883B

Vendor:DDC

BUS66108

Vendor:DDC

BUS66111-883B

Vendor:452Package Cooled:DDC

Description The HSCH-9101 single, the HSCH-9201 series pair, and the BUS66111-883B anti-parallel pair are advanced gallium arsenide Schottky barrier diodes. These devices are fabricated utilizing molecular beam epitaxy (MBE) manufacturing techniques and feature rugged construction and consistent electrical perfor- mance. A polyimide coating provides scratch protection and resistance to contamination.