Index "C"D/C:4000
D/C:4000
D/C:3000
ESD (electrostatic discharge) sensitive device. Although the MX841 features proprietary ESD protection circuitry, permanent damage may be sustained if subjected to high energy electrostatic discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Vendor:TDKD/C:O9+
Vendor:TDK
The internal circuit is composed of 4 stages including buffer output, which provide high noise immunity and stable out- put. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This cir- cuit prevents device destruction due to mismat...
Vendor:TDK
These devices come in 28 and 40-pin packages. The 28-pin devices do not have a Parallel Slave Port (PSP) implemented and the number of Analog-to-Digital (A/D) converter input channels is reduced to 5. An overview of features is shown in Table 1-1.
Vendor:880000Package Cooled:TDKD/C:2008
Vendor:880000Package Cooled:TDKD/C:2008
Vendor:TDK
TXCLK is an internally derived 1200 or 2400 Hz signal in internal mode and is connected internally to the RXCLK pin in slave mode. Receive data at the RXD pin is clocked out on the falling edge of RXCLK. The asynch/synch converter is bypassed when synchronous mode is selected and data is transmitted at the same rate as it is input.
Vendor:TDK
Vendor:TDKPackage Cooled:SMDD/C:09+
Failure to adhere to the above restrictions could result in a modifica- tion that is considered an act of manufacturing, and will require, under law, recertification of the modified product with the U.S. Food and Drug Administration (ref. 21 CFR 1040.10 (i)).
Vendor:TDKPackage Cooled:08+D/C:120000
24-Bit Resolution Analog Performance: C Dynamic Range: 105 dB Typical C SNR: 105 dB Typical C THD+N: 0.002% Typical C Full-Scale Output: 3.9 Vp-p Typical 4/8 Oversampling Interpolation Filter: C Stop-Band Attenuation: C50 dB C Pass-Band Ripple: 0.04 dB Sampling Frequency: 5 kHz to 200 kHz System Clock: 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, or 1152 fS With Autodetect Zero Flags for Selectable C...
Vendor:TDKD/C:06+
The K6F1016U4C families are fabricated by SAMSUNGs advanced full CMOS process technology. The families support industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
Vendor:TDKPackage Cooled:N/AD/C:08+
This is a four-state pin. DF/DCS = VA, output data format is offset binary with duty cycle stabilization applied to the input clock DF/DCS = AGND, output data format is 2s complement, with duty cycle stabilization applied to the input clock. DF/DCS = VRMA or VRMB , output data is 2s complement without duty cycle stabilization applied to the input clock DF/DCS = "float", output data is offs...
D/C:6935
128 kbytes of user NV RAM Integrated NV SRAM, real-time clock, crystal, power-fail control circuit and lithium energy source Totally nonvolatile with over 10 years of operation in the absence of power Watchdog timer restarts an out-of-control processor Alarm function schedules real-time related activities such as system wakeup Programmable interrupts and square wave output All registers are individually...
Vendor:TDK
The minimum VIN must meet two conditions: VIN 2.3V and VIN (VR + 3.0%) +VDROPOUT. VR is the nominal regulator output voltage. For example: V R = 1.2V, 1.5V, 1.8V, 2.5V, 2.8V, 3.0V, 3.3V, 4.0V, 5.0V. The input voltage (VIN = VR + 1.0V); IOUT = 100 µA. TCV OUT = (VOUT-HIGH - VOUT-LOW) *106 / (VR * ∆Temperature), V OUT-HIGH = highest voltage measured over the temperature range. V OUT-LOW = lowest ...
Vendor:TDKPackage Cooled:SMDD/C:09+
Vendor:TDKPackage Cooled:SMDD/C:09+
Parameter STATIC PERFORMANCE1 Resolution Resolution Relative Accuracy Relative Accuracy Differential Nonlinearity Output Leakage Current Output Leakage Current Full-Scale Gain Error Full-Scale Temperature Coefficient2 REFERENCE INPUT VREF Range Input Resistance Input Capacitance2 ANALOG OUTPUT
Vendor:TDKD/C:08+/09+
and sets the output buffer in the 3-state condition. MR can be left floating since an internal pull-up resistor will make the MR inactive. In the HCT version, the MR input and the two mode select pins S1 and S2 are TTL compatible, but the X1 input has CMOS input switching levels and may be driven by a TTL output using a pull-up resistor connected to VCC.
Vendor:TDKD/C:08+/09+
and sets the output buffer in the 3-state condition. MR can be left floating since an internal pull-up resistor will make the MR inactive. In the HCT version, the MR input and the two mode select pins S1 and S2 are TTL compatible, but the X1 input has CMOS input switching levels and may be driven by a TTL output using a pull-up resistor connected to VCC.
Vendor:TDKD/C:08+
Vendor:TDKD/C:08+
ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.
Vendor:TDK CORP
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recom- mend operation of FACT ® circuits outside databook specifications.
D/C:3000
The drivers provide four selectable levels of preemphasis to compensate for transmission line losses. The receivers incorporates receive equalization and compensates for input transmission line loss. This minimizes deterministic jitter in the link. The equalization is optimized to compensate for a FR-4 backplane trace with 5-dB, high-frequency loss between 375 MHz and 1.875 MHz. This corresponds to a 24-i...
D/C:3000
The drivers provide four selectable levels of preemphasis to compensate for transmission line losses. The receivers incorporates receive equalization and compensates for input transmission line loss. This minimizes deterministic jitter in the link. The equalization is optimized to compensate for a FR-4 backplane trace with 5-dB, high-frequency loss between 375 MHz and 1.875 MHz. This corresponds to a 24-i...
D/C:6000
(3) The products described in this material are intended to be used for standard applications or gen- eral electronic equipment (such as office equipment, communications equipment, measuring in- struments and household appliances). Consult our sales staff in advance for information on the following applications: Special applications (such as for airplanes, aerospace, automobiles, traffic control...
Vendor:TDK
The FCT841T bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The FCT841T is a buffered 10-bit wide version of the FCT373 function.
Vendor:TDKPackage Cooled:SMDD/C:09+
Vendor:TDKD/C:07+
Vendor:TDKD/C:08+
6. Multifunctional, high-precision analog-to-digital converter The family devices include a high-precision 10-bit analog-to-digital converter with four channels and are ideal for such analog control functions as processing audio signals, processing sensor inputs, detecting key switch states, and controlling battery use in portable equipment. Each channel has its own result register readily accessible fr...
Vendor:TDKPackage Cooled:1206-225Z
Composite type with a P-Channel Sillicon MOSFET (MCH3339) and a Schottky Barrier Diode (SBS007M) contained in one package facilitating high-density mounting. [MOSFET] • Low ON-resistance. • Ultrahigh-speed switching. [SBD] • Short reverse recovery time. • Low forward voltage.
Vendor:TDKPackage Cooled:1206D/C:03+
Vendor:TDK
Vendor:TDKD/C:08+
Exceeding these limits may cause malfunction or permanent damage to the device. This parameter is guaranteed by design but not production tested. Maximum output clamp energy capability at 150C junction temperature using single nonrepetitive pulse method. ESD data available upon request. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
Vendor:TDKD/C:08+
Frequency aging is the change in fC with time and is specified at +65C or less. Aging may exceed the specification for prolonged temperatures above +65C. Typically, aging is greatest the first year after manufacture, decreasing in subse- quent years. The center frequency, fC, is measured at the minimum insertion loss point, ILMIN, with the resonator in the 50 Ω test system (VSWR 1.2:1). The shunt in...
Vendor:TDKPackage Cooled:08+D/C:120000
Notes: 1. Absolute maximum ratings are limits beyond which operation may cause permanent damage to the device. These are stress ratings only; functional operation at or above these limits is not implied. 2. Human Body Model: 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Machine Model: 200pF capacitor discharged directly into each pin.
Vendor:TDKPackage Cooled:08+D/C:120000
Notes: 1. Absolute maximum ratings are limits beyond which operation may cause permanent damage to the device. These are stress ratings only; functional operation at or above these limits is not implied. 2. Human Body Model: 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Machine Model: 200pF capacitor discharged directly into each pin.
D/C:1566
Radio frequency IC for analog cordless telephone application in 26/50 MHz band (CTO standard). The IC performs full duplex communication. The transmitting and receiving frequency are depending on whether the IC is used in the handset or in the base station.
Vendor:TDK ?D/C:.
Low skew, fanout buffer 1 to 12 differential clock distribution I2C for functional and output control Feedback pin for input to output synchronization Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs + 2 DDR DIMMs Frequency supports up to 200MHz (DDR400) Supports Power Down Mode for power mananagement CMOS level control signal input
Vendor:TDKD/C:08+
Vendor:TDKD/C:08+
Byte program and Chip erase Auto program and Auto erase Program/erase operation controlled by software command Program/erase pulse controlled by an embedded timer 10000 program/erase cycles Tri-state output buffer TTL-compatible input and output in read and write mode Contained device-identifier code Incorporated data-protection Available packaging for Surface Mount
Vendor:TDKD/C:08+
Note 1 Specification is at TA e 25 C Actual values at operating temperature may differ from the TA e 25 C value When supply voltages are g15V quiescent operating junction temperature will rise approximately 20 C without heat sinking Accordingly VOS may change 0 5 mV and IB and IOS will change significantly during warm-ups Refer to the IB vs temperature and power dissipation graphs for expected values Power sup...
Vendor:TDKD/C:06+/07+
Vendor:TDKD/C:06+/07+
Vendor:TDKPackage Cooled:N/AD/C:08+
Vendor:TDKD/C:08+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Vendor:TDKD/C:08+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Vendor:TDKD/C:08+
Vendor:TDKD/C:06+/07+
Vendor:TDKPackage Cooled:SMDD/C:09+
Vendor:TDKPackage Cooled:SMDD/C:09+
The C3216Y5V1E475ZT is a fully differential, high-speed, low-jitter, 8-to-1 ECL/PECL multiplexer (mux) with dual output buffers. The device is designed for clock and data distri- bution applications, and features extremely low propa- gation delay (310ps typ) and output-to-output skew (30ps max).
Vendor:TDKD/C:08+
Single Schottky rectifier suited to Switched Mode Power Supplies and high frequency DC to DC converters. Packaged in SMA and SMB, this device is especially intended for use in parallel with MOSFETs in synchronous rectification and low voltage secondary rectification.
Vendor:TDKD/C:08+
Vendor:TDKD/C:08+
Vendor:TDKD/C:08+
Vendor:N/APackage Cooled:N/AD/C:08+09+
Vendor:TDKD/C:08+
PLL1 generates a frequency that is equal to the reference divided by an 8-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL1 is sent to two locations: the cross point switch and the PECL output (CY22394). The output of PLL1 is also sent to a /2, /3, or /4 synchronous post-divider that is output through CLKE. The frequency of PLL1 can be changed via serial prog...
Vendor:in stockPackage Cooled:TDKD/C:07+
Vendor:TDKPackage Cooled:SMDD/C:09+
• 100,000 erase/write cycle Enhanced Flash program memory typical • 1,000,000 erase/write cycle Data EEPROM memory typical • 1 second programming time • Flash/Data EEPROM Retention: > 100 years • Self-reprogrammable under software control • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its o...
Vendor:TDKPackage Cooled:N/AD/C:08+
Vendor:TDKD/C:08+
Test pin 2,normal ground Test pin 3,normal ground Reset: An active high signal used to reset the DM6588. Crystal Oscillator Input Crystal Oscillator Output Controller Program Write Enable: This pin is used to enable FLASH ROM programming. Data Output Pin Of Serial Port 1 The serial data is clocked out through this pin
This advanced technology has been especially tailored to mini- mize on-state resistance, provide superior switching perfor- mance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high effi- ciency switched mode power supplies, active power factor cor- rection, electronic lamp ballasts based on half bridge topology.
Vendor:STPackage Cooled:00+D/C:N/A
Vendor:NECPackage Cooled:TSSOPD/C:05+
CyClocksRT is our second-generation software application that allows users to configure this family of devices. The easy-to-use interface offers complete control of the many features of this family including, but not limited to, input frequency, PLL and output frequencies, and different functional options. Data sheet frequency range limitations are checked and performance tuning is automatically applied. CyC...
Vendor:TDKD/C:08+
Vendor:TDK CORP
Vendor:TDK CORP
Vendor:TDK
Vendor:TDK
Vendor:TDK
Vendor:TDKD/C:2006+
Vendor:PMIPackage Cooled:01+D/C:N/A
Vendor:PMIPackage Cooled:01+D/C:N/A
Vendor:TDK
Vendor:TDK
Vendor:TDKD/C:08+
Vendor:880000Package Cooled:TDKD/C:2008
Vendor:880000Package Cooled:TDKD/C:2008
Vendor:TDKD/C:08+
Vendor:880000Package Cooled:TDKD/C:2008