D2083

Vendor:STPackage Cooled:TO-3P

480 Address, Up to 15 IRQ and Three DMA Options ISA Host Interface -16 Bit Address Qualification -8 Bit Data Bus -IOCHRDY for ECP and IrCC -Three 8 Bit DMA Channels -Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems -PME Interface 100 Pin QFP Package

D2084UK

Vendor:SMLPackage Cooled:(LX)high-frequency

The A1421, A1422, and A1423 are ac-coupled Hall-effect sensors which include monolithic integrated circuits that switch in response to changing differential magnetic fields created by rotating ring magnets, or when coupled with a magnet, by ferrous targets. This family of devices also includes an integrated capacitor, providing the high accuracy of analog sensing without an external filter capa...

D2088

Vendor:日立D/C:TO-92

This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Hyundai Semiconductor Rev.10 / Jan.98

D2089

Vendor:TOSHIBAPackage Cooled:TO-3P

TRANSMITTER The transmitter accepts logic level clock (TCLK), positive data (TPOS) and negative data (TNEG) signals and generates current pulses on the LOUT+ and LOUT- pins. When properly connected to a center-tapped 1:2 transformer, an AMI pulse is generated which can drive a 75Ω coaxial cable.

D2092

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. This pin is an output when the hardware watchdog forces a system reset.

D20B80C085-51B6

Vendor:SANYOPackage Cooled:SOP-36D/C:03+

This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

D20B80C085-51B6

Vendor:SANYOPackage Cooled:SOP-36D/C:03+

This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

D20BB0-C085-51B6

Vendor:SANYOPackage Cooled:SOP-36D/C:04+

The D20BB0-C085-51B6 is an ultrahigh-speed, 12-bit digital-to-analog con- verter (DAC) settling to 0.025% in 35 ns. The monolithic de- vice is fabricated using Analog Devices Complementary Bipolar (CB) Process. This is a proprietary process featuring high-speed NPN and PNP devices on the same chip without the use of di- electric isolation or multichip hybrid techniques. The high speed of the D20BB0-C085...

D20C-73

Vendor:ALPHAD/C:2005

"Write Disturb" means a phenomenon that frequent write cycles executed to pages in Flash memory may cause a data error in another page to which write operations are not performed. For example, 20,001 to 50,000 write operations performed to pages other than page "n" may cause a 1-bit error in page "n".

D20LC20

Notes: 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 7. Outputs driving 50Ω transmission lines. 8. 50% input duty cycle. 9. Outputs loaded with 30 pF each. 10. Part-to-Part Skew at a given temperature and voltage. 11. Set-up and Hold times are relative to the falling edge of the input clock.

D20LC30

The D20LC30 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from 21.25 MHz to 1360 MHz and the support of two differential PECL output signals, the device meets the needs of the most demanding clock applications.

D20LC30

The D20LC30 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from 21.25 MHz to 1360 MHz and the support of two differential PECL output signals, the device meets the needs of the most demanding clock applications.

D20LC40

Vendor:600

• CATV Systems Operating in the 40 to 870 MHz Frequency Range • Input Stage Amplifier in Optical Nodes, Line Extenders and Trunk Distribution Amplifiers for CATV Systems • Output Stage Amplifier on Applications Requiring Low Power Dissipation and High Output Performance • Driver Amplifier in Linear General Purpose Applications

D20N03

• C compiler optimized architecture with optional extended instruction set • 100,000 erase/write cycle Enhanced Flash program memory typical • 1,000,000 erase/write cycle data EEPROM memory typical • Flash/data EEPROM retention: > 40 years • Self-programmable under software control • Priority levels for interrupts • 8 x 8 Single Cycle Hardware Multipli...

D20N03L

Vendor:MOTPackage Cooled:07+D/C:TO-251

The TMP86FM29 is the high-speed, high-performance and low power consumption 8-bit microcomputer, including FLASH, RAM, LCD driver, multi-function timer/counter, serial interface (UART/SIO), a 10-bit AD converter and two clock generators on chip.

D20NE03L

Vendor:STPackage Cooled:TO-252D/C:0

The FDS6982AS is designed to replace two single SO- 8 MOSFETs and Schottky diode in synchronous DC:DC power supplies that provide various peripheral voltages for notebook computers and other battery powered electronic devices. FDS6982AS contains two unique 30V, N-channel, logic level, PowerTrench MOSFETs designed to maximize power conversion efficiency. The high-side switch (Q1) is designed with specific em...

D20NF03L

Vendor:STPackage Cooled:07+D/C:TO-252

D20P03

Time filtering on the undervoltage and overvoltage detection and current limiting is programmable via the TIMER Pin. An external capacitor connected between the TIMER Pin and VEE determines the undervoltage/overvoltage time filter and the timeout in current limit. If the pin is tied to VEE, the time filter values and the current limit timeout revert to default figures.

D20P03

Time filtering on the undervoltage and overvoltage detection and current limiting is programmable via the TIMER Pin. An external capacitor connected between the TIMER Pin and VEE determines the undervoltage/overvoltage time filter and the timeout in current limit. If the pin is tied to VEE, the time filter values and the current limit timeout revert to default figures.

D20P06

Vendor:MOTPackage Cooled:07+D/C:TO-251

Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions to conexant.tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications engineer.

D20P25N

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

D20S30

Vendor:MOSPECPackage Cooled:08+D/C:2000

The ispLSI 2096VL is a High Density Programmable Logic Device containing 96 Registers, six Dedicated Input pins, three Dedicated Clock Input pins, two dedi- cated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096VL fea- tures in-system programmability through the Boundary Scan Test Access Port (TAP) and is ...

D20VIT80

Vendor:SHINDENGEND/C:2007+

The power detector is temperature compensated on the chip, enabling a single-ended output voltage with excellent accuracy over a wide range of operating temperatures. The PA is biased by a single +3.3 V supply and consumes ultra-low current in the OFF mode.

D20VT100

Vendor:NIEC

Communications between backplanes, modules and host is in ASCII over an RS-232C link or RS-485 bi-directional serial bus. Circuitry to convert RS-232C to RS485 is built into the 6B backplane. Baud rates are software programmable, with speeds up to 19.2 K Baud.

D20VT60

Vendor:SHINDENGEND/C:331

Zener diode D2 clamps the output voltage VOUT at +24V if the LED array circuit opens. To evaluate output voltages greater than +24V, zener diode D2 must be replaced. Choose the zener diode +2V above the maxi- mum V OUT . The MOSFET N1 breakdown voltage should exceed the zener voltage. Output capacitor C2s voltage rating must exceed the zener diode voltage.

D20XB60

Vendor:SHINDENGENPackage Cooled:N/AD/C:04+

At the output of all CCD's, transported pixel charge (electrons) is converted to a voltage by depositing the charge onto a capacitor (usually called the output or "floating" capacitor). The voltage that develops across this capacitor is obviously proportional to the amount of deposited charge (i.e., the number of electrons) according to ∆V = ∆Q/C. Once settled, the resulting capac...

D2101

The subsequent analog signal is sent to the on-chip line driver where the analog signal can be driven into an appropriate transformer to provide up to 14.5dBm power into a 135Ω line for G.SHDSL. In addition, the on-chip line driver can be used as an output buffer to generate 17dBm into a 135Ω line via an external line driver (such as the OPA2677) for HDSL2. With an appropriate DSP, the trans...

D2102

Package Cooled:08+D/C:2000

unless otherwise noted, minimum and maximum limits apply across the recommended operating junction temperature and voltage range, VTIMER = 0 V, and all outputs unloaded; typical specifications are at TJ = 25C, VVCC = 48 V, VTIMER = 0 V, and all outputs unloaded; positive currents are into pins.

D2102AL

The MC74HC1G14 is a high speed CMOS inverter with Schmitt−Trigger input fabricated with silicon gate CMOS technology. The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output. The MC74HC1G14 output drive current is 1/2 compared to MC74HC series.

D2102AL-4

Vendor:NECPackage Cooled:DIP/16

The CY22050 is the next-generation programmable FTG (frequency timing generator) for use in networking, telecom- munication, datacom, and other general-purpose applications. The CY22050 offers up to six configurable outputs in a 16-pin TSSOP, running off a 3.3V power supply. The on-chip reference oscillator is designed to run off an 8C30-MHz crystal, or a 1C133-MHz external clock signal.

D2104

D/C:SOP

The 16K EEPROM is capable of a 16-byte page write. A page write is initiated in the same way as a byte write, but the microcontroller does not send a stop con- dition after the first data word is clocked in. Instead, af- ter the EEPROM acknowledges the receipt of the first data word, the microcontroller can transmit up to 15 more data words. The EEPROM will respond with a z e ro a f t e r e a c h d a t a w o...

D2104A

Vendor:105Package Cooled:INTELD/C:N/A

The TC57 enters a low power shutdown mode when the shutdown input (SHDN) is high. During shutdown, the regulator is disabled, the output capacitor is discharged through the load, and supply current to the TC57 decreases to less than 1µA. Normal operation resumes when SHDN is brought low. If the shutdown mode is not used, SHDN should be tied to VIN.

D2104A-15

Vendor:INTELPackage Cooled:DIP16陶瓷D/C:97+

D2104A-2

Vendor:INTELPackage Cooled:DIPD/C:N/A

Standard Space Vector Modulation C 3 outputs version (svmStd3) is a variant of the svmStd function that, in contrary to svmStd, generates only top channel signal of each PWM pair. The bottom channel signal could be derived from the top channel signal by an external hardware. The function set consists of 4 TPU functions:

D2104A3

D2104A-4

Vendor:1256Package Cooled:INTELD/C:N/A

−I2S, Left, Right Justified or DSP −16/20/24/32 bit Word Lengths Four Independent stereo DAC outputs with independent digital volume controls Master or Slave Audio Data Interface 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation 28 pin SSOP Package

D2107

Vendor:35Package Cooled:INTELD/C:N/A

After the initial change on powerCup, subsequent changes in the Dallastat EEPROM memory cells will occur only if the wiper position of the part is moved greater than 12.5% of the total resistance range. Any wiper movement after initial powerCup which is less than 12.5% will not be recorded in the EEPROM memory cells. Since the Dallastat contains a 64CtoC1 multiplexer, a change of greater than 12.5% c...

D2107C

Vendor:INTELPackage Cooled:DIPD/C:79+

Notes a. When Mounted on 1 x 1 PCB FR4 Board. b. Not tested, specified by design. c. VLOADDUMP is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839. Supply voltages higher than Vbb(AZ) require an external current limit for the GND pin, e.g. witha 150-W resistor in GND connection. A resistor for the protection of the input is integrated. d. According to ANSI EOS/ESD-S5.1-1983...

D2107C-2

Vendor:INTELPackage Cooled:DIPD/C:79+

characteristics enable this device to be used in an RS-232-C inter- face with ground loop isolation and improved common mode rejection. As a line receiver, the HCPL-2300/HCPL-0300 will operate over longer line lengths for a given data rate because of lower IF and VF specifications.

D2107C-2

Vendor:INTELPackage Cooled:DIPD/C:79+

characteristics enable this device to be used in an RS-232-C inter- face with ground loop isolation and improved common mode rejection. As a line receiver, the HCPL-2300/HCPL-0300 will operate over longer line lengths for a given data rate because of lower IF and VF specifications.

D2109-3

Vendor:INTELPackage Cooled:25

2.1 General. The documents listed in this section are specified in sections 3 and 4 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements documen...

D2111

Vendor:CHMCPackage Cooled:DIPD/C:00

The LM27 is a precision, single digital-output, low-power thermostat comprised of an internal reference, DAC, tem- perature sensor and comparator. Utilizing factory program- ming, it can be manufactured with different trip points as well as different digital output functionality. The trip point (TOS) can be preset at the factory to any temperature in the range of +120˚C to +150˚C in 1˚C ...

D2112A-4

D2114

The 73K322L is a highly integrated single-chip modem IC which provides the functions needed to construct a CCITT V.23, V.22 and V.21 compatible modem, capable of 1200 or 0-300 bit/s full-duplex operation or 0-1200 bit/s half-duplex operation with or without the back channel over dial-up lines. The 73K322L is an enhancement of the 73K221L single- chip modem with performance characteristics suitable for Europ...

D2114-2

Vendor:INTERSILPackage Cooled:DIP陶瓷条子18脚D/C:80

D21142W

Vendor:XILINXPackage Cooled:PPLCC

The NCP1501 is a dual mode regulator that operates either as a PWM Buck Converter or as a Low Drop Out Linear Regulator. If a synchronization signal is present, the NCP1501 operates as a current mode PWM converter with synchronous rectification. The synchronization signal allows the user to control the location of the spurious frequency noise generated by a PWM converter. Linear mode is active when a s...

D2114-3

Vendor:N/APackage Cooled:N/AD/C:N/A

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU...

D21147S

D2114A

Vendor:55Package Cooled:INTELD/C:N/A

The TLE 4299 is a PNP based very low drop linear voltage regular. It regulates the output voltage to VQ = 5 V for an input voltage range of 5.5 V £ VI £ 45 V. The control circuit protects the device against potential caused by damages overcurrent and overtemperature.

D2114A5

Vendor:intPackage Cooled:91D/C:25/tube/

DYNAMIC PERFORMANCE Maximum Output Update Rate (fDAC) Output Settling Time (tST) (to 0.1%)1 Output Propagation Delay (tPD)1 Glitch Impulse1 Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA) Output Noise (IOUTFS = 2 mA)

D2114A-5

Vendor:INTELPackage Cooled:DIP18陶瓷D/C:83+

* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

D2114AL

Vendor:INTELPackage Cooled:DIPD/C:N/A

The NJU6060 is an RGB LED driver with PWM control. It contains PWM (pulse width modulation) controller, LED drivers, 8-bit serial interface, etc. Each of the R (red), G (green) and B (blue) outputs produces 32 levels individually so that the RGB LED emits 32,768 colors (32 x 32 x 32). It requires only four external components such as three resistors for LED current adjustment and the one for oscillat...

D2114AL-2

Vendor:INTELPackage Cooled:DIP18陶瓷D/C:84+

Fully compliant with the Universal Serial Bus Specification, version 1.1 USB keyboard design is compliant with USB Device Class Definition for Human Interface Devices (HID), version 1.1 Built-in 3.3v voltage regulator allows single +5V operating voltage drawing directly from USB bus Intergrated USB full speed transceiver Support for 19 x 8 standard key matrix. An Fn pin to select alternative matrix. Eac...

D2114AL-3

Vendor:1005Package Cooled:INTELD/C:N/A

The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar b...

D2114AL-5

Vendor:INTELPackage Cooled:DIPD/C:N/A

The information provided herein is believed to be reliable; however, C&D TECHNOLOGIES assumes no responsibility for inaccuracies or omissions. C&D TECHNOLOGIES assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the ci...

D2114L

Vendor:INTELPackage Cooled:DIPD/C:N/A

The MAX2338 receiver RF front-end IC is designed for dual-band CDMA cellular phones and can also be used in dual-band TDMA, GSM, or EDGE cellular phones. Thanks to the MAX2338s on-chip low-power LO divider, the cellular VCO module can be eliminated. The MAX2338 includes a low-noise amplifier (LNA) with an adjustable high-input third-order intercept point (IIP3) to minimize intermodulation and cross-modulatio...

D2114L-2

Vendor:INTELD/C:DIP

Relative accuracy g0 19% error maximum (DAC0808) Full scale current match g1 LSB typ 7 and 6-bit accuracy available (DAC0807 DAC0806) Fast settling time 150 ns typ Noninverting digital inputs are TTL and CMOS compati- ble High speed multiplying input slew rate 8 mA ms Power supply voltage range g4 5V to g18V Low power consumption 33 mW g5V

D2114L3

Vendor:INTELD/C:06+

1) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2

D2114L3

Vendor:INTELD/C:06+

1) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2

D2114NL4

Vendor:INTELD/C:08+

The device has 64 software-configurable I/O pins (36 in the FBGA-144 package), organized into four ports called Port E, Port F, Port G, and Port H. Each pin can be configured to operate as a general-purpose input or general-purpose out- put. In addition, many I/O pins can be configured to operate as inputs or outputs for on-chip peripheral modules such as the UARTs or timers.

D2115A-2

Vendor:INTELPackage Cooled:DIP=16

Two-frame transmit and receive PCM slip buffers Clock rate adapter synthesizes jitter attenuated system clocks from an internal or external reference Parallel 8-bit microprocessor port supports Intel or Motorola buses Automated Facility Data Link (FDL) management BERT generation and counting Two full-duplex HDLC controllers for data link and LAPD/SS7 signaling B8ZS/HDB3/Bit 7 zero suppression 80-pin MQ...

D2115A-2

Vendor:INTELPackage Cooled:DIP=16

Two-frame transmit and receive PCM slip buffers Clock rate adapter synthesizes jitter attenuated system clocks from an internal or external reference Parallel 8-bit microprocessor port supports Intel or Motorola buses Automated Facility Data Link (FDL) management BERT generation and counting Two full-duplex HDLC controllers for data link and LAPD/SS7 signaling B8ZS/HDB3/Bit 7 zero suppression 80-pin MQ...

D2115AL-2

Vendor:INTELPackage Cooled:DIP/16D/C:92+

When pin 23 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the digital data path. When pin 23 has a logic "0" applied, the FIFO is transparent, and the output data goes directly to the output three-state register (whose operation is controlled by pin 9 (ENABLE)). Read and write commands to the FIFO are ignored when the ADS-930 is operated in the "direct" mod...

D2116-7

Vendor:INTELPackage Cooled:DIPD/C:N/A

D2117

Vendor:105Package Cooled:INTELD/C:N/A

During full duplex transmission, the signal at Tip and Ring consists of both the signal from the device to the line and the signal from the line to the device. The signal input at RX, being sent to the line, must not appear at the output TX. In order to prevent this, the device has an internal cancellation circuit. The measure of attenuation is Transhybrid Loss (THL).

D2117-2

Vendor:INTELPackage Cooled:5

Reference Output Voltage: This output biases to VCC C1.2V. Connect to VT pin when AC- coupling the input. Bypass with 0.01µF low ESR capacitor to VCC. Maximum current source or sink is 0.5mA. See Input Interface Applications section.

D2118

Vendor:205Package Cooled:INTELD/C:N/A

n Low cost 8-bit OTP microcontroller n OTP program space with read/write protection (fully secured) n Quiet Design (low radiated emissions) n Multi-Input Wakeup pins with optional interrupts (4 to 8 pins) n 8 bytes of user storage space in EPROM

D2118-3

Vendor:INTELPackage Cooled:5

Out Short Circuit to GND Duration (VIN< 12V)...Continuous Out Short Circuit to GND Duration (VIN< 40V).5 sec Out Short Circuit to IN Duration (VIN< 12V)...Continuous Continuous Power Dissipation (TA = +70C)...300mW Storage Temperature..-65C to 150C Lead Temperature (soldering,10 sec)..250C

D21184

Vendor:intPackage Cooled:91D/C:30/tube/

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V...

D21187

D2118-7

Vendor:MOTPackage Cooled:DIP16陶瓷D/C:81+

Unlike other nonvolatile memory technologies, there is no write delay with MRAM. The entire memory operation occurs in a single bus cycle. Therefore, any operation including read or write can occur immediately following a write. Data Polling, a technique used with EEPROMs to determine if the write is complete is unnecessary. Page write, a technique used to enhance EEPROM write performance is also unnecessary ...

D211U

Vendor:in stockPackage Cooled:EupecD/C:08+

D2122

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage ...

D2123

D2125

Vendor:INTELPackage Cooled:CDIP16D/C:2007+

The SC16C2550B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.

D2125

Vendor:INTELPackage Cooled:CDIP16D/C:2007+

The SC16C2550B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.

D2125A-12

Vendor:INTELPackage Cooled:CDIP16D/C:——

D2125AC

D2125AL

Vendor:87Package Cooled:INTELD/C:N/A

s 2 kB byte-erasable Flash code memory organized into 256-byte sectors and 16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. s 256-byte RAM data memory. s Two 16-bit counter/timers. Timer 0 (and Timer 1 - P89LPC917) may be configured to toggle a port output upon timer overflow or to become a PWM output. s 23-bit system timer that can also be use...

D2125H

D2125H-1

Vendor:INTPackage Cooled:CDIP16D/C:N/A

BSerial interface (CLK, STB, DIN, DOUT) BKey scanning (6 4 matrices) BProgramming display modes (11-digit & 11-segment to 6-digit & 16-segment) BProgramming dimming step BHigh-voltage output (VDD-35V max). B2 channels LED ports. B2-pin General-purpose input port BBuilt-in oscillator BNo external resistor necessary for driver outputs (provides PMOS open-drain and pull-low resistor

D2125H2

The Am29DL640H is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ15CDQ0; byte mode data appears on DQ7CDQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers.

D2125H-3

Vendor:INTELPackage Cooled:DIPD/C:82+

Absolute Maximum Ratings • Supply voltage VDD (3.3V) VSS C 0.3 to +4.6V VDD (5.0V) VSS C 0.3 to +6.0V • Input voltage VI (3.3V) VSS C 0.3 to VDD3 + 0.3 V VI (5.0V) VSS C 0.3 to VDD5 + 0.3 V • Output voltage VO (3.3V) VSS C 0.3 to VDD3 + 0.3 V VO (5.0V) VSS C 0.3 to VDD5 + 0.3 V • Operating temperature ToprC20 to +75C • Storage temperature TstgC55 to +125C

D2126N

Vendor:NECD/C:05+

D2136

Vendor:MECPackage Cooled:SIP3D/C:2007+

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Regis- ter contents serve as input to an internal state-ma- chine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase op- erati...

D2137

All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exceptio...

D2137

All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exceptio...

D213E2

Vendor:INFINEONPackage Cooled:1000D/C:07+

Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register, respectively. These bytes are read-only. Bytes 2 and 3 provide access to TH and TL registers. Byte 4 contains the configuration register data, which is explained in detail in the CONFIGURATION REGISTER section of this datasheet. Bytes 5, 6 and 7 are reserved for internal use by the device and cannot be overwritten; ...

D2141-3

Vendor:INTELPackage Cooled:CDIP

1.1 Scope. This specification covers the performance requirements for NPN, silicon, power transistors for use in high-speed power-switching applications. Four levels of product assurance are provided for each encapsulated device type and two levels of product assurance are provided for each unencapsulated device type as specified in MIL-PRF-19500.

D2141-4

Vendor:INTELPackage Cooled:DIP/18D/C:96/97+

Balanced Ringing is applied to the line by setting RC (pin 30) to +5V and connecting the ringing signal (20Hz) to RV (pin 35) as shown in Figure 4. A 1.2Vrms input will give approximately 60Vrms output across Tip and Ring, sufficient for short loop SLIC applications. The SLIC is capable of detecting an Off Hook condition during ringing by filtering out the large A.C. component. A 0.47uF cap should be connec...

D2141L-5

Vendor:INTELPackage Cooled:DIPD/C:81+

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1 register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a Port B Read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset.

D2142

Vendor:105Package Cooled:INTELD/C:N/A

Hynix HYMD232726B(L)8J-J series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

D21422

Vendor:intPackage Cooled:84D/C:23/tube

The PSoC device incorporates flexible internal clock genera- tors, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal ...

D2142-2

Vendor:INTELPackage Cooled:DIPD/C:90+

D2142L-3

Vendor:INTELPackage Cooled:DIPD/C:2005+

The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages...

D2142L-3

Vendor:INTELPackage Cooled:DIPD/C:2005+

The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages...

D2147-2

D2147AD-35

Vendor:NECPackage Cooled:DIPD/C:83+

All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low state. This feature simplifies testing because the registers can be set to an initial state prior to executing the test sequence.

D2147D

Vendor:NECPackage Cooled:DIPD/C:N/A

The MAX3873A is implemented in Maxim's second-generation SiGe process and consumes only 260mW at 3.3V supply (output clock disabled, low output swing). The device is available in a 4mm x 4mm 20-pin QFN exposed-pad package and operates from -40C to +85C.

D2147H.H-2

Vendor:INTELPackage Cooled:CDIP18D/C:2007+