DL6306

Vendor:DATATRONIC(BOURNS)Package Cooled:96D/C:2128

This pin is connected to a voltage that must be at least 4V higher than the bus voltage of the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A minimum of 1µF, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability.

DL6307

Vendor:DATATRONICPackage Cooled:08+D/C:700

Note 11: Maximum power dissipation in the device (PDMAX) occurs at an output power level significantly below full output power. PDMAX can be calculated using Equation 1 shown in the Application Information section. It may also be obtained from the power dissipation graphs.

DL6308

D/C:89

Low Output Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Six Clock Outputs Polarity Control Selects True or Complementary Outputs Distributed VCC and GND Pins Reduce Switching Noise High-Drive Outputs (C 32-mA IOH, 32-mA IOL) State-of-the-Art EPIC-B™ BiCMOS Design Significantly Reduces Power Dissipati...

DL6313

D/C:89

This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges an...

DL632-250

D/C:94

The magnetic field changes are sensed by two integrated Hall transducers and then are differentially amplified on the chip. Differential sensing provides immunity to radial vibration, within the device operating air gap range, by rejection of common-mode signal changes. Steady-state system offsets are eliminated using an on-chip differential bandpass filter with integrated capacitor. This...

DL6352

D/C:88

Ultra−Low Dropout Voltage of 220 mV at 150 mA Low Output Noise of 30 mVrms Excellent Line and Load Regulation High Output Voltage Accuracy of "2% Low Supply Current of 75 mA Excellent Power Supply Rejection Ratio Wide Operating Voltage of 1.5 V to 3.3 V Low Quiescent Current of 0.1 mA Fast Dynamic Performance Fold Back Protection Circuit Low Temperature Drift Coefficient on the Output Volt...

DL641-80

D/C:88

DC Supply voltage pin 2 1) Output current Power Good and Fault Collector Output Current Operating Free Air Temperature Range Power dissipation Storage temperature Adjustable Under voltage blanking delay at Power Up Extra Protection Power Good input Power Good output Adjustable Power Good delay Remote control Adjustable Remote delay Adjustable Inrush Current Blank (surge) Positive Input of t...

DL643-15B

D/C:91

The bq2420x is designed to work with a current-limited wall-mount transformer and therefore does not provide any current regulation. However, these devices offer a fixed internal current limit to prevent damage to the internal powerFET. A time-limited pre-conditioning phase is provided to condition deeply discharged cells. Once the battery reaches the charge voltage, the high accuracy voltage regul...

DL643-25B

D/C:90

Instructions 1. Place codewheel on shaft. 2. Set codewheel height: (a) Place the correct gap setting tool (per Ordering Information Table) on motor base, flush up against the motor shaft as shown in Figure 2. The shim has two different size steps. Choose the one that most closely matches the width of the codewheel boss. The

DL6555

D/C:87

The DL6555 includes a POK output to indicate when input power is present. If either charging source is active, POK goes low. The DL6555 instead features a CHG output to indicate charging status. With USB connected, but without DC power, charge cur- rent is set to 100mA (max). This allows charging from both powered and unpowered USB hubs with no port communication required. When DC power is connected, charg...

DL6563

D/C:93

Vcc = 5V 10%, TA = 0C to 70C (Normal) unless otherwise specified. -55 # SymbolParameter Min.Max. READ CYCLE 1tRCRead Cycle Time55- 2tAAAddress Access Time-55 3tACSChip Select Access Time-55 4tOEOutput Enable to Output Valid-25 5tCLZChip Select to Output in Low Z5- 6tOLZOutput Enable to Output in Low Z5- 7tCHZChip Disable to Output in High Z020 8tOHZOut Disable to Output in High Z020 9tOHOutpu...

DL6581

D/C:89

The DL6581 is the third implementation of the fourth generation (G4) microprocessors from Motorola. The DL6581 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The DL6581 consists of a processor core, a 256-Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3 cache through a dedicated high bandwidth interface.

DL6623

D/C:85

Clocks in the ispLSI 1048 device are selected using the Clock Distribution Network. Four dedicated clockpins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (D0 on the ispLSI 1048 device). Th...

DL6692

D/C:95

DL6801

D/C:95

FEATURES lOptions :- 10mm lead spread - add G after part no. Surface mount - add SM after part no. Tape&reel - add SMT&R after part no. lHigh Current Transfer Ratio (500% min) lHigh Isolation Voltage (5.3kVRMS ,7.5kVPK ) lBasepin unconnected for improved noise immunity in high EMI environment lHigh sensitivity to low input drive current lCustom electrical selections available

DL6944

D/C:88

The SN74CBTD3384C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. This device features an integrated diode in series with VCC to provide level shifting for 5-V input down to 3.3-V output levels. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBTD3384C provides protection for undershoot up to −2 V by sens...

DL6948

D/C:87

The Programmable Interconnect Matrix (PIM) consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting and density limitations.

DL700147/TO13TR

Vendor:STPackage Cooled:SOPD/C:99+

DL70047/XT013TR

Vendor:STPackage Cooled:N/AD/C:99+

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

DL70047/XTTR

Vendor:STPackage Cooled:SMDD/C:99+

Internet time servers use several standard timing protocols. The major three are Time Protocol, Daytime Protocol, and Network Time Protocol (NTP). The time servers are continually listening for timing requests sent using any of these protocols. When the server receives a request, it sends time to your computer in the appropriate format. The protocol depends upon the type of client software used. Most client ...

DL-7018

Package Cooled:QFP/44

A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation.

DL-7018

Package Cooled:QFP/44

A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation.

DL-7140-NGP

Vendor:SANYOPackage Cooled:DIP-3D/C:08+

DL7150

Vendor:D-LINKPackage Cooled:QFPD/C:04+

Power-On Reset Generator with Adjustable Delay Time: 1.25ms to 10s Very Low Quiescent Current: 2.4µA typ High Threshold Accuracy: 0.5% typ Fixed Threshold Voltages for Standard Voltage Rails from 0.9V to 5V and Adjustable Voltage Down to 0.4V Are Available Manual Reset (MR) Input Open-Drain RESET Output Temperature Range: C40C to +125C Small SOT23 and 2mm 2mm QFN Packages

DL7200

Vendor:D-LINKPackage Cooled:0418/D/C:QFP

All values at 20C (68F). Relay has fixed coil polarity. Relay may pull in with less than Must Operate value. Relay adjustment may be affected if undue pressure is exerted on relay case. 5. For complete isolation between the relays magnetic fields, it is recommended that a .197" (5.0 mm) space be provided between adjacent relays. 6. Specifications subject to change without notice.

DL7200

Vendor:D-LINKPackage Cooled:0418/D/C:QFP

All values at 20C (68F). Relay has fixed coil polarity. Relay may pull in with less than Must Operate value. Relay adjustment may be affected if undue pressure is exerted on relay case. 5. For complete isolation between the relays magnetic fields, it is recommended that a .197" (5.0 mm) space be provided between adjacent relays. 6. Specifications subject to change without notice.

DL7600

Vendor:D-LINKPackage Cooled:BGAD/C:08+

Hardware Reset, active Low. Provides a hardware method of resetting the HY 29F400 to the read array state. When the device is reset, it immediately terminates any operation in progress. The data bus is tri-stated and all read/write commands are ignored while the input is asserted. While RESET# is asserted, the device will be in the Standby mode.

DL791A

DL-809A

Package Cooled:98+97+D/C:QFP-100P

The Hitachi HM628100I Series is 8-Mbit static RAM organized 1,048,576-word 8-bit. HM628100I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 44-pin TSOP II for high density surface m...

DL814002-C

DL8501

Vendor:N/APackage Cooled:DIPD/C:1991

Description The HYS 72Dxx0x0GR are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs) organized as 32M 72 (256MB), 64M 72 (512MB) and 128M 72 (1GB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive l...

DL8501

Vendor:N/APackage Cooled:DIPD/C:1991

Description The HYS 72Dxx0x0GR are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs) organized as 32M 72 (256MB), 64M 72 (512MB) and 128M 72 (1GB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive l...

DL8701

Vendor:D-LINKPackage Cooled:50D/C:N/A

In the MBM29DL16XTE/BE, a new design concept is implemented, so called Sliding Bank Architecture. Under this concept, the MBM29DL16XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size combinations; 0.5 Mb/15.5 Mb, 2 Mb/14 Mb, 4 Mb/12 Mb, 8 Mb/8 Mb.

DL8701

Vendor:D-LINKPackage Cooled:50D/C:N/A

In the MBM29DL16XTE/BE, a new design concept is implemented, so called Sliding Bank Architecture. Under this concept, the MBM29DL16XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size combinations; 0.5 Mb/15.5 Mb, 2 Mb/14 Mb, 4 Mb/12 Mb, 8 Mb/8 Mb.

DL89C10A

The DL89C10ACDL89C10A series fit perfectly in applications ranging from battery chargers to low-power remote sensors. The EPROM technology makes customization of application programs (detection levels, pulse gener- ation, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-p...

DL93C16AS

Vendor:n/aPackage Cooled:QFPD/C:93

DESCRIPTION Dual center tap rectifier suited for Switch Mode Power Supplies and High frequency DC to DC converters. Packaged in DPAK, D2PAK, TO-220AB, TO220-FPAB and I2PAK, this device is intended for use in low voltage, high frequency inverters, free wheeling and polarity protection applications.

DLA/6SGD

DLA/6SGD G

DLA/6YD

DLA001D

Vendor:STPackage Cooled:SOPD/C:06+PBF

6. Tlow to Thigh = 0 to +125C for LM317MATlow to Thigh = − 40 to +125C for LM317MAB. 7. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. 8. CAdj, when used, is connected between the adjustment pin and ground. 9. Since Long−Term Stability cannot be mea...

DLA001N

Vendor:STPackage Cooled:07+D/C:2300

Notes: 1. RJA is determined with the device mounted on a 1 in2 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. The thermal resistance from the junction to the circuit board side of the solder ball, RJB, is defined for reference. For RJC, the thermal reference point for the case is defined as the top surface of the copper chip carrier. RJC and RJB are guaranteed by design while RJA is deter...

DLA001N

Vendor:STPackage Cooled:07+D/C:2300

Notes: 1. RJA is determined with the device mounted on a 1 in2 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. The thermal resistance from the junction to the circuit board side of the solder ball, RJB, is defined for reference. For RJC, the thermal reference point for the case is defined as the top surface of the copper chip carrier. RJC and RJB are guaranteed by design while RJA is deter...

DLA11

Vendor:SANYOPackage Cooled:SMAD/C:08+

DLA11 C-TR

Vendor:SANYOPackage Cooled:1808

DLA11C

Vendor:JATPackage Cooled:SOD-6D/C:05+

Equivalent circuits for the twelve macrocell configurations are illustrated in Figure 5. In addition to emulating the four PAL-type output structures (configurations 3, 4, 9, and 10), the macrocell provides eight additional configurations. When creating a PEEL device design, the desired macrocell configuration is generally specified explicitly in the design file. When the design is assembled or compiled, the...

DLA11C/LA

Package Cooled:SOD-6D/C:08+

For those systems using buses wider than a single byte, the four independent receive paths can be bonded together to al- low synchronous delivery of data across a two-byte-wide (16- bit) path, or across all four bytes (32-bit). Multiple CYP15G0401DXA devices may be bonded together to provide synchronous transport of buses wider than 32 bits.

DLA-6GD

DLA-6SRD

DLA92001E

D/C:08+

The Motorola AM26LS31 is a quad differential line driver intended for digital data transmission over balanced lines. It meets all the requirements of EIAC422 Standard and Federal Standard 1020. The AM26LS31 provides an enable/disable function common to all four drivers as opposed to the split enables on the MC3487 EIAC422 driver. The high impedance output state is assured during power down. • Fu...

DLA92001H

D/C:07+

DLA92004E

Vendor:THERMIISTORPackage Cooled:SOD-123D/C:04+

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC/VAC, Post Office Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter. AMSC N/AFSC 5961 DISTRIBUTION S...

DLA92005F

D/C:07+

These N-Channel enhancement-mode power MOSFETs are manufactured using the latest manufacturing process technology. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These tran...

DLA93003P

D/C:07+

ICCL106 ICCZVCC = 5.5 V98 † All typical values are at VCC = 5 V, TA = 25C. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

DLA940006D

Vendor:JATPackage Cooled:SOD-123D/C:05+

Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by mask option. Software instructions determine the CMOS output or Schmitt trigger or CMOS (dependent on options) input with a pull-high resistor (determined by pull-high options).

DLA94006D

Vendor:THERMIISTORPackage Cooled:SOD-123D/C:04+

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

DLA97013

Vendor:SEMITEC ?Package Cooled:00+?D/C:1760

The LIM provides 100% connectivity of the inputs and out- puts of each LC in a given CLB. The benefit of the LIM is that no general routing resources are required to connect feedback paths within a CLB. The LIM connects to the GRM via 24 bidirectional nodes.

DLA98998

Vendor:SEMITEC ?Package Cooled:N/A?D/C:2945

There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit arrangement. The TTL/BTL output drivers for bit 0 are enabled with OEA1/OEB1, output drivers for bits 1C2C3 are enabled with OEA2/OEB2 and output drivers for bits 4C5C6 are enabled with OEA3/OEB3.

DLA98998

Vendor:SEMITEC ?Package Cooled:N/A?D/C:2945

There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit arrangement. The TTL/BTL output drivers for bit 0 are enabled with OEA1/OEB1, output drivers for bits 1C2C3 are enabled with OEA2/OEB2 and output drivers for bits 4C5C6 are enabled with OEA3/OEB3.

DLB5018V

Vendor:SOPD/C:2005+

When the XAUI_EN bit is set to 1, if a local/remote fault is received on the XAUI inputs, it will be passed as ||LF|| or ||RF|| Sequence Ordered_sets respectively, i.e., /K28.4/D0.0/D0.0/D1.0(D2.0)/. Local fault is declared when any of the following conditions are detected:

DLBL01009

Vendor:JRCPackage Cooled:SQFP120D/C:2007+

DLBL01009C704TE

Vendor:JRCPackage Cooled:QFPD/C:N/A

DLBRT2 1A01

Vendor:ALCTELPackage Cooled:QFP-208

DLBRT21A01

Vendor:ALCTELD/C:07+

The CY7C133 (master) provides on-chip arbitration to resolve simultaneous memory location access (contention). Table 2 shows a summery of conditions where BUSY is asserted. If both ports CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but which one is not pr...

DLBRT21A01

Vendor:ALCTELD/C:07+

The CY7C133 (master) provides on-chip arbitration to resolve simultaneous memory location access (contention). Table 2 shows a summery of conditions where BUSY is asserted. If both ports CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but which one is not pr...

DLC/6GD

DLC26SRDLA13

Vendor:kingbPackage Cooled:kingbD/C:dc98

o Powered Device Interface Fully Integrated IEEE 802.3af-Compliant PD Interface PD Detection and Programmable Classification Signatures Less than 10µA Leakage Current Offset During Detection Integrated MOSFET for Isolation and Inrush Current Limiting Gate Output Allows External Control of the Internal Isolation FET Programmable Inrush Current Control/ULVO PGOOD/PGOOD Outputs Enab...

DLC548GGU

Vendor:TIPackage Cooled:BGAD/C:6+

The DLC548GGU (1) devices are members of the Texas Instruments (TI) TMS470R1x family of gen- eral-purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The A128 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-b...

DLC549GGL

The AME1505 is a 5A low-dropout positive voltage regu- lator. The dropout voltage of AME1505 is 750mV at maxi- mum output current. The output voltage is preset at fac- tory. It is available in fixed and adjustable output voltage versions. The fixed voltage range could expand from 1.25V to 3.7V, where 5V and 3.3V voltage supplies are avail- able. AME1505 has 2 new features: First, a remote Sense pin is wire...

DLC549GGU980-80

The change in output voltage due to a specified change in load current. It includes the effects of self-heating. Load regulation is expressed in either microvolts per milliampere, parts-per- million per milliampere, or ohms of dc output resistance.

DLC549GGU980-80

The change in output voltage due to a specified change in load current. It includes the effects of self-heating. Load regulation is expressed in either microvolts per milliampere, parts-per- million per milliampere, or ohms of dc output resistance.

DLC-6ID

DLC-6ID(V4)

DLC-6SGD

DLC-6SGD(V4)

DLC-6SRD(V6)

DLC-6YD(V5)

DLCL-501N7SDG

Vendor:CITIZEN ?Package Cooled:2007PB?D/C:3097

Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load. 2. Minimum rise/fall times are guaranteed at minimum specified load. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500Ω resistor in parallel.

DLD 2.5 PE-DB

DLDPUNCH

DLF2000

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

DLF-4000

DLFC0735P-101A

Vendor:NECPackage Cooled:SMDD/C:09+

DLG3416

DLH36000B11BQC

DLH36000B11CQC

Vendor:QFPPackage Cooled:81D/C:DSP

• Head Office (Hi-Sincerity Microelectronics Corp.): 10F.,No. 61, Sec. 2, Chung-Shan N. Rd. Taipei Taiwan R.O.C. Tel: 886-2-25212056 Fax: 886-2-25632712, 25368454 • Factory 1: No. 38, Kuang Fu S. Rd., Fu-Kou Hsin-Chu Industrial Park Hsin-Chu Taiwan. R.O.C Tel: 886-3-5983621~5 Fax: 886-3-5982931

DLH36107

DLH36107CAE11AQC

DLH36107TAA11BQC

Vendor:DSPPackage Cooled:03+D/C:12560

DLH36117KA11FQC

Vendor:TIPackage Cooled:QFPD/C:08+

DLH36117KA11FQC

Vendor:TIPackage Cooled:QFPD/C:08+

DLH36117KAA11AQC

Vendor:DSPPackage Cooled:QFP1420-100D/C:02+

HIGH SPEED: tPD = 3.5ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA = 25C HIGH NOISE IMMUNITY: VNIH = VNIL = 10% VCC (MIN.) POWER DOWN PROTECTION ON INPUT SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) at VCC = 4.5V BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V IMPROVED LATCH-UP IMMUNITY

DLH36117KAE51AQC

Vendor:DSPPackage Cooled:QFPD/C:2004

The Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 for the CAT24FC02 (see Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to

DLH36117KAG51AQC

Vendor:DSPPackage Cooled:QFPD/C:2008+

The PWR_DWN# signal is an asynchronous, active-low LVTTL input that places the device in a low power inac- tive state without removing power from the device. All internal clocks are turned off, and all clock outputs are held low. Since PWR_DWN# is asynchronous, the signal is syn- chronized internally to each individual clock. As shown in Figure 3, a falling-rising-falling edge sequence on any individual clo...

DLH36117KAH51CQC

Vendor:DSPPackage Cooled:QFPD/C:04+

ideal for many applications in the HVAC/R industry as well as for industrial systems. Some applications include global commercial rooftop A/C, global chiller applications, industrial pumps, material handlers, elevators, escalators, air compressors and industrial systems.

DLH36117KAI51AQC

Vendor:DSPPackage Cooled:QFPD/C:04+

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information,...

DLH36117KAK51BQC

Vendor:DSP ?Package Cooled:2004?D/C:2421

The modem can connect to a host system serially (RS-232 functionality), or as an 8-bit peripheral to the processor in a host system. The TMS320C54V90 uses a standard Digital Signal Processor (DSP) and proprietary firmware to perform all the modem signal processing, the V.42/V.42bis compression, and AT commands interpretation for modem control functions.

DLH36117KAL51BQC

Vendor:DSPGPackage Cooled:QFP100D/C:4

The ACQ/ACTQ utilizes Fairchild Quiet Series¥ technol- ogy to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series¥ fea- tures GTO¥ output control and undershoot corrector in addition to a split ground bus for superior performance.

DLH36117KBF51CQC

Vendor:DSPPackage Cooled:QFP100D/C:04+

The device is available with an access time of 55, 60, 70, or 90 ns and is offered in 48-pin TSOP and 63-ball F i n e P i t c h B G A p a ck a g e s . S t a n d a r d c o n t r o l pinschip enable (CE#), write enable (WE#), and out- put enable (OE#)control normal read and write op- erations, and avoid bus contention issues.

DLH36119

Vendor:DSPD/C:05+

DLH36127ACA11CQC

Package Cooled:QFPD/C:05+

144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set an...