DQ2817A-25

Vendor:SEEQD/C:DIP

CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation.

DQ2817A-250/200

Vendor:SEEQPackage Cooled:CDIPD/C:N/A

DQ2817A-350

Vendor:SEEQPackage Cooled:DIPD/C:90+

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be⋅M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (200 to 400 MHz). The M-value must be programmed by the ser...

DQ2817A-350

Vendor:SEEQPackage Cooled:DIPD/C:90+

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be⋅M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (200 to 400 MHz). The M-value must be programmed by the ser...

DQ2817A-45

Vendor:SEEQPackage Cooled:DIP

DQ2864

Vendor:305Package Cooled:SEEQD/C:N/A

Amplitude compensation (harmonic compensation) To maintain appropriate auditory balance for the treble region that is made up of harmonic components, a high- speed detector and high-performance VCA circuit are used for amplitude control of the treble component. The amount of compensation is determined from a calcula- tion performed based on the DC level input to the CTL1 pin, and the DC level detecte...

DQ2864-250

Vendor:11Package Cooled:SEEQD/C:N/A

Overcharging and Over-Discharging Dedicated for One-Cell Applications Integrated Low-Impedance MOSFET Switch and Sense Resistor Precision Trimmed Overcharge and Overdischarge Voltage Limits Extremely Low Power Drain 3-A Current Capacity Overcurrent and Short-Circuit Protection Reverse Charger Protection Thermal Protection

DQ2864-300

Vendor:SEEQPackage Cooled:DIPD/C:N/A

Note 1. Test voltage must be applied within dv/dt rating. Note 2. Guaranteed to trigger at an IF value less than or equal to max. IFT , recommended IF lies between Rated IFT and absolute max. IFT . Note 3. Measured with input leads shorted together and output leads shorted together.

DQ2864A

Vendor:SeeQD/C:08+

cleared immediately, and remains cleared. If the power is restored (no UVREG or UVREF), and if no OVERTEMP fault exists, then the latched fault remains cleared when the RESET line returns to high. However, FAULT = 1 may still occur because a UVBOOT fault condition may still exist.

DQ2864A-15

Vendor:SEEQPackage Cooled:DIPD/C:N/A

• ML22Q54 The ML22Q54 is a speech synthesis device with a 4-Mbit flash memory built in. The voice data can be easily written to the flash memory using a special tool. The on-chip flash memory product is suitable for the diversified low volume production or short delivery time applications that the on-chip mask ROM product cannot support. The ML22Q54 is most suitable for evaluation because the circui...

DQ2864A-150

Vendor:SEEQPackage Cooled:DIPD/C:N/A

The IDT71V2576/78 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V2576/78 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self- timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V2576/78 can provide f...

DQ2864H-200

Vendor:SeeQPackage Cooled:CDIP28D/C:2007+

DQ2864H-250

Vendor:SEEQPackage Cooled:DIPD/C:92+

1. Hitachi neither warrants nor grants licenses of any rights of Hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Pr...

DQ28C256250

Vendor:seeqPackage Cooled:seeqD/C:dc97

DQ28C256-256

DQ28C256-300

Vendor:SEEQD/C:CDIP-28

DQ28C256-300

Vendor:SEEQD/C:CDIP-28

DQ28C256A-150

Vendor:SEEQD/C:DIP

The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (D...

DQ28C256A-200

Vendor:DIPPackage Cooled:SEEQD/C:04+

the part number LM26CIM5-TPA has TOS = 85˚C, and programmed as an active-low open-drain overtemperature shutdown output. • the part number LM26CIM5-FPD has TUS = −5˚C, and programmed as an active-high, push-pull undertemperature shutdown output. Active-high open-drain and active-low push-pull options are available, please contact National Semiconductor for more informa- tion.

DQ28C64-150

DQ28C64-15DC

Vendor:SEEQD/C:DIP

DQ28C64-200

Vendor:105Package Cooled:SEEQD/C:N/A

• When an HF signal is input, it is sliced to precise levels and converted to an EFM signal. The phase is compared with the internal VCO and a PLL clock is reproduced at an average frequency of 4.3218 MHz. • Precise timing for a variety of required internal timing needs (including the generation of the reference clock) is produced by the attachment of an external 16.9344 MHz crystal o...

DQ28C64-250/200/350

DQ28C64-300

Vendor:SEEQPackage Cooled:CDIP28D/C:——

The NCP1086 voltage regulator series provides adjustable and 3.3 V output voltages at currents up to 1.5 A. The regulator is protected against overcurrent conditions and includes thermal shutdown. The NCP1086 series has a composite PNP−NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Consideratio...

DQ28C64-300

Vendor:SEEQPackage Cooled:CDIP28D/C:——

The NCP1086 voltage regulator series provides adjustable and 3.3 V output voltages at currents up to 1.5 A. The regulator is protected against overcurrent conditions and includes thermal shutdown. The NCP1086 series has a composite PNP−NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Consideratio...

DQ28C64DM-20

DQ28C65

Vendor:SEEQPackage Cooled:DIP

Note: 1) Inverter low-side is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one control IC which has gate driving, current sensing and protection functions. 2) Inverter power side is composed of four inverter dc-link input pins and three inverter output pins. 3) Inverter high-side is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IG...

DQ28C65-200

Vendor:SEEQPackage Cooled:CDIPD/C:N/A

Recovered Serial Data. These ECL 100K outputs (+5V referenced) represent the recovered data from the input data stream (RIN). This recovered data is aligned with the recovered clock (RCLK) with a sampling window compatible with most data processing devices.

DQ28C65-250

Vendor:63Package Cooled:SEEQD/C:N/A

Therefore, do not burn, destroy, cut, crush, or chemi- cally decompose the product, since gallium arsenide material in powder or vapor form is harmful to human health. Observe the relevant laws and regulations when disposing of the products. Do not mix them with ordinary industrial waste or household refuse when disposing of GaAs-containing products.

DQ28C65-25D

Vendor:SEEQPackage Cooled:DIPD/C:00+

DQ28C65A

D/C:08+

DQ28HC256

DQ28HC25680

DQ36C32-35

Vendor:SEEQPackage Cooled:N/AD/C:89

Motorola is offering the Chip Pak option package. ApplicationCspecific parts will have an SPX prefix, followed by a four digit number, unique to the specific customer. Devices will be shipped in a tape and reel packaging. NOTE: The die and wire bonds are exposed on the front side of the Chip Pak (pressure is applied to the backside of the device). Front side die and wire protection must be provided in ...

DQ408AK/883

DQ48F010-25

Vendor:SEEQD/C:CDIP

DQ48F512-20

Vendor:SEEQPackage Cooled:DIP

DQ48F512-200

DQ48F512-25

Vendor:SEEQPackage Cooled:DIP32陶瓷D/C:89+

DQ48F512-250

Vendor:29Package Cooled:SEEQD/C:N/A

o 4 Dedicated Comparators plus 1 Auxiliary Comparator o 5V Dedicated Comparator Has 1.25% Accuracy o -5V, +12V, -12V, +15V, -15V Dedicated Comparators Have 1.5% Accuracy o Overvoltage/Undervoltage Detection or Programmable Delay Using Auxiliary Comparator o Internal 1.24V Reference with 1% Initial Accuracy o Wide Supply Range: 2.7V to 11V o Built-In Hysteresis o 250µA Max Supply Current ...

DQ48F512-250

Vendor:29Package Cooled:SEEQD/C:N/A

o 4 Dedicated Comparators plus 1 Auxiliary Comparator o 5V Dedicated Comparator Has 1.25% Accuracy o -5V, +12V, -12V, +15V, -15V Dedicated Comparators Have 1.5% Accuracy o Overvoltage/Undervoltage Detection or Programmable Delay Using Auxiliary Comparator o Internal 1.24V Reference with 1% Initial Accuracy o Wide Supply Range: 2.7V to 11V o Built-In Hysteresis o 250µA Max Supply Current ...

DQ5133

Vendor:SeeQPackage Cooled:CDIPD/C:06+

DQ5133-200

Vendor:SEEQPackage Cooled:DIP-28D/C:03+

Note 1: Specifications to -40C are guaranteed by design and not production tested. All typical values are guaranteed by design characterization and are not production tested. Note 2: Tested with TA = +25C, DVDD = 3.3V, and all peripherals inactive except for port pins. Note 3: These numbers are guaranteed by design and are not tested. Note 4: Can be calculated as (fHFXIN / 6). Note 5: Can be calculated as 6...

DQ5133-200

Vendor:SEEQPackage Cooled:DIP-28D/C:03+

Note 1: Specifications to -40C are guaranteed by design and not production tested. All typical values are guaranteed by design characterization and are not production tested. Note 2: Tested with TA = +25C, DVDD = 3.3V, and all peripherals inactive except for port pins. Note 3: These numbers are guaranteed by design and are not tested. Note 4: Can be calculated as (fHFXIN / 6). Note 5: Can be calculated as 6...

DQ5133-300

Vendor:SEEQPackage Cooled:CWDIP28D/C:——

Hynix HYMD116645B(L)8J-J series incorporates SPD(serial presence detect). Serial presence detect function is implement-ed via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden- tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

DQ5143-200

Vendor:SEEQPackage Cooled:DIP

OFFSET VOLTAGE OFFSET CURRENT TEST The offset voltage and offset current tests are performed in the same general way as the bias current test The only difference is that the switches S5a and S5b are closed on the same half-cycle of the triangular wave input The synchronous operation of S5a and S5b forces the ampli- fier under test to draw its input currents through matched high and low input resistors on...

DQ5143-250

Vendor:SEEQPackage Cooled:CWDIP28D/C:——

Load Regulation Parasitic line resistance can degrade load regulation. In order not to affect the behavior of the regulator, it is best to connect directly the R1 resistance from the resistor divider to the case, and not to the load. For the same reason, it is best to connect the resistor R2 to the Negative side of the load.

DQ5143-250

Vendor:SEEQPackage Cooled:CWDIP28D/C:——

Load Regulation Parasitic line resistance can degrade load regulation. In order not to affect the behavior of the regulator, it is best to connect directly the R1 resistance from the resistor divider to the case, and not to the load. For the same reason, it is best to connect the resistor R2 to the Negative side of the load.

DQ5143-300

Vendor:SEEQPackage Cooled:DIP-28D/C:03+

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltag...

DQ5143-450

Package Cooled:1D/C:DIP-28

A decoupling capacitor of 0.01µF must be connected between VDD (pin 2) and GND (pin 4), as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.

DQ5213H

D/C:08+

The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the 16th clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data are transmitted to the host through DATA OUT. The number of serial clock pulses used also dep...

DQ52B13

DQ52B33

Package Cooled:DIP

The Bluetooth controller consists of a number of functional blocks that operate under control of the embedded microcontroller. The microcontroller has access to these blocks via the AMBA System Bus (ASB) and the VLSI Peripheral Bus (VPB).

DQ52B33-250

Vendor:12D/C:N/A

block write and block read operation from any external I2C controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read opera- tions, the system controller can access individual indexed bytes. The offset of the indexed byte i...

DQ52B33-250

Vendor:12D/C:N/A

block write and block read operation from any external I2C controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read opera- tions, the system controller can access individual indexed bytes. The offset of the indexed byte i...

DQ52B33H-350

Vendor:SEEQPackage Cooled:CDIPD/C:N/A

DQ52B33H-350

Vendor:SEEQPackage Cooled:CDIPD/C:N/A

DQ52BB-350

Vendor:SEEQPackage Cooled:DIP

DQ7652

Vendor:DIPPackage Cooled:.D/C:04+

DQ8451

Vendor:DELCOPackage Cooled:DIP40

DQ9232DQ-T1

Vendor:SIPackage Cooled:SOP/8D/C:00+

MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2 register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port A Read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset.

DQ9232H

Vendor:PHILIPSPackage Cooled:QFP80D/C:08+

To achieve contrast control, pin 1 is shorted to pin 2 and pin 3 is shorted to pin 4. The voltages at pins 1 and 4 are con- trolled by the input voltage at pin seven. As the voltage at pin 7 increases, the voltages at pins 1 and 4 become offset. With pin 7 at zero volts, pins 1 and 4 are at minimum offset and the contrast is set to the minimum value of -38dB typical. With pin 7 at 4V, pins 1 and 4 are ...

DQ9233DQ-T1

Vendor:SILICOPackage Cooled:TSOPD/C:08+

• Acquisition: C Feature selection via special function register C Simultaneous reception of TTX, VPS, and WSS C Fixed framing code for VPS and TTX C Acquisition during VBI C Direct access to VBI RAM buffer C Acquisition of packets x/26, x/27, 8/30 (firmware) C Assistance of all relevant checks (firmware) C 1-bit framing code error tolerance (switchable) • Display: C Features selec...

DQXO-3-6.13KHZ

Package Cooled:CAN3D/C:120

DQY008

DR04083

Package Cooled:06+D/C:DIP-28

Zener Voltage Range − 3.3 V to 200 V ESD Rating of Class 3 (>16 kV) per Human Body Model Flat Handling Surface for Accurate Placement Package Design for Top Side or Bottom Circuit Board Mounting Pb−Free Packages are Available

DR04083

Package Cooled:06+D/C:DIP-28

Zener Voltage Range − 3.3 V to 200 V ESD Rating of Class 3 (>16 kV) per Human Body Model Flat Handling Surface for Accurate Placement Package Design for Top Side or Bottom Circuit Board Mounting Pb−Free Packages are Available

DR06522

Vendor:BENPackage Cooled:QFP/48D/C:96+

The sensor array is composed of 300 rows and 300 columns of sensor plates. Associated with each column are two sample-and-hold circuits. A fingerprint image is sensed or captured one row at a time. Thisrow captureoccurs in two phases. In the first phase, the sensor plates of the selected row are pre-charged to the VDD voltage. During this pre-charge period, an internal signal enables the firs...

DR06M

DR07965

Vendor:SYMBIOSPackage Cooled:N/AD/C:95

NOTES: 1. Minimums are guaranteed but not production tested. 2. This parameter is guaranteed but not production tested. 3. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.12ns for CL = 50pF. Since this time constant is much smaller than the rise and fall times o...

DR1030-100-R

DR1030-101-R

DR1030-150-R

DR1030-151-R

DR1030-220-R

DR1030-3R9-R

DR1040-151-R

DR1040-221-R

DR1040-331-R

DR1040-7R0-R

DR1040-8R2-R

DR1050-1R5-R

DR1050-221-R

DR1050-2R2-R

DR1050-330-R

DR1050-391-R

DR1050-8R2-R

DR1112C

Vendor:.D/C:07+

DR119

Vendor:ROHM

RS is the parasitic series resistance of the diode, the sum of the bondwire and leadframe resistance, the resistance of the bulk layer of silicon, etc. RF energy coupled into RS is lost as heat it does not contribute to the rectified output of the diode. CJ is parasitic junction capacitance of the diode, controlled by the thickness of the epitaxial layer and the diameter of the Schottky contact. R j...

DR122G408

Vendor:GENSD/C:99

Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may af- fect reliability.

DR124-1R0-R

DR124-1R5-R

DR124-220-R

DR124-331-R

DR124-4R7-R

DR125-3R3-R

EUROPE: LDC for ON Semiconductor C European Support German Phone: (+1) 303C308C7140 (MonCFri 2:30pm to 7:00pm CET) Email: ONlitCgerman@hibbertco.com French Phone: (+1) 303C308C7141 (MonCFri 2:00pm to 7:00pm CET) Email: ONlitCfrench@hibbertco.com English Phone: (+1) 303C308C7142 (MonCFri 12:00pm to 5:00pm GMT) Email: ONlit@hibbertco.com

DR125-4R7

Vendor:COOPERD/C:07/08+

Parameter Carrier Frequency Operating Voltage (VDD_MEM) Operating Voltage (VDD_PIO) RF Output Power RX Sensitivity Load Impedance Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Average Current Consumption

DR125-4R7

Vendor:COOPERD/C:07/08+

Parameter Carrier Frequency Operating Voltage (VDD_MEM) Operating Voltage (VDD_PIO) RF Output Power RX Sensitivity Load Impedance Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Average Current Consumption

DR127-100-R

Vendor:COOPERPackage Cooled:SMD电感D/C:06+

The XPLA3 architecture follows a simple timing model that allows deterministic timing in design and redesign. The basic timing model is shown in Figure 2. One key feature of the XPLA3 CPLD is the ability to have up to 48 product term inputs into a single macrocell and maintain consistent tim- ing. This is achieved through the use of a fully populated PLA (Programmable AND Programmable OR Array) which ...

DR127-100-R

Vendor:COOPERPackage Cooled:SMD电感D/C:06+

The XPLA3 architecture follows a simple timing model that allows deterministic timing in design and redesign. The basic timing model is shown in Figure 2. One key feature of the XPLA3 CPLD is the ability to have up to 48 product term inputs into a single macrocell and maintain consistent tim- ing. This is achieved through the use of a fully populated PLA (Programmable AND Programmable OR Array) which ...