D30131F1

Vendor:NECD/C:03+

The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever the I/O, RST , or VCC pins are high. When using the 1-Wire port in battery operate mode, RST and VCC provide no power since they are low. However, I/O will provide sufficient power as long as the specified timing and voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasit...

D30133F1

The Intersil ISL422XE devices are 2.7V to 5.5V powered RS-232 transmitters/receivers which meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Additionally, they provide 15kV ESD protection (IEC61000-4-2 Air Gap, and Human Body Model) on transmitter outputs and receiver inputs (RS-232 pins). Targeted applications are PDAs, Palmtops, and hand-held products where the low operational, and...

D30133F1

The Intersil ISL422XE devices are 2.7V to 5.5V powered RS-232 transmitters/receivers which meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Additionally, they provide 15kV ESD protection (IEC61000-4-2 Air Gap, and Human Body Model) on transmitter outputs and receiver inputs (RS-232 pins). Targeted applications are PDAs, Palmtops, and hand-held products where the low operational, and...

D30200GD-100

Vendor:NECPackage Cooled:QFPD/C:N/A

The HAL 805 features a temperature-compensated Hall plate with choppered offset compensation, an A/D converter, digital signal processing, a D/A converter with output driver, an EEPROM memory with redun- dancy and lock function for the calibration data, a serial interface for programming the EEPROM, and protection devices at all pins. The internal digital signal processing is of great benefit because...

D30200GD-100

Vendor:NECPackage Cooled:QFPD/C:N/A

The HAL 805 features a temperature-compensated Hall plate with choppered offset compensation, an A/D converter, digital signal processing, a D/A converter with output driver, an EEPROM memory with redun- dancy and lock function for the calibration data, a serial interface for programming the EEPROM, and protection devices at all pins. The internal digital signal processing is of great benefit because...

D30200GD-133

Vendor:NECPackage Cooled:QFPD/C:N/A

When the ORG* pin is connected to VCC, the (x16) organization is selected. When it is connected to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/ BUSY status during a programming operat...

D30210GD-133

Vendor:NETPackage Cooled:SMD

Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to VCC. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device in the programming state allowing programming address, data and VPP to be applied for programming o...

D30210GD-133/167

Vendor:NECPackage Cooled:QFP120D/C:08+09+

D30210GD-133VR4310

Vendor:NECPackage Cooled:QFP2828-120

D30210GD-167

Package Cooled:QFP/240D/C:08+09+

The counter is loaded digit by digit corresponding to the digit strobe outputs. BCD thumb wheel switches with four diodes per decade connected between the digit strobe outputs and the BCD inputs is one method to supply BCD data for loading the counter decades.

D30210GD-177

Vendor:NECPackage Cooled:04+D/C:QFP

D30210GD-177

Vendor:NECPackage Cooled:04+D/C:QFP

D3031

Vendor:SILICOREPackage Cooled:08+D/C:1500

As Figure 4 shows, the TVSF Polymer device is reliable and stable over a duration of hundreds of pulses. The TVSF device has been tested with fast rate ESD pulses at 8kV contact discharge. Clamping voltage relatively consistent through 500 pulses. This is far more than most equipment would see in a lifetime.

D3031

Vendor:SILICOREPackage Cooled:08+D/C:1500

As Figure 4 shows, the TVSF Polymer device is reliable and stable over a duration of hundreds of pulses. The TVSF device has been tested with fast rate ESD pulses at 8kV contact discharge. Clamping voltage relatively consistent through 500 pulses. This is far more than most equipment would see in a lifetime.

D3037TF

Vendor:QFP-64Package Cooled:HITD/C:2004+

The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC.

D3037TF

Vendor:QFP-64Package Cooled:HITD/C:2004+

The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC.

D30380GD-25

Vendor:NECPackage Cooled:50D/C:N/A

D30412LRJ-200

Vendor:4Package Cooled:NECD/C:N/A

(EIAJ1201) Sampling Rate: 32/44.1/48/88.2/96 kHz Recover 128 / 256 / 384 / 512 fs System Clock Very Low Jitter System Clock Output (80ps Typically) On-Chip Master Clock Oscillator, Only an External 12.000 MHz or 16.000 MHz Crystal Is Required Selectable Output PCM Audio Data Format Output User Bit Data, Flag Signals, and Channel Status Data With Block Start Signal Single + 3.3-V Power Supply Package: 28...

D30412LRJ-200

Vendor:4Package Cooled:NECD/C:N/A

(EIAJ1201) Sampling Rate: 32/44.1/48/88.2/96 kHz Recover 128 / 256 / 384 / 512 fs System Clock Very Low Jitter System Clock Output (80ps Typically) On-Chip Master Clock Oscillator, Only an External 12.000 MHz or 16.000 MHz Crystal Is Required Selectable Output PCM Audio Data Format Output User Bit Data, Flag Signals, and Channel Status Data With Block Start Signal Single + 3.3-V Power Supply Package: 28...

D30412LRJ-75

D30412RJ-75

Vendor:1Package Cooled:NECD/C:N/A

As the LEDs are driven directly by the MCU, care had to be taken to avoid drawing excessive currents from port pins or exceeding the specified current or dissipation capability of the 5 volt regulator. The digit current for an acceptable brightness is too high for a port pin so FET buffers are incorporated. The segment resistors of 220R were chosen to give a segment current of 10mA so the digit current c...

D3044TE

Functional Tests (In Freescale Test Fixture, 50 ohm system) VDD = 26 Vdc, IDQ = 2400 mA, Pout = 40 W Avg. N−CDMA, f = 880 MHz, Single−Carrier N−CDMA, 1.2288 MHz Channel Bandwidth Carrier. ACPR measured in 30 kHz Channel Bandwidth @ 750 kHz Offset. Peak/Avg. Ratio = 9.8 dB @ 0.01% Probability on CCDF.

D3044TE

Functional Tests (In Freescale Test Fixture, 50 ohm system) VDD = 26 Vdc, IDQ = 2400 mA, Pout = 40 W Avg. N−CDMA, f = 880 MHz, Single−Carrier N−CDMA, 1.2288 MHz Channel Bandwidth Carrier. ACPR measured in 30 kHz Channel Bandwidth @ 750 kHz Offset. Peak/Avg. Ratio = 9.8 dB @ 0.01% Probability on CCDF.

D30450GD-80

Package Cooled:06+D/C:800

Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. If the command byte is reserved and therefore not valid, it will not be acknowledged. Only valid command bytes will be acknowledged.

D3045BGT

Vendor:N/APackage Cooled:60D/C:N/A

EN - Is the enabling input for the bridge. This digital input, when pulled low, will enable the bridge, following the inputs from AL, BL, CL and AH, BH, CH inputs. When pulled high, it will override all other inputs and disable the bridge. It is inter- nally pulled high to VBIAS, and can be driven by logic levels up to VBIAS.

D304X

Vendor:JLIPackage Cooled:TO-220D/C:04+

In order to detect whether the boot block feature is set on the first/last 8K-byte block or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address 0002(hex) for first(bottom) location or FFF2(hex) for last(top) location.If the DQ0/DQ1 of output data is "1,&qu...

D30500RJ-200

Vendor:NECPackage Cooled:PGAD/C:97+98+00+

D30500S2-150

Vendor:NECPackage Cooled:QFP

These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electrically-insulating, thermally-conductive "pads" ma...

D30500S2-150

Vendor:NECPackage Cooled:QFP

These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electrically-insulating, thermally-conductive "pads" ma...

D30500S2-150VR5000

D30500S2-180

*Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

D30500S2-180

*Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

D30500S2-200

Vendor:NECPackage Cooled:06+D/C:800

COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definition in Hex table on page 11 (I/O8 - I/O15 are dont care inputs for the command codes). The comman...

D30500SI-200

Vendor:NECPackage Cooled:04D/C:156

The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL is HIGH (this is a start bit) prior to the expiration of the watchdog time-out period to prevent a RESET signal. The state of two nonvolatile control bits

D30500SZ-200

Package Cooled:06+D/C:800

The over range devices display 1 and decimal point. The character height and package configuration are the same as the numeric and hexadecimal devices. Character selection is obtained via external switching transistors and current limiting resistors.

D3050QA82-250

Vendor:NECPackage Cooled:QFP

D30541GD

Package Cooled:06+D/C:800

To measure a refractive index, the LED must be illuminated during the measurement cycle, although not necessarily for the entire measurement cycle. An external current-limiting resistor should be used to ensure that the LED does not experience excessive currents.

D30541GD-1GT

D30541GD-200

Vendor:NECD/C:05+

• Untinted non diffused lens • Utilizing ultrabright AllnGaP and InGaN technology • Very high luminous intensity • Very small emission angle • High operating temperature: Tj (chip junction temperature) up to 125 C for AllnGaP devices • Luminous intensity and color categorized for each packing unit • ESD-withstand voltage: 2 kV acc. to MIL STD 883 D, ...

D3055

Vendor:国产/进口Package Cooled:F-2D/C:09

3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +85C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User selectable size Data RAM: 192 bytes Data EEPROM: 128 bytes User Programmable Options 24 I/O pins, fully programmable as: C Input with pull-up resistor C Input wi...

D30550AGD-350

Package Cooled:N/AD/C:08+

D30550F2-400

D3055GC 003

Vendor:NECPackage Cooled:TPQFPD/C:94+

D3055VL

Vendor:MotorolaPackage Cooled:SOT-252

Following a START condition the bus master must output the address of the slave it is accessing. The address of the D3055VL is shown in Figure 3. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW.

D3055VL

Vendor:MotorolaPackage Cooled:SOT-252

Following a START condition the bus master must output the address of the slave it is accessing. The address of the D3055VL is shown in Figure 3. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW.

D305A

Vendor:ROGERSPackage Cooled:MSOP-10D/C:06+

The MSK 3020 is an H-bridge power circuit packaged in a space efficient isolated ceramic tab power SIP package. The MSK 3020 consists of P-Channel MOSFETs for the top transistors and N-Channel MOSFETs for the bottom transistors. The N Channel MOSFETS are current sensing to allow lossless current sensing for current controlled applications. The MSK 3020 uses M.S. Kennedy's proven power hybrid technology to b...

D305A

Vendor:ROGERSPackage Cooled:MSOP-10D/C:06+

The MSK 3020 is an H-bridge power circuit packaged in a space efficient isolated ceramic tab power SIP package. The MSK 3020 consists of P-Channel MOSFETs for the top transistors and N-Channel MOSFETs for the bottom transistors. The N Channel MOSFETS are current sensing to allow lossless current sensing for current controlled applications. The MSK 3020 uses M.S. Kennedy's proven power hybrid technology to b...

D305A-M04

Vendor:DURELPackage Cooled:MSOP-10D/C:04+

or Powered-Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Ω Typical) Rail-to-Rail Switching on Data I/O Ports − 0- to 5-V Switching With 3.3-V VCC − 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow, With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical) Fast...

D305A-M04

Vendor:DURELPackage Cooled:MSOP-10D/C:04+

or Powered-Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Ω Typical) Rail-to-Rail Switching on Data I/O Ports − 0- to 5-V Switching With 3.3-V VCC − 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow, With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical) Fast...

D3065015-002

The LTC6900 operates with a single 2.7V to 5.5V power supply and provides a rail-to-rail, 50% duty cycle square wave output. The CMOS output driver ensures fast rise/fall times and rail-to-rail switching. The frequency-setting resistor can vary from 10kΩ to 2MΩ to select a master oscillator frequency between 100kHz and 20MHz (5V supply). The three-state DIV input determines whether the master clo...

D30671F2-400

SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 sele...

D306A

Vendor:120

Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a 'dummy' write operation by sending the START condition, slave address and word address of the location it wishes to read. After the IS24CXX acknowledge the word address, the Master device resends the START condition and the slave address, this time with th...

D30700LRS-250

Vendor:NECD/C:98+

PARAMETER Reference Voltage VREF Voltage Fb Voltage Line Regulation UVLO UVLO Threshold - VCC UVLO Hysteresis - VCC UVLO Threshold - VC UVLO Hysteresis - VC UVLO Threshold - Fb UVLO Hysteresis - Fb Supply Current VCC Dynamic Supply Current VC Dynamic Supply Current VCC Static Supply Current VC Static Supply Current Soft-Start Section Charge Current Oscillator Frequency

D30700RS-200

Vendor:NECPackage Cooled:CPGA

fOSC(tc)Oscillator frequency over line and temperature Trimmed for 360 kHz (1) Ensured by design. Not production tested. (2) Maximum 450-kHz frequency can be achieved when both channels are enabled. (3) 270 kHz is the default frequency during start-up for both channels. (4) See Table 1. (5) See PWM detailed description

D30710AF5-400

Vendor:NECPackage Cooled:BGA

Up to 630 Mbps Simplex (Point-to-Point) and Half-Duplex (Multipoint) Interface Typical Differential Output Voltage of 340 mV Into a 50-Ω Load Integrated 110-Ω Line Termination on LVDM1677 Product Propagation Delay Time: − Driver: 2.5 ns Typ − Receiver: 3 ns Typ Recommended Maximum Transfer Rate: − Driver: 650 M-Transfers/s − Receiver: 350 M-Transfers/s Driver is High...

D30710AF5-400

Vendor:NECPackage Cooled:BGA

Up to 630 Mbps Simplex (Point-to-Point) and Half-Duplex (Multipoint) Interface Typical Differential Output Voltage of 340 mV Into a 50-Ω Load Integrated 110-Ω Line Termination on LVDM1677 Product Propagation Delay Time: − Driver: 2.5 ns Typ − Receiver: 3 ns Typ Recommended Maximum Transfer Rate: − Driver: 650 M-Transfers/s − Receiver: 350 M-Transfers/s Driver is High...

D30720F5-550

Vendor:NECPackage Cooled:BGA

The LTC®3450 is a complete power converter solution for small thin film transistor (TFT) liquid crystal display (LCD) panels. The device operates from a single Lithium-Ion cell, 2- to 3-cell alkaline input or any voltage source between 1.5V and 4.6V.

D30720FG550

D3072F1

Package Cooled:N/AD/C:BGA

The PTHxx050Y are a series of ready- to-use switching regulator modules from Texas Instruments designed specifically for bus termination in DDR and QDR memory applications. Operating from either a 3.3-V, 5-V or 12-V input, the modules generate a VTT output that will source or sink up to 6 A of current (8 A transient) to accu- rately track their VREF input. VTT is the required bus termination suppl...

D30730F5-700

D3088-99

D30AGD

D30M1M9-70

D30N03

Vendor:GFPackage Cooled:07+D/C:TO-251

1. Storage Under normal circumstances, storage of beam lead diodes in Agilent supplied waffle/gel packs is sufficient. In particularly dusty or chemically hazardous environ- ments, storage in an inert atmo- sphere desiccator is advised.

D30N03

Vendor:GFPackage Cooled:07+D/C:TO-251

1. Storage Under normal circumstances, storage of beam lead diodes in Agilent supplied waffle/gel packs is sufficient. In particularly dusty or chemically hazardous environ- ments, storage in an inert atmo- sphere desiccator is advised.

D30N06

Vendor:MOTPackage Cooled:07+D/C:TO-251

5. Output clip detection function (pin(1)) The output clip detection terminal of pin(1) has the open collector output structure on chip as shown in Fig.5. In case that the output waveform is clipping, the clip detection circuit is operated and NPN Tr. is turned on. It is possible to improve the tone quality with the current of flowing into pin(1) and with controlling the volume, tone control circuit thro...

D30NE06

This block generates the system timing and control signal supplied to the CPU and on-chip peripherals. There are two types of system clock sources: a built-in RC oscillator or an external ceramic resonator. Both of them are mask optional and generate a 4MHz system clock. They also generate 2MHz for the CPU, and 1 MHz for the base timer. The following shows the relationship of code type number with oscillatio...

D30NF

Package Cooled:TO-3D/C:05+

D30S04M

Package Cooled:TOP-3AD/C:00+

The efficient 32-bit, 33MHz target-only PCI interface is compliant with version 2.2 of the PCI Bus Specification and version 1.0 of PCI Power Management Specification. For applications that do not require the internal parallel port or the local Bus, card designers can assign a Subsystem Vendor ID and a Subsystem ID using 32 input pins. If the UARTs are not required, the Local Bus can be extended from ...

D30U20S

Vendor:SECPackage Cooled:TO-220FD/C:00+

UC3874-1 is designed for logic level MOSFETs and has UVLO turn-on and turn-off thresholds of 4.5V and 4.4V respectively. The UC3874-2 is designed for standard power MOSFETs and has UVLO turn-on and turn-off thresholds of 10V and 9V respectively. A precision 2.5V reference can supply 20mA to external circuitry. An error amplifier with soft start, high bandwidth current amplifier, and a synchronizable ...

D30VT80

Vendor:282

Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider when S_LOAD tran- sitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input ...

D31/KFM6022W2

D/C:150000

The 33996 directly interfaces with microcontrollers and is compatible with both 3.3 V and 5.0 V CMOS logic levels. The 33996, in effect, serves as a bus expander and buffer with fault management features that reduce the MCUs fault management burden.

D31/KFM6022W2

D/C:150000

The 33996 directly interfaces with microcontrollers and is compatible with both 3.3 V and 5.0 V CMOS logic levels. The 33996, in effect, serves as a bus expander and buffer with fault management features that reduce the MCUs fault management burden.

D31/KFM6022WS

Package Cooled:NEW D/C:0

D31004NL

D/C:08+

Package power dissipation is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125oC. The maximum allowable I...

D3100GS

Vendor:NECD/C:05+

LINEARITY Linearity refers to how well a transducers output follows the equation: Vout = Voff + sensitivity x P over the operating pressure range. There are two basic methods for calculating nonlinearity: (1) end point straight line fit (see Figure 5) or (2) a least squares best line fit. While a least squares fit gives the best case linearity error (lower numerical value), the calculations required...

D3104

Vendor:INTELPackage Cooled:CDIP24D/C:91

AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 Ω to VTT. Based upon recommended crystal specifications as outlined in operation section. C3 dB point of PLL transfer characteristics.

D31-1

Vendor:NECD/C:08+

This family is a 16M bit dynamic RAM organized 4,194,304 x 4-bit configuration with Fast Page mode CMOS DRAMs. Fast Page mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(50, 60 or 70ns) and refresh cycle(2K ref. or 4K ref.) and power consumption (Normal o...

D3117S

During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time.

D3118769

Vendor:SUNPackage Cooled:06+D/C:800

D313-2SD313

Vendor:FSC-CHINAPackage Cooled:TO-220D/C:08+

D3140

Vendor:NECPackage Cooled:SOPD/C:2007+

Please note: The signals and voltages at the Pins REC, INT, FLA, FLB, Q1A, Q1B, Q2A and Q2B cannot be measured by standard measurement equipment due to very high inter- nal impedances. For the same reason, the PCB should be protected against surface humidity.

D314335MSA

D/C:96

RESET: This is an active high input which clears the Command, Status, Request, and Temporary registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore requests. Following a Reset, the controller is in an idle cycle.

D3146-B

Vendor:THAILANDPackage Cooled:DIPD/C:2005+

NOTES: 1. Dimensions are in inches. 2. Metric equivalents are given for general information only. 3. All terminals are isolated from case. 4. The preferred measurements used herein are the metric units. However, this transistor was designed using inch-pound units of measurement. In case of conflicts between the metric and inch-pound units, the inch-pound units shall be the rule. 5. In accordance...

D31576N7

Vendor:NECPackage Cooled:BGAD/C:08+09+

D3166P5

Package Cooled:SOP8

C 500 ns instruction cycle at 24 MHz operation Superset of the 8051 architecture with 8 datapointers On-chip emulation support logic (Enhanced Hooks Technology TM) 32K byte on-chip ROM (with optional ROM protection) C alternatively up to 64K byte external program memory Up to 64K byte external data memory 256 byte on-chip RAM Additional 2K byte on-chip RAM (XRAM) Seven 8-bit parallel I/O ports Two...

D31A3100

The IS41C4100 and IS41LV4100 is a CMOS DRAM optimized for high-speed bandwidth, low power applica- tions. During READ or WRITE cycles, each bit is uniquely addressed through the 19 address bits. The first ten address bits (A0-A9) are entered as row address and latter nine bits nine address bits (A0-A8) are entered as column address. The row address is latched by the Row Address Strobe (RAS). The colu...

D31A3100L

Vendor:celducPackage Cooled:dipD/C:08+

The UC3823A and UC3823B and the UC3825A and UC3825B family of PWM controllers are improved versions of the standard UC3823 and UC3825 family. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is assured to a tolerance of 5%. Oscillator discharge current is specified at...

D31A7110

Protect Register Disable (PRDS) The PRDS instruction is a ONE TIME ONLY instruction which renders the Protect Register unalterable in the future Therefore the specified registers become PERMANENTLY protected against data changes As in the PRWRITE in- struction the PRE and PE pins must be held high while loading the instruction and after loading the PRDS instruc- tion the PRE and PE pins become dont care...

D31B5100

D31FU

D32.AYWW

Vendor:STPackage Cooled:06+D/C:500

NTSC, PAL and SECAM composite video standards are interlaced video schemes and therefore have odd and even fields. For odd fields, the first broad vertical sync pulse is coincident with the start of horizontal, while for even fields, the first broad vertical sync pulse starts in the middle of a horizontal line.

D-3200

The AP1187 keeps a constant 1.25V between the VSENSE pin and the ADJ pin. By placing a resistor R1 across these two pins and connecting the VSENSE and VOUT pin together, a constant current flows through R1, adding to the IADJ current and into the R2 resistor producing a voltage equal to the (1.25/R1)*R2 + IADJ*R2. This voltage is then added to the 1.25V to set the output voltage. This is summarized in the...

D32050FNL/ECI VDOA-32A

D32051FL

Vendor:TIPackage Cooled:PLCC

Isolation is provided by an optocoupler with regulation done on the secondary side using the TL431 adjustable precision shunt regulator. Small signal compensation with tight voltage regulation is achieved using this part on the secondary side. Many choices exist for the output inductor depending on cost, volume, and mechanicall strength. Several design options are iron powder, molypermalloy (MPP), or a fe...

D32053FNL

Vendor:TIPackage Cooled:PLCC

HPC3130A for Compact PCI Applications Provides Card Detection Mechanism Independent of PCI Present Signals for Advanced Card Protection Provides Path to Guarantee Idle State During PCI Bus Connections Fabricated in Advanced Low-Power CMOS Process Features a CBT Switch† Control Feature for REQ64 Implementation Package Options: C 120-pin QFP Package C 128-pin LQFP Package C 144-pin LQFP Package

D32053FNL/DS301

Vendor:TIPackage Cooled:PLCC68

D32056FN

Vendor:TIPackage Cooled:PLCC

Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Reverse recovery time Reverse recovery charge Emitter-collector voltage

D3207

Vendor:NND/C:07+

• Available on Both Encoder Modules (HEDS-9000 Series) and Encoder Kit Housing (HEDS-5500 Series) • Complementary Outputs • Industry Standard Line Driver IC • Single 5 V Supply • Onboard Bypass Capacitor • 70C and 100C Versions Available

D3207X

Vendor:MOTPackage Cooled:SMD-8

1.56 V@VDD=3.3 V). The design of proper sense circuitry is a matter of scaling the RSENSE and the gain in buffer transistor to meet the logic high as shown in Figure 4. Assuming the VBE(min) of the transistor is approx. 0.5 V. Table 1 lists some recommended RSENSE values according to the nominal operating current.