D10KC20

D10L20U

Vendor:IRPackage Cooled:TOD/C:07+

D10LC20H

Vendor:SHINCLENGENPackage Cooled:2003D/C:2

BENEFITS Needs no more external protection snubber or varistor Enables equipment to meet IEC 61000-4-5 Reduces component count up to 80 % Interfaces directly with the microcontroller Eliminates any gate kick back on the microcontroller Allows straightforward connection of several ACS™ on same cooling pad.

D10LC20UR

Package Cooled:TOD/C:07+

Receive Filter The receive filter consists of three independent sections used for both the removal of quantization noise as well as the reduction of data rate (otherwise known as downsampling). The first section is comprised of a sinc5 filter with a downsampling ratio of 12x. The resulting digital signal is then passed to a droop compensation filter before being sent through the final IIR filter sectio...

D10LC20UR

Package Cooled:TOD/C:07+

Receive Filter The receive filter consists of three independent sections used for both the removal of quantization noise as well as the reduction of data rate (otherwise known as downsampling). The first section is comprised of a sinc5 filter with a downsampling ratio of 12x. The resulting digital signal is then passed to a droop compensation filter before being sent through the final IIR filter sectio...

D10LC40

Package Cooled:TOD/C:07+

will vary with supply voltage, switching frequency and the external MOSFETs used. Note 5: Both CSE+, CSEC and CSF+, CSFC current sense comparators have the same performance specifications. Note 6: The current sense comparator threshold has a 0.33%/C temperature coefficient (TC) to match the TC of the external MOSFET RDSON. Note 7: Guaranteed by design, not subject to test. Note 8: Rise and fall times are m...

D10LC40U

Vendor:PIPackage Cooled:08+D/C:1200

The LTC®6101/LTC6101HV are versatile, high voltage, high side current sense amplifiers. Design flexibility is provided by the excellent device characteristics; 300µV Max offset and only 375µA (typical at 60V) of current consumption. The LTC6101 operates on supplies from 4V to 60V and LTC6101HV operates on supplies from 5V to 100V.

D10LC4D

Vendor:新电源Package Cooled:07+

D10LCA20

Vendor:87D/C:N/A

Drain-to-Source Breakdown Voltage 200 Gate Threshold Voltage …2.04.0 Gate-to-Source Leakage Forward100 Gate-to-Source Leakage Reverse-100 Zero Gate Voltage Drain Current25 Static Drain-to-Source … 0.100 On-State Resistance One Diode Forward Voltage …1.4

D10LCA20

Vendor:87D/C:N/A

Drain-to-Source Breakdown Voltage 200 Gate Threshold Voltage …2.04.0 Gate-to-Source Leakage Forward100 Gate-to-Source Leakage Reverse-100 Zero Gate Voltage Drain Current25 Static Drain-to-Source … 0.100 On-State Resistance One Diode Forward Voltage …1.4

D10N400C

D10NF06L

Vendor:STPackage Cooled:TO-252D/C:1

The RF5189 is a linear, medium-power, high-efficiency amplifier IC designed specifically for battery-powered WLAN applications such as PC cards, mini PCI, and compact flash applications. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in 2.5GHz WLAN and other spread-spectrum transmitter...

D10NF10

Vendor:STPackage Cooled:TO-252D/C:1

Address Latch-Enable Output. This pin functions as a clock to latch the external address LSB from the multiplexed address/data bus. This signal is commonly connected to the latch enable of an external 373 family transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high when the device is in a reset condition.

D10NF10

Vendor:STPackage Cooled:TO-252D/C:1

Address Latch-Enable Output. This pin functions as a clock to latch the external address LSB from the multiplexed address/data bus. This signal is commonly connected to the latch enable of an external 373 family transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high when the device is in a reset condition.

D10P03L

Vendor:HARRISPackage Cooled:07+D/C:TO-251

The UCC3952 monolithic BiCMOS lithiumCion battery protection circuit increases the useful operating life of a one-cell rechargeable battery pack. Cell protection features include internally trimmed charge and discharge voltage limits, discharge current limit with a delayed shutdown, and an ultra-low-current sleep mode state when the cell is discharged. Additional features include an on-chip MOSFET ...

D10PF06

Vendor:STPackage Cooled:N/AD/C:0

BVDSSDrain-to-Source Breakdown Voltage-100 ∆BV DSS/∆T J Temperature Coefficient of Breakdown Voltage RDS(on)Static Drain-to-Source On-State Resistance VGS(th)Gate Threshold Voltage-2.0 gfsForward Transconductance2.5 IDSSZero Gate Voltage Drain Current

D10PF06

Vendor:STPackage Cooled:N/AD/C:0

BVDSSDrain-to-Source Breakdown Voltage-100 ∆BV DSS/∆T J Temperature Coefficient of Breakdown Voltage RDS(on)Static Drain-to-Source On-State Resistance VGS(th)Gate Threshold Voltage-2.0 gfsForward Transconductance2.5 IDSSZero Gate Voltage Drain Current

D10S30

D10SB10

Vendor:SHINDENGENPackage Cooled:DIP4D/C:02+

It contains a Single-Ended (SE) power stage, drive logic, protection control logic, a full differential input comparator and a HVP charger to charge the SE capacitor. With this amplifier a compact 1 20 W closed loop self-oscillating digital amplifier system can be built. The TDA8931 has a high efficiency so that a heat sink is not required up to 20 W (RMS). The system operates on an asy...

D10SB20

Vendor:SHINDENGENPackage Cooled:DIP4D/C:02+

Note Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifica- tion isnot implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

D10SB20

Vendor:SHINDENGENPackage Cooled:DIP4D/C:02+

Note Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifica- tion isnot implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

D10SB40

Vendor:SHINDENGENPackage Cooled:DIP4D/C:02+

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

D10SB40

Vendor:SHINDENGENPackage Cooled:DIP4D/C:02+

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

D10SB60

Vendor:SHINDENGENPackage Cooled:DIP4D/C:02+

4.4.4 Group E inspection. Group E inspection shall be conducted in accordance with the conditions specified for subgroup testing in table IX of MIL-PRF-19500. Electrical measurements (end-points) shall be in accordance with table I, group A, subgroup 2 herein.

D10SB80

Vendor:SHINDENGENPackage Cooled:DIP4D/C:02+

Since the ADR512 characteristics resemble those of a Zener diode, the cathode shown in Figure 5 will be 1.2 V higher with respect to the anode (V+ with respect to VC on the ADR512 package). Since the cathode of the ADR512 is tied to ground, the anode must be C1.2 V.

D10SC3M

The HYM72V32M636T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The HYM72V32M636T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

D10SC4M

Package Cooled:TOD/C:07+

A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor. This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI that will run on a Windows PC.

D10SC6MR

Package Cooled:TOD/C:07+

Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse Provides automatic entry into Holdover and return from Holdover Manual and automatic hitless reference switching Provides lock, holdover and accurate reference fail indication

D10SC6MR

Package Cooled:TOD/C:07+

Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse Provides automatic entry into Holdover and return from Holdover Manual and automatic hitless reference switching Provides lock, holdover and accurate reference fail indication

D10SC9MR

D10SD6M

Package Cooled:TOD/C:07+

Members of the Texas Instruments Widebus™ Family State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs...

D10U20S

Vendor:SECPackage Cooled:TO-220FD/C:00+

We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all cla...

D10U20S

Vendor:SECPackage Cooled:TO-220FD/C:00+

We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all cla...

D10VB20

Vendor:SHINDENGENPackage Cooled:DIP4D/C:02+

‡ Unless otherwise noted, voltages are reference to ground and currents are positive into and negative out of the specified terminals. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500 µs. Consult the Packaging Section of the Portable Products Data Book (TI Literature No. SLUD001) for thermal limitations and considerations of the package.

D10VB60

Vendor:SHINDENGENPackage Cooled:DIP4D/C:02+

The VHCT374A consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are com- mon to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transi- tion. With the Output Enable (OE) LOW, the contents of the...

D10VB60

Vendor:SHINDENGENPackage Cooled:DIP4D/C:02+

The VHCT374A consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are com- mon to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transi- tion. With the Output Enable (OE) LOW, the contents of the...

D10VD60Z

The EP7311 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 VC3.3 V allowing the device to achieve a performance level equivalent to 60 MIPS. The device has three basic power states:

D10VD60Z

The EP7311 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 VC3.3 V allowing the device to achieve a performance level equivalent to 60 MIPS. The device has three basic power states:

D10XB100H

Vendor:GULFPackage Cooled:GBLD/C:2007

D10XB20

Package Cooled:ZIP-4D/C:02+

The D10XB20 uses advanced trench technology to provide excellent RDS(ON), low gate charge and operation with gate voltages as low as 1.8V while retaining a 12V VGS(MAX) rating. This device is suitable for use as a uni-directional or bi-directional load switch, facilitated by its common-drain configuration.

D10XB60H

Package Cooled:TOD/C:07+

The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration pro- gram from an external memory. The Xilinx PROMs have been...

D10XB80

D10XX

Vendor:CHMCPackage Cooled:DIPD/C:07+

D11 24R9 FCS

Vendor:ＶＩＳＨＡＹ

D11..

Vendor:SOP-5PD/C:03+

The MQ photoelectric sensor area reflective type has adapted this optical triangulation range measurement prin- ciple, but in order to improve the relia- bility of the detection of the sensor, a more elaborate method has been devised. First, light receivers are posi- tioned symmetrically on either side of the axis of the light projector, compos- ing a triple beam arrangement. As shown in Fig. 2...

D11/CRCW06030R0P5E3

Vendor:ＶＩＳＨＡＹ

D11/CRCW0603100120R1ET1E3

Vendor:ＶＩＳＨＡＹ

D11/CRCW060310031K61ET1E3

Vendor:ＶＩＳＨＡＹ

D11/CRCW060310047R1P5E3

Vendor:ＶＩＳＨＡＹ

D11/CRCW06031004K701ET1E3

Vendor:ＶＩＳＨＡＹ

D11/CRCW0603205RFKTA

Vendor:ＶＩＳＨＡＹ

D11/CRCW06032K0F100P5

Vendor:ＶＩＳＨＡＹ

D11/CRCW06032K15F100P5

Vendor:ＶＩＳＨＡＹ

D11/CRCW06032K15FKEA

Vendor:ＶＩＳＨＡＹ

D11/CRCW06032K15FKTA

Vendor:ＶＩＳＨＡＹ

D11/CRCW06033K32FKTA

Vendor:ＶＩＳＨＡＹ

D11/CRCW0603619RF100P5

Vendor:ＶＩＳＨＡＹ

D110-00

D11010N

Vendor:TIPackage Cooled:DIP塑封中片D/C:98

This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT ...

D11010N

Vendor:TIPackage Cooled:DIP塑封中片D/C:98

This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT ...

D11014FN

Vendor:xrPackage Cooled:PLCC

The 64K bytes of flash EEPROM program memory are used to store the application program. It has security features to prevent unintentional programming and to prevent unautho- rized access to the program code. This memory can be pro- grammed with a device external programming unit or with the device installed in the application system (in-system pro- gramming).

D11014FN

Vendor:xrPackage Cooled:PLCC

The 64K bytes of flash EEPROM program memory are used to store the application program. It has security features to prevent unintentional programming and to prevent unautho- rized access to the program code. This memory can be pro- grammed with a device external programming unit or with the device installed in the application system (in-system pro- gramming).

D11046

D110551-0000

D11100221R

D1111

Vendor:三洋D/C:TO-92

attributes through memory-mapped control registers (MMRs) an extension not found on the i960 Kx, Sx or Cx processors. Physical and logical configu- ration registers enable the processor to operate with all combinations of bus width and data object alignment. The processor supports a homogeneous byte ordering model.

D1111D

D1115

D111649R

D111A448

D1120

Vendor:SONYPackage Cooled:DIPD/C:96+

DESCRIPTION The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low,...

D1120010KJJ2

D1120022R5P5

The input/output pins (I/O 1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).

D112002K75PS

D11200510R5P5

D1120-A1

Vendor:SIEMENSPackage Cooled:PLCC44

D1120-A1

Vendor:SIEMENSPackage Cooled:PLCC44

D1128MX4D85TF75-SSE

D1131SH

Vendor:in stockPackage Cooled:EupecD/C:08+

D1133

Codec negative analog output. The DC level is Vcm, and the full-scale ac output is 2.8V p-p5%. The maximum loading is 1k Ω in parallel with 20 pF for modem applications. For audio applications with low-impedance load, the maximum distortion-free (THD <C60 db) current is 10 mA rms.

D1134

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable fail...

D1135

Vendor:FAIRCHILDPackage Cooled:TO-220D/C:05+

D1140B

Vendor:SONYPackage Cooled:SMD-20D/C:00+

Notes: 1.Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2.Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed. 3.The package thermal impedance is calculated in accordance with JESD 51.

D1-14510-9

D1146

Vendor:KECD/C:排带

Notes 1. Derate linearly from 25C at a rate of 2.42 mW/ C 2. Derate linearly from 25C at a rate of 1.42 mW/ C. 3. Derate linearly from 25C at a rate of 2.42 mW/ C. 4. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside these ratings.

D1-1488-5

Vendor:HARRISPackage Cooled:DIP陶瓷条子14脚D/C:73

D1149R

Vendor:QFP-48Package Cooled:SONYD/C:2004+

2-channel, 256-position End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Compact MSOP-10 (3 mm 4.9 mm) package Fast settling time: tS = 5 µs typical on power-up Full read/write of wiper register Power-on preset to midscale Extra package address decode pin AD0 Computer software replaces µC in factory programming applications Single supply: 2.7 V to 5.5 V Low te...

D11501FNR

Vendor:TI

D11508PN

Vendor:TIPackage Cooled:TQFPD/C:92

Hynix HYMD212G726(L)S4M-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

D1151M5

D11522K

D1153002

Vendor:SUNPackage Cooled:PGA

D1-15501B-8

D1-15530-2

Package Cooled:DIP

D1-15530-8

Vendor:HARRISPackage Cooled:DIP

(8-2) Input Timing Digital audio signal data into DIN terminal is fetched into the internal shift register by BCK signal rising edge. The fetched data in the shift register are transferred by rising edge or falling edge of LRCK as shown below:

D1-15530-9

Package Cooled:DIP

Notes. The SM5009 series reduce crystal current by limiting driving current of oscillating-stage inverter and inhibiting oscillating amplitude. Depending on the characteristics of using crystal or the mounting condition, they may not oscillate normally. Please evaluate the oscillation start-up characteris- tics adequately with your actual device.

D1-15531-9

Vendor:HARPackage Cooled:50D/C:N/A

After the 5 minute incubation, combine the diluted DNA with the diluted Lipofectamine™ 2000 (total volume is 100 µl). Mix gently and incubate for 20 minutes at room temperature to allow the DNA-Lipofectamine™ 2000 complexes to form. The solution may appear cloudy, but this will not inhibit the transfection. Note: DNA- Lipofectamine™ 2000 complexes are stable for 6 hours at room temper...

D1-15531-9

Vendor:HARPackage Cooled:50D/C:N/A

After the 5 minute incubation, combine the diluted DNA with the diluted Lipofectamine™ 2000 (total volume is 100 µl). Mix gently and incubate for 20 minutes at room temperature to allow the DNA-Lipofectamine™ 2000 complexes to form. The solution may appear cloudy, but this will not inhibit the transfection. Note: DNA- Lipofectamine™ 2000 complexes are stable for 6 hours at room temper...

D1156R

Vendor:SONYPackage Cooled:TQFPD/C:1994

The submount product may show the change of the optical and electrical characteristics due to the influences of an assembly substrate (strain, thermal conductivity, etc.) prepared by the customer. Therefore, the supplier is not obliged to guarantee that all optical and electrical characteristics meet specifications after the shipment.

D1156R

Vendor:SONYPackage Cooled:TQFPD/C:1994

The submount product may show the change of the optical and electrical characteristics due to the influences of an assembly substrate (strain, thermal conductivity, etc.) prepared by the customer. Therefore, the supplier is not obliged to guarantee that all optical and electrical characteristics meet specifications after the shipment.