ESB2E A1

Vendor:INTELPackage Cooled:BGAD/C:0551+

ESB30.0000F20D35

Vendor:HOSONICD/C:N/A

HIGH SPEED : tPD = 21 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4017

ESB30.0000F20D35

Vendor:HOSONICD/C:N/A

HIGH SPEED : tPD = 21 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4017

ESB30A105

ESB30A132

Vendor:PANASOINCD/C:07/08+

ESB30A332

Vendor:PANASOINCD/C:07/08+

ESB30B106

ESB30B132

Vendor:PANASOINCD/C:07/08+

ESB30B133

ESB30B301

Vendor:PANASOINCD/C:07/08+

ESB30B305

ESB30B333

ESB32

Vendor:PANASOINCD/C:07/08+

ESB32134

Vendor:PANASOINCD/C:07/08+

ESB32153

Vendor:PANASOINCD/C:07/08+

ESB32232

Vendor:PANASOINCD/C:07/08+

ESB32234

Vendor:PANASOINCD/C:07/08+

ESB32252

Vendor:PANASOINCD/C:07/08+

ESB32352

ESB32433

Vendor:PANASOINCD/C:07/08+

ESB32452

Vendor:PANASOINCD/C:07/08+

ESB32453

Vendor:PANASOINCD/C:07/08+

ESB33

Vendor:PANASOINCD/C:07/08+

ESB33133

Vendor:PANASOINCD/C:07/08+

The DS1804 can be easily used as an OTP device. The user of the DS1804 can trim the desired value of the wiper position and set this position for storage as described above. Any activity through the three- terminal port can then be prevented by connecting the CS input pin to VCC. Also, an OTP application does not adversely affect the number of times EEPROM is written, since EEPROM will only be loaded and not...

ESB641

Vendor:PANASOINCD/C:07/08+

ESB64500

ESB64600

Vendor:PANASOINCD/C:07/08+

ESB68000

ESB68400

ESB92D11B

Vendor:PANASOINCD/C:07/08+

ESB92D17B

Vendor:PANASOINCD/C:07/08+

ESB92S

Vendor:PANASOINCD/C:07/08+

ESB92S17B

Vendor:PANASOINCD/C:07/08+

ESB92S94B

Vendor:PANASOINCD/C:07/08+

ESC17661MAA

D/C:00

The LH28F016SU is a very high density, highest per- formance non-volatile read/write solution for solid-state storage applications. Its symmetrically blocked archi- tecture (100% compatible with the LH28F008SA 8M Flash memory), extended cycling, low power 3.3 V operation, very fast write and read performance and selective block locking provide a highly flexible memory component suitable for high den...

ESC2088026-13

Vendor:HARRISPackage Cooled:SMDD/C:08+

These N-Channel power MOSFETs are manufactured using the innovative UltraFET® process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in a...

ESC2088026-13

Vendor:HARRISPackage Cooled:SMDD/C:08+

These N-Channel power MOSFETs are manufactured using the innovative UltraFET® process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in a...

ESC208826-13

Vendor:HARPackage Cooled:98+D/C:SOP-7.2-28P

ESC231H1800C

D/C:07+

Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the ESC231H1800C/5903 (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The ZBTTM has a one cycle deselect, i.e., the data b us will tri-state one clock cycle after deselect is initiated.

ESC231H1800C

D/C:07+

Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the ESC231H1800C/5903 (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The ZBTTM has a one cycle deselect, i.e., the data b us will tri-state one clock cycle after deselect is initiated.

ESC6121-001

Package Cooled:SOPD/C:07+

• Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and AGP memory • One selectable frequency for VCH video channel clock (48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V) • Power management using power-down, CPU stop, and PCI stop pins • Three function select pins (include test-mode select) • Cypress Spread Spectrum for best electromagnetic interference (EMI) reduction • S...

ESC614

Given: V+ = 28V, MSK 4362 +15V IQ = 85mA, -15V IQ = 40mA. External Loads: +15V = 25 mA, -15V = 25 mA -15V Converter Efficiency = 50% PDISS due to +15V IQ,85 mA x 13V = 1.11 W PDISS due to -15V IQ, (40 mA / 0.5) x 13V = 1.04 W PDISS due to +15V Ext load, 25 mA x 13V = 325 mW PDISS due to -15V Ext load, (25 mA / 0.5) x 13V = 650 mW PDISS Total = 1.11 W + 1.04 W + 325 mW+650 mW=3.13W 3.13 W x 9C/W = 28...

ESC614-1ATS

Package Cooled:05+D/C:QFP

ESC614-2

ESC614A

ESC614X-15

Vendor:ADPackage Cooled:QFP2828-160D/C:95+

The EB-2100x accommodates either a coaxial or an optical S/PDIF digital audio interface. Either input may be selected by moving jumper J2. Connect J2 pins 1-2 for coaxial or J2 pins 2- 3 for optical S/PDIF. A Crystal CS8415A digital audio interface receiver is utilized to convert the incoming S/PDIF signal to serial I2S used by the DDX-2000. The receiver also recovers a 256*Fs clock synchronized to the inco...

ESC615-1

ESC615X-4

The DS1669 is offered in two standard IC packages which include an 8Cpin 300 mil DIP and an 8Cpin 200 mil SOIC. Like the DS1668, the DS1669 can be configured to operate using a single pushbutton or digital source input. This is illustrated in Figure 1. Additionally, the DS1669 can be configured to operate in a dual pushbut- ton configuration which is shown in Figure 2. The DS1669 pinouts allow access...

ESC772TO-126

Vendor:NECD/C:07+

ESCANP8ENREVB

ESCD221

Vendor:31Package Cooled:EQUIPEMENTSD/C:N/A

The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has been expanded to support the ISO/IEC7816-3 ...

ESCD229

Vendor:48Package Cooled:EQUIPEMENTSD/C:N/A

Converted to nat2000 DTDCORRECTED TYPOSadded text on IN (5V and clock) (JFG)CORRECTED PIN TABLES LAYOUT (JFG)addded a new page pi in between the rows in the tableremoved new page pi before the table as it created a blank pageformat clean up (JFG)format edits (JFG)Move note12(clock failsafe) to App Info.Delete 75Mhz spec by Peter KuoADD 50PS TO RSSOP BY PETER KUOAC&DC BY PETER KUO 3/19/1999288A AC by Peter ...

ESCD229S3

Vendor:8Package Cooled:EQUIPEMENTSD/C:N/A

A separate option converts the 16 x 2 RAM in any CLB into a 16 x 1 dual-port RAM. In this mode, any operation that writes into the F-RAM, automatically also writes into the G- RAM, using the F address. The G-address can, therefore, not be used to write into the G-RAM.

ES-CF43212PC

Vendor:FUJPackage Cooled:QFP

The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given moment. When a STA111 is selected with all of its LSPs parked, the active scan chain is the current scan register only. When a LSP is unparked, the active scan chain becomes: TDIB the current STA111 register the local scan ring registers a PAD bit TDOB. Refer to Table 7 for Unparked configurations of...

ES-COLOR/CONNECTIX

Vendor:MICROCHIPPackage Cooled:PLCC44D/C:97+

S/PDIF Compatible Digital Audio receiver/transmitter sup- ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards Left-justified, I2S or right-justified serial data input with 16, 18, 20 or 24-bit word widths (transmitter) Two channel mode and Single Channel Double Frequency (SCDF) mode Digital Transmission Content Protection (DTCP)a crypto- graphic protocol for protecting audio content from un...

ESCT2

D/C:02

Since power dissipation inside a microprocessor is proportional to the square of the core voltage, Intel XScale processors implement DVM as a means to more efficiently utilize battery capacity. To support this power saving architecture, the ISL6271A integrates an I2C bus for communication with the host processor. The processor, acting as the bus master, transmits a voltage level and voltage slew rate to the ...

ESCT2

D/C:02

Since power dissipation inside a microprocessor is proportional to the square of the core voltage, Intel XScale processors implement DVM as a means to more efficiently utilize battery capacity. To support this power saving architecture, the ISL6271A integrates an I2C bus for communication with the host processor. The processor, acting as the bus master, transmits a voltage level and voltage slew rate to the ...

ESD003

Vendor:CMDPackage Cooled:SOP-20

Supply-voltage range: The operating range in normal operation is between 4 and 40 V. If pin VREF is connected to VS, the circuit is operating between 3.1 and 4.5 V. In this case, however, VREF is no longer internally stabilized, i.e. the analog IC functions depend on the operating voltage.

ESD-03

Package Cooled:08+D/C:800

The memory controller supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM. Up to three parallel accesses to the internal RAM and ROM from three of the following four sources are supported: • Two 64-bit data accesses from the C67x+ CPU • One 256-bit program fetch from the core and program cache • One 32-bit data access from the peripheral system (either dMAX or UHPI)

ESD03A04-TE16L

D/C:07+

DESCRIPTION Input. Decoded by LAN91C100FD to determine access to its registers. Input. Used by LAN91C100FD for internal register selection. Input. Used as an address qualifier. Address decoding is only enabled when AEN is low. Input.Used during LAN91C100FD register accesses to determine the width of the access and the register(s) being accessed. nBE0-nBE3 are ignored when nDATACS is low (burst accesses)...

ESD03A04-TE16L

D/C:07+

DESCRIPTION Input. Decoded by LAN91C100FD to determine access to its registers. Input. Used by LAN91C100FD for internal register selection. Input. Used as an address qualifier. Address decoding is only enabled when AEN is low. Input.Used during LAN91C100FD register accesses to determine the width of the access and the register(s) being accessed. nBE0-nBE3 are ignored when nDATACS is low (burst accesses)...

ESD0505-M0500091

Vendor:EPCOS ?Package Cooled:2006?D/C:4200

Built-in watch dog timer Low current consumption130µA TYP. Low operating threshold voltageVCC=0.8V Watch dog stop function (RCT terminal) Long clock monitoring time TPR (POWER ON) : TWD (clock monitoring)=1 : 1 6. Fewer outer components

ESD0505-M0500091

Vendor:EPCOS ?Package Cooled:2006?D/C:4200

Built-in watch dog timer Low current consumption130µA TYP. Low operating threshold voltageVCC=0.8V Watch dog stop function (RCT terminal) Long clock monitoring time TPR (POWER ON) : TWD (clock monitoring)=1 : 1 6. Fewer outer components

ESD0P8RFLE6327

Vendor:InfineonD/C:600

ESD103E

ESD104E

The LM78LXX is available in the plastic TO-92 (Z) package, the plastic SO-8 (M) package and a chip sized package (8-Bump micro SMD) using Nationals micro SMD package technology. With adequate heat sinking the regulator can deliver 100mA output current. Current limiting is included to limit the peak output current to a safe value. Safe area protection for the output transistors is provided to limit inter-

ESD104LD06

ESD11H120

Vendor:PANSONICD/C:.

ESD11H121

Vendor:PANASOINCD/C:07/08+

ESD11H230

Vendor:PANASOINCD/C:07/08+

The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the internal peripherals and the four external interrupt lines (including the FIQ), to provide an interrupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and, using the Auto-vectoring feature, reduces the interrupt latency time.

ESD11H231

Vendor:PANASOINCD/C:07/08+

ESD11V121

Vendor:PANASOINCD/C:07/08+

ESD11V130

Vendor:PANASOINCD/C:07/08+

FEATURES lOptions :- 10mm lead spread - add G after part no. Surface mount - add SM after part no. Tape&reel - add SMT&R after part no. lHigh Isolation Voltage (5.3kVRMS ,7.5kVPK ) lHigh Surge Anode Current (5.0 A) lHigh Blocking Voltage (200V*1, 400V*1) lLow Turn on Current (5mA typical) lAll electrical parameters 100% tested lCustom electrical selections available

ESD11V230

Vendor:PANASOINCD/C:07/08+

ESD1330FBA

Vendor:EPSONPackage Cooled:07+D/C:QFP

ESD1330FBA

Vendor:EPSONPackage Cooled:07+D/C:QFP

ESD1351FOA

Vendor:EPSONPackage Cooled:07+D/C:QFP

ESD1351FOA

Vendor:EPSONPackage Cooled:07+D/C:QFP

ESD16

Vendor:PANASOINCD/C:07/08+

ESD165206

Vendor:PANASOINCD/C:07/08+

MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two programmable flag default settings, and serial or parallel programming of the offset settings.

ESD165208

Vendor:PANASONICD/C:07/08+

ESD165227

Vendor:PANASOINCD/C:07/08+

ESD165256

Vendor:PANASOINCD/C:07/08+

ESD165278

Vendor:PANASOINCD/C:07/08+

ESD165288

Vendor:PANASOINCD/C:07/08+

ESD17

Vendor:PANASOINCD/C:07/08+

ESD170201

Vendor:PANASOINCD/C:07/08+

ESD170206

Vendor:PANASOINCD/C:07/08+

ESD170302

Vendor:PANASOINCD/C:07/08+

ESD172302

Vendor:PANASOINCD/C:07/08+

ESD172306

Vendor:PANASOINCD/C:07/08+

ESD175201

Vendor:PANASOINCD/C:07/08+

ESD177201

Vendor:PANASOINCD/C:07/08+

ESD177202

Vendor:PANASOINCD/C:07/08+

ESD177302

Vendor:PANASOINCD/C:07/08+

ESD5B5.0ST1G

Vendor:ONSD/C:08+

To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices. This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger supports this family. Numerous third-party developers not only offer device-level devel...

ESD5B5.0ST1G

Vendor:ONSD/C:08+

To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices. This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger supports this family. Numerous third-party developers not only offer device-level devel...

ESD5V0S5USE6327

ESD5Z12T1G

Vendor:ON

2. Handling In order to avoid damage to beam lead devices, particular care must be exercised during inspection, testing, and assembly. Although the beam lead diode is designed to have exceptional lead strength, its small size and delicate nature requires that special handling techniques be observed so that the devices will not be mechani- cally or electrically damaged. A vacuum pickup is recommended fo...

ESD5Z2.5T1G

Vendor:ON

Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 • ICS clock will acknowledge each byte one at a time. • Contro...