Index "F"Vendor:cmacPackage Cooled:cmacD/C:dc04
During steady-state operation for a typical switching cycle, the oscillator sets the driver logic and turns on N1 power device. N1 conducts current through the inductor and re- verse biases the external diode. The LED current is supplied by the output capacitor when N1 is conducting. Once N1 on-time period is concluded, the internal power device is turned off and the external diode is forward baised. T...
Vendor:11Package Cooled:POLYFETD/C:N/A
Vendor:POLYFETPackage Cooled:N/AD/C:08+
Vendor:580
The Versatile Timer Unit (VTU) module contains four inde- pendent timer subsystems, each operating in either dual 8- bit PWM configuration, as a single 16-bit PWM timer, or a 16-bit counter with two input capture channels. Each of the four timer subsystems offer an 8-bit clock prescaler to ac- commodate a wide range of frequencies.
Vendor:N/APackage Cooled:DIPD/C:07+
5. Output clip detection function (pin(1)) The output clip detection terminal of pin(1) has the open collector output structure on chip as shown in Fig.5. In case that the output waveform is clipping, the clip detection circuit is operated and NPN Tr. is turned on. It is possible to improve the tone quality with the current of flowing into pin(1) and with controlling the volume, tone control circuit thro...
Vendor:STPackage Cooled:TO-39D/C:99
Supply voltage Shutdown current MOSFET on resistance Short-circuit current limit Input logic low Input logic high Average Output current FG input Positive-going threshold voltage FG input Negative-going threshold voltage FG input Hysteresis voltage
Vendor:POLYFETPackage Cooled:N/AD/C:08+
The Flash memory on the F2012 offers In-Application Programming (IAP) functionality. The IAP routines are part of the on-chip boot loader software, which controls the interface between the digital logic and the Flash memory. Please note that all programming methods (JTAG, ISP, IAP) use IAP calls.
Vendor:POLYFETPackage Cooled:(LX)high-frequency
Theseversatile devices are usefulfor driving a wide range of loads including solenoids, relays DC mo- tors, LED displays filament lamps, thermal print- heads and high power buffers. The ULN2001A/2002A/2003Aand 2004A are sup- plied in 16 pin plastic DIP packages with a copper leadframe to reduce thermal resistance. They are available also in small outline package (SO-16) as ULN2001D/2002D/2003D/2004D.
Vendor:RENESASPackage Cooled:08+D/C:800
The power switch has full over-current protection. Whenever the current limit of the switch is exceeded, the device enters a constant-current mode, where the output voltage is progressively reduced to prevent the current from increasing further. The OC# output becomes active low only if the overcurrent condition exceeds at least 10ms. This fault blanking delay prevents false alarms from being reported to th...
Vendor:POLYFETPackage Cooled:(LX)high-frequency
Memory D Up To 32kB Flash Memory D Flash Memory Partitioning D Endurance 1M Erase/Write Cycles, 100 Year Data Retention D In-System Serially Programmable D External Program/Data Memory (64kB) D 1,280 Bytes Data SRAM D Flash Memory Security D 2kB Boot ROM D Programmable Wait State Control
Vendor:SEMITECPackage Cooled:LL34D/C:08+
A fixed 1.4MHz operating frequency ensures operation outside the DSL frequency band, provides fast transient response, and allows the use of small external compo- nents. Only 4.7µF input and output ceramic capacitors are needed for 1A applications. Forced PWM operation ensures a constant switching frequency over all load conditions. Output voltage accuracy is 1% over load, line, and temperature operat...
Vendor:SEMITECPackage Cooled:LL34D/C:08+
A fixed 1.4MHz operating frequency ensures operation outside the DSL frequency band, provides fast transient response, and allows the use of small external compo- nents. Only 4.7µF input and output ceramic capacitors are needed for 1A applications. Forced PWM operation ensures a constant switching frequency over all load conditions. Output voltage accuracy is 1% over load, line, and temperature operat...
"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiar- ies ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). ...
Vendor:MOSPECPackage Cooled:TO-220D/C:02+
After the input data remains zero for 2500 or 12 500 cycles of Fs as set by the system register (D4, D5), the channel-mute flag becomes active. Zero-data detection is available for both channels independently, so the two outputs (MUTER and MUTEL) indicate that zero data has been detected on the respective channel. The zero-detect register value in the serial-control data selects the detection period. The ...
Vendor:MOSPECPackage Cooled:TO-220D/C:02+
The HYM72V12C736B(L)S4 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 1Gbytes memory. The HYM72V12C736B(L)S4 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and out- puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
Vendor:MOSPECPackage Cooled:TO-220D/C:02+
The HYM72V12C736B(L)S4 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 1Gbytes memory. The HYM72V12C736B(L)S4 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and out- puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
Vendor:MOSPECPackage Cooled:TO-220D/C:05+
SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
Vendor:MOSPECPackage Cooled:TO-220D/C:02+
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available ADC smart power management Each peripheral can be individually disabled to save power
Vendor:MOSPECPackage Cooled:TO-220D/C:05+
Thermal Design The IRU1261 incorporates an internal thermal shutdown that protects the device when the junction temperature exceeds the maximum allowable junction temperature. Although this device can operate with junction tempera- tures in the range of 1508C, it is recommended that the selected heat sink be chosen such that during maxi-
Vendor:TOSPackage Cooled:08+D/C:2000
A dedicated control input (EN, Active High) has been included for power-up sequencing flexibility. When this input is taken low, the regulator is disabled. In this state, the supply current will drop to near zero. An inter- nal discharge MOSFET resistance (500Ω) will force the output to ground whenever the device has been shut- down.
Package Cooled:08+D/C:2000
All outputs skew <100 ps typical (250 max.) 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines Low operating current 24-pin SOIC package Jitter: <200 ps peak to peak, <25 ps RMS Compatible with Pentium™-based processors
Vendor:NEWPOWERPackage Cooled:06+D/C:TO-220
The Am79C988A Quad Integrated Ethernet Transceiver (QuIET) device consists of four independent 10BASE-T transceivers which are compliant with the IEEE 802.3 Section 14 (Medium Attachment Unit for 10BASE-T Cabling) standard. When combined with AMD's Integrated Multiport Repeater 2 (IMR2™) chip, the QuIET device provides a system-level solution to designing a managed 10BASE-T repeater.
Package Cooled:3P
Interrupt flags with programmable masking Dual Chip Enables allow for depth expansion without external logic UB and LB are available for x8 or x16 bus matching TTL-compatible, single 5V (10%) power supply Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)
576 x 16-bit high-performance CMOS Dynamic Random Access Memories. These devices offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the 16100 series ideal for use in 16-, 32-bit wide data bus systems.
D/C:00+
Vendor:LTPackage Cooled:SMD
Vendor:LTPackage Cooled:TSSOP-20PD/C:O145
In applications using one DAC per channel, where the track- and-hold feature of the 5B39 is not used, the Write Enable input should be set to low by grounding it to power common, as on the 5B01 and 5B08 backplanes. The module current output will then track its input signal.
Vendor:FSCPackage Cooled:TO-220
FO transceivers The widely used Time Division Multiplex (TDM) transmission technique now enables bit rates up to 10Gbps and is well established in modern transport systems. Today's high-speed fiber optic transmission systems offer the following standard bit rates:
Vendor:FSCPackage Cooled:TO-220
FO transceivers The widely used Time Division Multiplex (TDM) transmission technique now enables bit rates up to 10Gbps and is well established in modern transport systems. Today's high-speed fiber optic transmission systems offer the following standard bit rates:
Vendor:fscPackage Cooled:fscD/C:dc84
The REFCLK input can be configured three ways. When both REFCLK+ and REFCLK- are connected to a differential 100K-compatible PECL source, the REFCLK input will behave as a differential PECL input. When either the REFCLK- or the REFCLK+ input is at a TTL LOW, the other REFCLK input becomes a TTL-level input allowing it to be connected to a low-cost TTL crystal oscillator. The REFCLK input structure, th...
Vendor:fscPackage Cooled:fscD/C:dc84
The REFCLK input can be configured three ways. When both REFCLK+ and REFCLK- are connected to a differential 100K-compatible PECL source, the REFCLK input will behave as a differential PECL input. When either the REFCLK- or the REFCLK+ input is at a TTL LOW, the other REFCLK input becomes a TTL-level input allowing it to be connected to a low-cost TTL crystal oscillator. The REFCLK input structure, th...
Vendor:FPackage Cooled:06+D/C:800
Package Cooled:06+D/C:800
Ruotare il selettore su OC . Quando lalimentazione a ON e si applica il segnale di start tra i ter- minali A1 e B1, inizia il conteggio e luscita va a ON per circa 0.8 sec. dopo che trascorso il tempo impostato. Luscita torna allo stato iniziale a fine conteggio o se viene tolta lalimentazione.
Vendor:RENESASPackage Cooled:BGAD/C:07+
The APL5523 is a dual low dropout regulator with output1 with 3.3V/0.5A and output2 with 1.8V/0.3A output capability. In order to obtain lower dropout voltage and faster transient response, which is criti- cal for low voltage applications, the APL5223 has been optimized. The dropout voltages are guaran- teed at 0.6V at 0.5A for output1 and 0.9V at 0.3A for output 2. Current limit is trimmed to ensure speci- ...
Vendor:HITPackage Cooled:2040D/C:05+
(Continued) Instruction system best suited to controller • Wide choice of data types (bit, byte, word, and long word) • Wide choice of addressing modes (23 types) • Enhanced multiply-divide instructions and RETI instructions • Enhanced high-precision computing with 32-bit accumulator Instruction system compatible with high-level language (C language) and multita...
Vendor:HDPackage Cooled:(SX)computer ICD/C:05+
tpZL15nsEnable time, high-impedance-to-low-level output (1) All typical values are at 25C and with a 3.3-V supply voltage. (2) HP4194A impedance analyzer (or equivalent) (3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. (4) VID = 200 mVpp (LVD201, 203), VID = 400 mVpp (LVD206, 207), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k samp...
Vendor:HDPackage Cooled:(SX)computer ICD/C:05+
tpZL15nsEnable time, high-impedance-to-low-level output (1) All typical values are at 25C and with a 3.3-V supply voltage. (2) HP4194A impedance analyzer (or equivalent) (3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. (4) VID = 200 mVpp (LVD201, 203), VID = 400 mVpp (LVD206, 207), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k samp...
D/C:08+/09+
technology. It is ideal for low power and low noise 3.3V applications. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
D/C:08+/09+
technology. It is ideal for low power and low noise 3.3V applications. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
Vendor:03+Package Cooled:TQFP144D/C:04+
The ST92F124/F150/F250 microcontroller is de- veloped and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register programming model for ultra-fast con- text switching and real-time event response. The intelligent on-chip peripherals offload the ST9 core from I/O and data management processing tasks allowing critic...
Vendor:HITACHIPackage Cooled:TQFP-M144PD/C:07+
Multi-channel selector Lch input Input selector Rch output Multi-channel selector Rch input Input selector Lch input 1 Input selector Rch input 1 Input selector Lch input 2 Input selector Rch input 2 Input selector Lch input 3 Input selector Rch input 3 Input selector Lch input 4 Input selector Rch input 4 Input selector Lch input 5 Input selector Rch input 5 Input selector Lch input 6 Input selector ...
Package Cooled:06+D/C:800
D/C:08+/09+
The AUTO ON-LINE® feature allows the device to automatically "wake-up" during a shutdown state when an RS-232 cable is connected and a connected peripheral is turned on. Otherwise, the device automatically shuts itself down drawing less than 1µA. TABLE 1
Collector C Base Cutoff Current, IE= 0mA, VCB=-10V Emitter C Base Cutoff Current, IC= 0mA, VEB=-10V Collector C Base Breakdown Voltage, IC= -10µA, IE= 0mA Collector C Emitter Breakdown Voltage, IC= -10mA, IB= 0mA Emitter C Base Breakdown Voltage, IE= -10µA, IC= 0mA DC Current Gain, IC= -12mA, VCE=-0.15V
Vendor:804
In addition to transmitting configuration data to the FPGAs, the configuration circuit is also responsible for pausing configuration whenever there is insufficient data available for transmission. This occurs when the flash read bandwidth is lower than the configuration write bandwidth. Configuration is paused by stopping the DCLK to the FPGA, when waiting for data to be read from the flash or for data ...
D/C:176
. . . employing the Schottky Barrier principle in a large area metal-to-silicon power diode. State of the art geometry features epitaxial construction with oxide passivation and metal overlay contact. Ideally suited for low voltage, high frequency rectification, or as free wheeling and polarity diodes in surface mount applications where compact size and weight are critical to the system.
Package Cooled:06+D/C:800
The LTC®3704 is a wide input range, current mode, positive-to-negative DC/DC controller that drives an N-channel power MOSFET and requires very few external components. Intended for low to high power applications, it eliminates the need for a current sense resistor by utilizing the power MOSFETs on-resistance, thereby maxi- mizing efficiency.
Vendor:HYPERSTONEPackage Cooled:08+D/C:2400
NIST (National Institute of Standards and Technology) operates an Internet Time Service from Boulder, Colorado, using multiple servers distributed around the country. The NIST servers distribute time using the Time, Daytime, and NTP formats.
Package Cooled:TQFP164D/C:03+04+05
3. Preventive measure against oscillation For preventing the oscillation, it is advisable to use C4, the condenser of polyester film having small characteristic fluctuation of the temperature and the frequency. The condenser (C6) between input and GND is effective for preventing oscillation which is generated with a feedback signal from a output stage. The resistance R to be series applied to C4 is ef...
Vendor:RENESERPackage Cooled:QFPD/C:05+
Package Cooled:TQFP
Vendor:TIPackage Cooled:QFP64D/C:08+
• Short C when two or more lines are short-circuited together. • Open C Lack of continuity between pins at both ends of the cable. • Crossed pair C When a pair is connected to different pins at each end (i.e. Pair 1 is connected
Vendor:NSPackage Cooled:DIP
Package Cooled:QFP-120D/C:05+/CB
Vendor:TIPackage Cooled:SSOP20D/C:2007+
Package Cooled:SOP20D/C:06+
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or at any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Package Cooled:SOP20D/C:06+
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or at any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The TMS27C512 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC512 OTP PROM is supplied in a 32-lead plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix).
The TMS27C512 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC512 OTP PROM is supplied in a 32-lead plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix).
Vendor:ATMELPackage Cooled:TSSOP24D/C:01+
Vendor:ATMELPackage Cooled:SOP-24D/C:06+
Vendor:PHIPackage Cooled:CQFPD/C:04+
Vendor:NECPackage Cooled:01+D/C:N/A
The LEDs are packed in cardboard boxes after packaging in anti-electrostatic bags. Please refer to figures page. The label on the minimum packing unit shows ; Part Number, Lot Number, Ranking, Quantity In order to protect the LEDs from mechanical shock, we pack them in cardboard boxes for transportation. The LEDs may be damaged if the boxes are dropped or receive a strong impact against them, so pre...
Vendor:MORNSUNPackage Cooled:ORG PACKINGD/C:08+
Vendor:MORNSUNPackage Cooled:ORG PACKINGD/C:08+
Vendor:N/APackage Cooled:00+D/C:SOP-8
Vendor:SPackage Cooled:SOP20
Vendor:MOTPackage Cooled:DIP
Vendor:SGS THOMPackage Cooled:SOP-8PD/C:00+
Vendor:STPackage Cooled:DIP-8D/C:06+
Vendor:PHILIPSPackage Cooled:01+D/C:N/A
digital or analog input Three 16-bit timer/counters Highly flexible reload, capture, compare capabilities Full-duplex serial channel Twelve interrupt vectors, four priority levels 8-bit A/D converter with 8 multiplexed inputs and programmable internal reference voltages 16-bit watchdog timer
Vendor:ZIOLGPackage Cooled:DIP
Recordings are stored in on-chip Flash memory cells, providing zero-power message storage. This unique single-chip solution is made possible through Winbonds patented Multi-Level Storage (MLS) technology. Audio data are stored directly in solid-state memory without digital compression, providing superior quality voice and music reproduction.
D/C:97
The LS323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset shift left shift right parallel load and hold operations The type of operation is determined by S0 and S1 as shown in the Mode Select Table All flip-flop outputs are brought out through TRI-STATE buffers to separate I O pins that also serve as data inputs in the parallel load mode Q...
Vendor:NECPackage Cooled:QFPD/C:9606
Internal Sample-and-Hold Single +1.9V 0.1V Operation Choice of SDR or DDR output clocking Interleave Mode for 2x Sampling Rate Multiple ADC Synchronization Capability Guaranteed No Missing Codes Serial Interface for Extended Control Fine Adjustment of Input Full-Scale Range and Offset Duty Cycle Corrected Sample Clock
Vendor:SHARPPackage Cooled:_____________D/C:96+
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Vendor:TSSOP8Package Cooled:800
Vendor:TSSOP8Package Cooled:800