FMG26U

Bidirectional 8-bit input/output port. Each bit can be configured as wake-up in- put by options. Software instructions determine the CMOS output or Schmitt trigger or CMOS (dependent on options) input with a pull-high resistor (deter- mined by pull-high options).

FMG2A /G2

Vendor:ROHMPackage Cooled:SOT-153D/C:09+

FMG2A-T148

Vendor:ROHMPackage Cooled:04D/C:2730

Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.

FMG2A-T148

Vendor:ROHMPackage Cooled:04D/C:2730

Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.

FMG2AT149

Package Cooled:3000D/C:00+

An additional feature of the ispLSI 3160 is the Boundary Scan capability, which is composed of cells connected between the on-chip system logic and the device's input and output pins. All I/O pins have associated boundary scan registers, with 3-state I/O using three boundary scan registers and inputs using one.

FMG2G100US120

Vendor:FAIRCHILD

On-chip communications peripherals include: USB control- ler, ACCESS.bus, Microwire/Plus, SPI, UART, and Ad- vanced Audio Interface (AAI). Additional on-chip peripherals include DMA controller, PCM/CSVD conversion module, Timing and Watchdog Unit, Versatile Timer Unit, Multi- Function Timer, and Multi-Input Wakeup.

FMG2G100US60

The programmable features of the ICS8430I-61 support two input modes and to program the M divider and N output di- vider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider and N output divider. On the LOW-to-...

FMG2G150US120

DESCRIPTION The SPN2302 is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density , DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuit...

FMG2G150US120

DESCRIPTION The SPN2302 is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density , DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuit...

FMG2G200LS60

In more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of DATEL's HS Series heat sinks. See Ordering Information for the assigned part number. See page 1-183 of the DATEL Data Acquisition Components Catalog for more information on the HS Series. Request DATEL Application Note AN-8, "Heat Sinks for DIP Data Con...

FMG2G300LS60E_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

FMG2G300US60

Vendor:3Package Cooled:farchildD/C:N/A

The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device. 2. Each channel. 3. Enable Input - No pull up resistor required as the device has an internal pull up resistor. 4. tPLH - P...

FMG2G400LS60

Vendor:FairchildPackage Cooled:NEW

Enhanced 2D Graphics Controller Supports pixel depths of 8, 16, 24 and 32 bit. Full BitBLT implementation for all 256 raster operations defined for Windows. Supports 4 transparent BLT modes - Bitmap Transparency, Pattern Transparency, Source Transparency and Destination Transparency. Hardware clipping Fast line draw engine with anti-aliasing. Supports 4-bit alpha blended font for anti- aliased tex...

FMG2G400US60_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

FMG2G50US120

Note 6: Junction to ambient thermal resistance (no external heat sink) for the 7 lead TO-220 package mounted vertically, with 1⁄2 inch leads soldered to a PC board containing approximately 4 square inches of (1 oz.) copper area surrounding the leads.

FMG2G75US120

CDMA balanced input pin. This pin is internally DC-biased and should be DC-blocked if connected to a device with a DC level other than VCC present. A DC to connection to VCC is acceptable. For single-ended input operation, one pin is used as an input and the other CDMA input is AC-coupled to ground. The balanced input impedance is 1kΩ, while the single-ended input impedance is 500Ω.

FMG2G75US60A

The second solution can be used if all digits' segments are required. This time, hexadecimal-decode operation can be selected because the standard segment connection pattern is used (Table 4). The penalty for this configuration is that one diode is required per digit (Figure 2). Each diode is passing only one segment's current, so it can be a low-cost single signal diode like 1N4148, BAS16 (silicon), or BAT...

FMG3 / G3

Vendor:ROHMPackage Cooled:SOT-153D/C:09+

FMG32R

Vendor:NECPackage Cooled:01+D/C:N/A

FMG-32R

Vendor:三肯Package Cooled:TOD/C:07+

♦ Four ADC Channels with Serial LVDS/SLVS Outputs ♦ Excellent Dynamic Performance 69.6dB SNR at fIN = 19.3MHz 92dBc SFDR at fIN = 19.3MHz -87dB Channel Isolation ♦ Ultra-Low Power 135mW per Channel (Normal Operation) 1.2mW Total (Shutdown Mode) ♦ Accepts 20% to 80% Clock Duty Cycle

FMG32S

Vendor:NECPackage Cooled:01+D/C:N/A

The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle.

FMG32S

Vendor:NECPackage Cooled:01+D/C:N/A

The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle.

FMG-32S

Vendor:三肯Package Cooled:TOD/C:07+

Expansion Memory (Optional in 176-pin packages) Three address zones for static devices, with config- urable wait states and 8- or 16-bit-wide bus Up to 1 Mbyte of additional code and data Supports host-controlled code download and on- board flash update Memory access protection

FMG-33R

Vendor:三肯Package Cooled:TOD/C:07+

for Fibre Channel, SCSI and emerging interface technologies such as InfiniBand, Serial ATA and others. Thinner drivers allow for better and more versatile performance while adding value at the firmware level. Fusion-MPT provides the flexibility and rich feature set to make options like Integrated Mirroring possible for boot volume protection at no additional cost.

FMG33S

Vendor:NSCPackage Cooled:TO-220FD/C:05+

Complies with CCITT Recommendation G.721C1988 Complies with the American National Standard (T1.301C1987) FullCDuplex, SingleCChannel Operation MuCLaw or ACLaw Coding is Pin Selectable Synchronous or Asynchronous Operation Easily Interfaces with Any Member of Motorolas PCM CodecCFilter MonoCCircuit Family or Other Industry Standard Codec Serial PCM and ADPCM Data Transfer Rate from 64 kbps to 5.12 Mbp...

FMG-33S

Vendor:三肯Package Cooled:TOD/C:07+

In addition to the standard output configuration, the outputs of the ispLSI 1032EA are individually program- mable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output con...

FMG-33SR

Vendor:三肯Package Cooled:TOD/C:07+

FMG-34R

Vendor:三肯Package Cooled:TOD/C:07+

1. The FMG-34R CMOS operational amplifier uses a 3 gain stage architecture and an improved frequency compensation scheme to achieve large voltage gain, high output driving capability, and better frequency stability. In a conventional CMOS operational amplifier design, compensation is achieved with a pole splitting capacitor together with a nulling resistor. This method is, however, very bias depen...

FMG-34R

Vendor:三肯Package Cooled:TOD/C:07+

1. The FMG-34R CMOS operational amplifier uses a 3 gain stage architecture and an improved frequency compensation scheme to achieve large voltage gain, high output driving capability, and better frequency stability. In a conventional CMOS operational amplifier design, compensation is achieved with a pole splitting capacitor together with a nulling resistor. This method is, however, very bias depen...

FMG34S

Vendor:NECPackage Cooled:01+D/C:N/A

These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses effectively are isolated.

FMG-34S

Vendor:三肯Package Cooled:TOD/C:07+

1. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under rec- ommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

FMG36R

Vendor:NECPackage Cooled:01+D/C:N/A

Industry's first TotalCMOS™ PLD - both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed 3V, In-System Programmable (ISP) using a JTAG interface - On-chip supervoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms - 4-pin JTAG interface (TCK, T...

FMG36R

Vendor:NECPackage Cooled:01+D/C:N/A

Industry's first TotalCMOS™ PLD - both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed 3V, In-System Programmable (ISP) using a JTAG interface - On-chip supervoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms - 4-pin JTAG interface (TCK, T...

FMG-36R

Vendor:三肯Package Cooled:TOD/C:07+

FMG-36S

Vendor:三肯Package Cooled:TOD/C:07+

The 3-STATE control gate operates as two input and such that if either G1 and G2 are high, all eight outputs are in the high impedance state. In order to enhance PC board layout, the 74AC541 offers a pinout having inputs and outputs on opposite side of the package. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient exces...

FMG3A /G3

Vendor:ROHMPackage Cooled:SOT-153D/C:09+

FMG4A

Vendor:ROHM ?Package Cooled:96+?D/C:1640

• Microchip's web site: www.microchip.com • Microchip's Technical Library CD-ROM, Order No. DS00161 • More than 112 Application Notes available: C Embedded Control Handbook, Order No. DS00092 C Embedded Control Handbook, Volume 2, Math Library, Order No. DS00167 • Microchip's Overview, Quality Systems and Customer Interface System, Order No. DS00169 • Third party software and h...

FMG4AT148

READY/BUSY: The RDY/BSY pin provides the devices ready/busy status when using the A/A Mux interface. The RDY/BSY pin is a reflection of Status Register bit 7, which is used to indicate whether a program or erase operation has been completed. Use of the RDY/BSY pin is optional, and the pin does not need to be connected.

FMG4-T148

FMG5 MCT149

FMG5A

Vendor:availPackage Cooled:ROHM　D/C:06+

The Hynix HYM76V8735HGT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes memory. The Hyundai HYM76V8735HGT8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

FMG5A /G5

FMG5A T148

Vendor:ROHM ?Package Cooled:00+?D/C:2500

FMG6 / G6

Vendor:ROHMPackage Cooled:SOT-153D/C:09+

FMG7 / G7

Vendor:ROHMPackage Cooled:SOT-153D/C:09+

FMG7 T149

Vendor:availPackage Cooled:ROHM　D/C:06+

FMG7 T149

Vendor:availPackage Cooled:ROHM　D/C:06+

FMG75US60

Vendor:FARCHILD

FMG7A\G7

FMG7AT148

Vendor:27000Package Cooled:ROHMD/C:02+

Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

FMG7T149

Vendor:ROHMPackage Cooled:N/AD/C:N/A

When collision signaling is enabled, a 10 MHz signal is sent from the CD pins through an isolation transformer to the DTE. When the function is disabled, this output goes to a zero differential state. The 10 MHz output from the CD pins indicates a collision on the transmission media, a heartbeat function, or that the transmitter is in jabber mode.

FMG7T149

Vendor:ROHMPackage Cooled:N/AD/C:N/A

When collision signaling is enabled, a 10 MHz signal is sent from the CD pins through an isolation transformer to the DTE. When the function is disabled, this output goes to a zero differential state. The 10 MHz output from the CD pins indicates a collision on the transmission media, a heartbeat function, or that the transmitter is in jabber mode.

FMG8 MCT149

FMG8A T149

Vendor:ROHMD/C:2006

FMG8AT148

TRI-STATE is a registered trademark of National Semiconductor Corporation COP8TM Microcontrollers MICROWIRETM MICROWIRE PLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation iceMASTERTM is a trademark of MetaLink Corporation

FMG8AT149

Vendor:ROHMPackage Cooled:N/AD/C:N/A

The out-of-band receiver in the FMG8AT149 contains a frequency agile oscillator that can downconvert any channel in the 70C130 MHz frequency range to a SAW centered IF. The desired channel is then subsampled by a 6-bit A/D converter at a rate that is more than 4 times the symbol rate. An additional 6-bit A/D is provided to allow for direct input of baseband signals

FMG8AT149

Vendor:ROHMPackage Cooled:N/AD/C:N/A

The out-of-band receiver in the FMG8AT149 contains a frequency agile oscillator that can downconvert any channel in the 70C130 MHz frequency range to a SAW centered IF. The desired channel is then subsampled by a 6-bit A/D converter at a rate that is more than 4 times the symbol rate. An additional 6-bit A/D is provided to allow for direct input of baseband signals

FMG9A

Vendor:ROHMPackage Cooled:SOT153D/C:02+

Accesses to the MBAR register at long word $3FF00 are internal only, and are only visible by enabling show cycles. Users should directly access only the MBAR register, and use the LPSTOP instruction to generate the LPSTOP broadcast access to $3FFFE. The remaining address range $3FF04-3FFFD is Motorola reserved and should not be accessed.

FMG9AT148

Vendor:ROHMPackage Cooled:2008D/C:60,000

• I2C-bus standard and fast mode compatible • TSSOP8 and SO8 packages • Programmable conversion rate (0.0625 Hz to 26 Hz) • Undervoltage lockout prevents erroneous temperature readings • Latch-up testing is done to JESDEC Standard JESD78 which

FMG9AT148

Vendor:ROHMPackage Cooled:2008D/C:60,000

• I2C-bus standard and fast mode compatible • TSSOP8 and SO8 packages • Programmable conversion rate (0.0625 Hz to 26 Hz) • Undervoltage lockout prevents erroneous temperature readings • Latch-up testing is done to JESDEC Standard JESD78 which

FMG9A-T148

Vendor:ROHMPackage Cooled:SOT23-5D/C:N/A

FMG-G12R

Vendor:SANKENPackage Cooled:TO-220FD/C:04+

Line Build-Out, Transmitter: Logic low used with 225ft or more of cable is used on transmit path. Logic high used with less than 225ft of cable. DS3, E3 and STS-1 Select: Set low for E# applications. Set high for DS3, allow to float for STS-1 operation. Formerly OPT! on the 78P7200. Transmitter Enable: When high, enables transmitter. When low, tri-states transmitter drivers, LOUT. This pin was called OPT@ o...

FMG-G12R

Vendor:SANKENPackage Cooled:TO-220FD/C:04+

Line Build-Out, Transmitter: Logic low used with 225ft or more of cable is used on transmit path. Logic high used with less than 225ft of cable. DS3, E3 and STS-1 Select: Set low for E# applications. Set high for DS3, allow to float for STS-1 operation. Formerly OPT! on the 78P7200. Transmitter Enable: When high, enables transmitter. When low, tri-states transmitter drivers, LOUT. This pin was called OPT@ o...

FMG-G12S

Vendor:SANKENPackage Cooled:TO-220FD/C:04+

• Multiple output clocks at different frequencies Three CPU clocks at 2.5V, up to 100 MHz Nine 3.3V SDRAM clocks at 100 MHz Eight synchronous PCI clocks at 33 MHz Two synchronous APIC clocks at 16.67 MHz or 33 MHz Two 3V66 clocks at 66 MHz Two USB clocks at 48 MHz One reference clock at 14.318 MHz

FMG-G12S

Vendor:SANKENPackage Cooled:TO-220FD/C:04+

• Multiple output clocks at different frequencies Three CPU clocks at 2.5V, up to 100 MHz Nine 3.3V SDRAM clocks at 100 MHz Eight synchronous PCI clocks at 33 MHz Two synchronous APIC clocks at 16.67 MHz or 33 MHz Two 3V66 clocks at 66 MHz Two USB clocks at 48 MHz One reference clock at 14.318 MHz

FMGG26

These 4-bit magnitude comparators perform comparison of straight binary or BCD codes Three fully-decoded decisions about two 4-bit words (A B) are made and are externally available at three outputs These devices are fully expand- able to any number of bits without external gates Words of greater length may be compared by connecting compara- tors in cascade The A l B A k B and A e B outputs of a stage h...

FMG-G26L

Vendor:SANKENPackage Cooled:TO-220FD/C:02+

FMG-G26L contains 1024 x 8 bits serial EEPROM with programmable write protection for each byte. Ran- dom access to any byte except PSC is always possible. The memory can also be written/erased byte by byte after the two bytes PSC are verified successfully. Each byte in the memory is protected by an its individual protect bit. The protect bit is one-time programmable and cannot be erased. After the protec...

FMG-G26S

Vendor:SKPackage Cooled:TO220F

Reliable CMOS with MNOS cell technology 105 erase/write cycles (in page mode) 10 years data retention Software data protection Write protection by RES pin (only the HN58C257A series) Industrial versions (Temperatur range: C 20 to 85˚C and C 40 to 85˚C) are also available.

FMGG2CS

D/C:08+/09+

Inhibit*: This is an open-collector (open-drain) negative logic input, that is referenced to GND. Driving this pin to GND disables the modules output voltage. If Inhibit* is left open-circuit, the output will be active whenever a valid input source is applied.

FMG-G2CS

Vendor:SANKENPackage Cooled:07+D/C:TO-220

The ULN2001A, ULN2002A, ULN2003A, and ULN2004A are monolithic high-voltage, high-current Darlington transistor arrays. Each consists of seven npn Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current rating of a single Darlington pair is 500 mA. The Darlington pairs may be paralleled for higher current capability. Applicati...

FMG-G3CS

Vendor:SANKENPackage Cooled:TO-220FD/C:04+

A detailed block diagram of the UCC3941 is shown in Fig. 1. Unique control circuitry provides high efficiency power conversion for both light and heavy loads by tran- sitioning between discontinuous and continuous conduc- tion based on load conditions. Fig. 2 depicts converter

FMG-S-T148

FMH25N50G

FMI27851

Vendor:DDCPackage Cooled:DIP24D/C:9420

Bank Select Address (BA0 and BA1) defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the Command Truth Table for details on device commands.

FMIPSS-125-101M

D/C:88500

FMK1-K671

Vendor:METALLHAUBEPackage Cooled:N/AD/C:04+

Leads are Readily Solderable Lead and Mounting Surface Temperature for Soldering Purposes: 260C Max. for 10 Seconds Shipped in 12 mm Tape and Reel, 5000 units per reel Polarity: Polarity Band Indicates Cathode Lead ESD Protection: Human Body Model > 4000 V (Class 3) ESD Protection: Machine Model > 400 V (Class C) Marking: U4J

FMK3-2003

Vendor:N/APackage Cooled:N/AD/C:03+

HIGH PERFORMANCE • Polynomial complies to Intelsat IESS-308; RTCA DO-217 Appendix F, Revision D and proposed ITU-TS SG-18 (Formerly CCITT SG- 18) standards • 50 MBytes/sec burst transfer rate with a 50 MHz clock for all block lengths • Sustained data transfer rate of 12.5 MBytes/sec for block lengths from 54 bytes through 255 bytes using a 50 MHz clock • Processing latenc...

FMK3-2003

Vendor:N/APackage Cooled:N/AD/C:03+

HIGH PERFORMANCE • Polynomial complies to Intelsat IESS-308; RTCA DO-217 Appendix F, Revision D and proposed ITU-TS SG-18 (Formerly CCITT SG- 18) standards • 50 MBytes/sec burst transfer rate with a 50 MHz clock for all block lengths • Sustained data transfer rate of 12.5 MBytes/sec for block lengths from 54 bytes through 255 bytes using a 50 MHz clock • Processing latenc...

FMK3G-K1334

Vendor:METALLHAUBEPackage Cooled:N/AD/C:04+

The power factor controller section consists of the LinFinity LX1562 Power Factor Controller IC (IC1), MOSFET M1, inductor L3, diode D5, capacitor C8 and additional biasing, sensing and compensation components (see schematic). This IC was chosen for its minimal component count, low start-up supply current and robust error amplifier. This is a boost topology designed to step-up and regulate the output DC bu...

FMK4-K576

Vendor:FCTPackage Cooled:N/AD/C:00+

IF input frequency at iFInP and iFInM: 130 MHz. IF differential input voltage 480 mVp-p across a matched 360Ω differential impedance (240 mVp-p at iFInP and iFInM, with a single ended impedance of 180Ω). This input level is calculated from a 50Ω power source delivering -11 dBm to a lossy 7.2:1 impedance transforming network. The test circuit for this input is shown in Figure 32.

FMK4-K576

Vendor:FCTPackage Cooled:N/AD/C:00+

IF input frequency at iFInP and iFInM: 130 MHz. IF differential input voltage 480 mVp-p across a matched 360Ω differential impedance (240 mVp-p at iFInP and iFInM, with a single ended impedance of 180Ω). This input level is calculated from a 50Ω power source delivering -11 dBm to a lossy 7.2:1 impedance transforming network. The test circuit for this input is shown in Figure 32.

FMK4-K671

Vendor:360

The ISL6434 monitors all the output voltages. A single Power Good signal is issued when the core is within 10% of the DAC setting and all other outputs are above their under- voltage levels. Additional built-in overvoltage protection for the core output uses the lower MOSFET to prevent output voltages above 115% of the DAC setting. The PWM controllers overcurrent function monitors the output current b...

FMKA130_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

FMKA130L

Vendor:Fairchild

NOTES:1. Complete part number includes a suffix to identify operating temperature range (E or L) and package type (LH, LT, or UA). 2. As used here, negative flux densities are defined as less than zero (algebraic convention) and -50 G is less than +10 G. 3. Typical Data is at TA = +25C and VCC = 12 V and is for design information only.

FMKA140

Package Cooled:N/AD/C:01+

HY57V28820A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

FMKA140_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

FML10

Vendor:三肯Package Cooled:TOD/C:07+

NOTES 1Guaranteed by characterization. 2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition. 3Data: C[7:0]; S[7:0]; Y[7:0] Control: P_HSYNC; P_ VSYNC; P_BLANK; S_HSYNC; S_VSYNC; S_BLANK

FML10

Vendor:三肯Package Cooled:TOD/C:07+

NOTES 1Guaranteed by characterization. 2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition. 3Data: C[7:0]; S[7:0]; Y[7:0] Control: P_HSYNC; P_ VSYNC; P_BLANK; S_HSYNC; S_VSYNC; S_BLANK

FML12R

VDE = Differential Error Voltage = Common-Mode Error Voltage. See Theory of Operation section. VFS = 2 (VREFHI C VREFLO). 3Maximum input transition time (10% to 90%) = 0.8/(2f) where f is the operating CLK rate. 4Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.

FML12S

Vendor:3063Package Cooled:三肯D/C:N/A

These N-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for low voltage applications such as audio a...

FML12S

Vendor:3063Package Cooled:三肯D/C:N/A

These N-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for low voltage applications such as audio a...

FML-12S

Vendor:三肯Package Cooled:TOD/C:07+

Members of the Texas Instruments Widebus™ Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Distributed VCC and GND Pins Minimi...

FML-13S

Vendor:三肯Package Cooled:TOD/C:07+

The FCT240T and FCT244T are octal buffers and line drivers designed to be employed as memory address drivers, clock drivers, and bus-oriented transmitters/receivers. The devices provide speed and drive capabilities equivalent to their fastest bipolar logic counterparts while reducing power consumption. The input and output voltage levels allow direct interface with TTL, NMOS, and CMOS devices without e...

FML14S

Vendor:SANKENPackage Cooled:TO-220FD/C:02+

The SynchFet family of Co-Pack RAD-Hard MOSFETs and Schottky diodes offers the designer an innovative, board space saving solution for switching regulator and power management applications. RAD-Hard MOSFETs utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. Combining this technology with International Rectifiers low forward drop Schottky rectifiers results...

FML-14S

Vendor:三肯Package Cooled:TOD/C:07+

FML-14S

Vendor:三肯Package Cooled:TOD/C:07+

FML16S

Vendor:SANKENPackage Cooled:TO-220FD/C:02+

The FML16S is a 2048-stage ultra low voltage operation BBD variable delay line in audio frequency range. The device operates on +3 V supply and provides a signal delay up to 102.4 ms and is suitable for use as reverberation effect of low voltage operation audio equip- ment such as portable stereo, radio cassette recorder and microphone.

FML22R

Vendor:SANKENPackage Cooled:TO220F

High Drive External Buffer Output Enable. These signals provide two output enable controls for external data bus transceivers on the memory and peripheral data bus, MDATA. BOEN[0] is asserted low during external device read transactions. BOEN[1] is asserted low during SDRAM read transactions.

FML22R

Vendor:SANKENPackage Cooled:TO220F

High Drive External Buffer Output Enable. These signals provide two output enable controls for external data bus transceivers on the memory and peripheral data bus, MDATA. BOEN[0] is asserted low during external device read transactions. BOEN[1] is asserted low during SDRAM read transactions.

FML-22R

Vendor:SANKENPackage Cooled:07+D/C:TO-220

For BCP converters configured with the negative-polarity option on the On/Off Control pin ("N" suffix added to part number), operation is opposite to that described above. The converter is disabled when the On/Off Control pin is left open and enabled when pulled low.