Index "F"Vendor:INTELPackage Cooled:98+D/C:BGA35*35
Spectrum. The finite Fourier transform (FFT) of the discrete-time-sampled TH output. Ideally, this is obtained with a very high-resolution ADC quantizing the TH output with a clock rate locked to the TH clock (the ADC may be clocked at a slower rate than the TH). In the case of a dual TH (DTH), we can also use the beat frequency test, where the input frequency is close to an integer multiple of the clock fr...
Vendor:INTELPackage Cooled:0535+D/C:BGA
The 82C37A is an enhanced version of the industry standard 8237A Direct Memory Access (DMA) controller, fabricated using Intersils advanced 2 micron CMOS process. Pin compatible with NMOS designs, the 82C37A offers increased functionality, improved performance, and dramatically reduced power consumption. The fully static design permits gated clock operation for even further reduction of power.
Vendor:INTELPackage Cooled:0535+D/C:BGA
The Automatic Shut-Off is a safety system which turns off the electrical power of a load based either on a movement detection or a position detection. This detection will be taken into account after a well defined time delay. A typical application is the safety feature in irons which will switch off the heating element when the iron is left immobile for a well defined period, which can be dependant on the p...
Vendor:64Package Cooled:INTERD/C:N/A
The HEF4049B provides six inverting buffers with high current output capability suitable for driving TTL or high capacitive loads. Since input voltages in excess of the buffers supply voltage are permitted, the buffers may also be used to convert logic levels of up to 15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic elements is shown in the table below.
Vendor:INTELPackage Cooled:BGA
SILENT SWITCHER â UHC SMART STARTUltraFET â SPMVCX STAR*POWER Stealth SuperSOT-3 SuperSOT-6 SuperSOT-8 SyncFET TinyLogic TruTranslation
Vendor:INTELPackage Cooled:BGA
Vendor:INTELPackage Cooled:BGAD/C:0247+
Vendor:INTELPackage Cooled:BGAD/C:0411+
Vendor:INTELPackage Cooled:BGA
Vendor:INTELPackage Cooled:BGAD/C:03+
As VCE is further increased, beyond the thermally limited region, the safe output current decreases more rapidly. This so-called second breakdown region is a characteristic of bipolar output transistors. It is caused by the tendency of bipolar transistors to produce hot spotspoints on the transistor where current flow concentrates at high VCE. Exceeding the safe output current in the second breakdown re...
Vendor:INTELPackage Cooled:BGAD/C:03+
As VCE is further increased, beyond the thermally limited region, the safe output current decreases more rapidly. This so-called second breakdown region is a characteristic of bipolar output transistors. It is caused by the tendency of bipolar transistors to produce hot spotspoints on the transistor where current flow concentrates at high VCE. Exceeding the safe output current in the second breakdown re...
Vendor:INSTELD/C:99
Note 4: The LTC1998C is guaranteed to meet specified performance from 0C to 70C. The LTC1998C is designed, characterized and expected to meet specified performance from C40C to 85C but is not tested or QA sampled at these temperatures. The LTC1998I is guaranteed to meet specified performance from C40C to 85C. Note 5: This parameter is not 100% tested.
Vendor:INSTELD/C:99
Note 4: The LTC1998C is guaranteed to meet specified performance from 0C to 70C. The LTC1998C is designed, characterized and expected to meet specified performance from C40C to 85C but is not tested or QA sampled at these temperatures. The LTC1998I is guaranteed to meet specified performance from C40C to 85C. Note 5: This parameter is not 100% tested.
The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/ word address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organization).
The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/ word address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organization).
Vendor:availPackage Cooled:INTELD/C:05+
Feedback input. When ADJ is grounded, the device enters fixed voltage mode. When ADJ is con- nected to an external resistor network, the device operates as an adjustable regulator. The Adjust pin can also be tied directly to the OUT pin which configures the CM3004 as a 1.2V regulator.
Vendor:INTELPackage Cooled:0535+D/C:BGA
(e) For a dual device surface mounted on 85 sq cm single sided 2oz copper on FR4 PCB, in still air conditions with all exposed pads attached attached. The copper area is split down the centre line into two separate areas with one half connected to each half of the dual device. (f) For a dual device with one active die. (g) For dual device with 2 active die running at equal power. (h) Repetitive rating - pu...
Vendor:INTELPackage Cooled:BGAD/C:N/A
Vendor:INTELPackage Cooled:BGAD/C:9933+
Vendor:INTELPackage Cooled:BGAD/C:02+
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Vendor:INTELPackage Cooled:BGAD/C:02+
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Vendor:INTELPackage Cooled:BGAD/C:99+
Two-level OCP with 96mS delay time Peak-current-mode operation with cycle-by-cycle current limiting PWM frequency continuously decreasing w/ burst mode at light loads Low start-up current (8uA) Low operating current (3.7mA) VDD over-voltage protection (OVP) AC input brownout protection with hysteresis Programmable over-temperature protection (OTP) Constant power limit over universal AC input ra...
Vendor:INTELPackage Cooled:BGA
The function of the Data Output Register can be controlled by the user via the FT mode pin (Pin 14 in the TQFP). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register.
Vendor:INSTELD/C:99
This manual describes the hardware of the H8S/2149 and H8S/2169 F-ZTAT™. Although the H8S/2169 is not explicitly mentioned in Section 2 to 7 or Section 9 to 22, the descriptions in these Sections apply to both the H8S/2149 and H8S/2169.
Vendor:INTELPackage Cooled:BGAD/C:02+
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
Vendor:INTELPackage Cooled:50D/C:N/A
Vendor:INTELPackage Cooled:BGA
OFFSET VOLTAGE OFFSET CURRENT TEST The offset voltage and offset current tests are performed in the same general way as the bias current test The only difference is that the switches S5a and S5b are closed on the same half-cycle of the triangular wave input The synchronous operation of S5a and S5b forces the ampli- fier under test to draw its input currents through matched high and low input resistors on...
Vendor:INTELPackage Cooled:BGAD/C:0518+
Vendor:intelPackage Cooled:02+D/C:BGA
Vendor:INTELPackage Cooled:BGAD/C:00+
Vendor:INTELPackage Cooled:BGAD/C:00+
Vendor:INTELPackage Cooled:BGAD/C:0022+
Vendor:INTELPackage Cooled:BGAD/C:N/A
Vendor:INTELPackage Cooled:BGAD/C:04+
Vendor:INTELPackage Cooled:BGAD/C:0302+
Vendor:INTELPackage Cooled:BGAD/C:0302+
Vendor:INTELPackage Cooled:BGAD/C:01+
Vendor:INTELPackage Cooled:BGAD/C:01/02+
Vendor:INTELPackage Cooled:BGAD/C:01/02+
Vendor:INTELPackage Cooled:BGA
The 80C186EB Timer Counter Unit (TCU) provides three 16-bit programmable timers Two of these are highly flexible and are connected to external pins for control or clocking A third timer is not connected to any external pins and can only be clocked internally However it can be used to clock the other two timer channels The TCU can be used to count external events time external events generate non-repe...
Vendor:INTELD/C:0133+
Vendor:INTELD/C:0308+
Programmable Output Voltage to 36 V Voltage Reference Tolerance: 0.4%, Typ @ 25C (TL431B) Low Dynamic Output Impedance, 0.22 W Typical Sink Current Capability of 1.0 mA to 100 mA Equivalent Full−Range Temperature Coefficient of 50 ppm/C Typical Temperature Compensated for Operation over Full Rated Operating Temperature Range Low Output Noise Voltage Pb−Free Packag...
Vendor:INTELPackage Cooled:BGAD/C:02+
The Run-Time Mode provides a standard JTAG interface for on-chip debugging, and the Real-Time Mode provides additional status pins PCST[2:0]which are used in conjunction with the JTAG pins for real- time trace information at the processor internal clock or any division of the pipeline clock.
The SMJ320C6203 device is part of the SMJ320C62x fixed-point DSP generation in the SMJ320C6000 DSP platform. The C62x DSP devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.
Vendor:availPackage Cooled:INTELD/C:00+
Vendor:intelPackage Cooled:BGAD/C:2003+
Vendor:intelPackage Cooled:BGAD/C:2003+
Vendor:BGAPackage Cooled:5D/C:INTEL
Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28 lead SOIC, the bat- tery/crystal package (i.e. SNAPH...
Vendor:intelPackage Cooled:BGAD/C:2003+
Notes: 5. Distribution data sample size is 450 samples taken from 9 different wafers. Future wafers allocated to this product may have nominal values anywhere within the upper and lower specification limits. 6. Measurements made on production test board, Figure 4. This circuit represents a trade-off between an optimal noise match and a realizable match based on production test requirements ...
Vendor:intelPackage Cooled:BGAD/C:2003+
Notes: 5. Distribution data sample size is 450 samples taken from 9 different wafers. Future wafers allocated to this product may have nominal values anywhere within the upper and lower specification limits. 6. Measurements made on production test board, Figure 4. This circuit represents a trade-off between an optimal noise match and a realizable match based on production test requirements ...
Vendor:INTELPackage Cooled:BGAD/C:03+
In questo capitolo saranno illustrate tutte le operazioni da effettuare per ottenere il corretto funzionamento della scheda. A questo scopo di seguito riportata la funzione dei jumpers, dei connettori e di tutti quei componenti che possono modificare il comportamento della scheda.
Vendor:INTELPackage Cooled:BGAD/C:00+
NOTES 1. MAXIMUM ALIGNMENT DEVIATION BETWEEN LEADS NOT TO BE GREATER THAN 0.2 mm. 2. MAXIMUM NON-CUMULATIVE VARIATION BETWEEN TAPE FEED HOLES SHALL NOT EXCEED 1 mm IN 20 PITCHES. 3. HOLDDOWN TAPE NOT TO EXCEED BEYOND THE EDGE(S) OF CARRIER TAPE AND THERE SHALL BE NO EXPOSURE OF ADHESIVE. 4. NO MORE THAN 3 CONSECUTIVE MISSING COMPONENTS ARE PERMITTED. 5. A TAPE TRAILER, HAVING AT LEAST THREE FEED HOLES...
Vendor:INTELPackage Cooled:0535+D/C:BGA
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset error have been nulled. Note 2: No missing codes over temperature. Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period. Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz. Note 5: The...
Vendor:INTELPackage Cooled:1000D/C:04+
Vendor:INTELPackage Cooled:1000D/C:04+
Vendor:N/AD/C:08+09+
Vendor:INTELPackage Cooled:BGA
Vendor:INTELPackage Cooled:BGA
Vendor:INTELPackage Cooled:BGAD/C:0410+
Vendor:availPackage Cooled:INTELD/C:05+
Supports Interrupt on change, eliminates management polling Flexible built-in LED support for TX Activity, RX Activity and Collision Indication or Activity, Link state and Collision Digital PLL circuit using advanced digital algorithm to reduce jitter Low-power, high-performance CMOS process Available in a small outline 100-pin LQFP 3.3V DC power with 5V DC tolerant I/O
Vendor:availPackage Cooled:INTELD/C:05+
Supports Interrupt on change, eliminates management polling Flexible built-in LED support for TX Activity, RX Activity and Collision Indication or Activity, Link state and Collision Digital PLL circuit using advanced digital algorithm to reduce jitter Low-power, high-performance CMOS process Available in a small outline 100-pin LQFP 3.3V DC power with 5V DC tolerant I/O
Vendor:INTELPackage Cooled:0535+D/C:BGA
These units are single, dual, and quad channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full MIL-PRF-38534 Class Level H or K testing or from the appro- priate DSCC Drawing. All devices are manufactured and tested on a MIL-PRF-38534 certified line and a...
Vendor:INTELPackage Cooled:BGAD/C:03+
Vendor:INTELPackage Cooled:BGA
Vendor:INTELPackage Cooled:BGAD/C:0714+/0726+
Vendor:INTELPackage Cooled:BGAD/C:0714+/0726+
Vendor:intelPackage Cooled:BGAD/C:03+
There is a small temperature drift of the comparator thresh- olds in the 8038. To compensate for this, the voltage divider at pin 7 uses thin film resistors plus diffused resistors. The different temperature coefficients of these resistors causes the voltage at pins 7 and 8 to vary 0.5mV/oC to maintain overall low frequency drift at VCC = 20V. At higher supply voltages, e.g., 15V (+30V), th...
Vendor:intelPackage Cooled:BGAD/C:03+
There is a small temperature drift of the comparator thresh- olds in the 8038. To compensate for this, the voltage divider at pin 7 uses thin film resistors plus diffused resistors. The different temperature coefficients of these resistors causes the voltage at pins 7 and 8 to vary 0.5mV/oC to maintain overall low frequency drift at VCC = 20V. At higher supply voltages, e.g., 15V (+30V), th...
Vendor:INTELPackage Cooled:SOP
Vendor:N/APackage Cooled:N/AD/C:9+
CS/HOLD (Pin 4): CMOS-Level Digital Enable Input for the Latch Holding F and G Bits. Logic 0 makes the latch transparent so that the F and G inputs directly control the filters cutoff frequency and gain. Logic 1 holds the last values of these inputs prior to the transition. This pin floats to logic 0 (V C) when open circuited because of a small current source (see Electrical Characteristics, Note 5).
Vendor:INTELPackage Cooled:BGA
Important notice: This document contains information of a new product. IC Media Corp reserves the right to make any changes without further notice to any product herein to improve design, function or quality and reliability. No responsibility is assumed by IC Media Corp for its use, nor for any infringements of patents of third parties which may result from its use.
Vendor:INTELPackage Cooled:BGAD/C:0345+
Vendor:N/APackage Cooled:N/AD/C:08+09+
Low cost 3.3 V CMOS MxFE for broadband modems 12-bit D/A converter 2/4 interpolation filter 200 MSPS DAC update rate Integrated 23 dBm line driver with 19.5 dB gain control 12-bit, 80 MSPS A/D converter −12 dB to +48 dB low noise RxPGA (< 2.5 nV/rtHz) Third order programmable low-pass filter Flexible digital data path interface Half- and full-duplex operation Backward compatible with AD9...
Vendor:N/APackage Cooled:N/AD/C:08+09+
Low cost 3.3 V CMOS MxFE for broadband modems 12-bit D/A converter 2/4 interpolation filter 200 MSPS DAC update rate Integrated 23 dBm line driver with 19.5 dB gain control 12-bit, 80 MSPS A/D converter −12 dB to +48 dB low noise RxPGA (< 2.5 nV/rtHz) Third order programmable low-pass filter Flexible digital data path interface Half- and full-duplex operation Backward compatible with AD9...
Vendor:N/APackage Cooled:N/AD/C:08+09+
Short-Circuit Protection The outputs are protected against the short circuit. The FW82801DBSL6DM protects the circuit for shorted output by sens- ing the output voltages. The FW82801DBSL6DM shuts down the PWM signals and LDO controller, when the output volt- ages drops below the set values.
Vendor:N/APackage Cooled:N/AD/C:08+09+
Short-Circuit Protection The outputs are protected against the short circuit. The FW82801DBSL6DM protects the circuit for shorted output by sens- ing the output voltages. The FW82801DBSL6DM shuts down the PWM signals and LDO controller, when the output volt- ages drops below the set values.
Vendor:INTELPackage Cooled:BGA
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the ...
Vendor:INTELPackage Cooled:BGA31*31D/C:03+
Vendor:INTELPackage Cooled:BGA
Vendor:INTEL
Vendor:ITNELPackage Cooled:BGAD/C:05+
The ISL6118 has integrated current sensing on the power MOSFETs that allows for rapid control of OC events. Once an OC condition is detected the ISL6118 goes into its current regulation (CR) control mode. The ISL6118 CR level is set to a nominal 0.6A and is regulated to within 25% over full temperature, bias voltage range and OC magnitude. The speed of this control is proportional to the level of OC. Thus a ...
Vendor:300
The SM561 is a very simple and versatile device to use. The frequency and spread% range is selected by programming S0 and S1 digital inputs. These inputs use three (3) logic states including High (H), Low (L), and Middle (M) to select one of the
Vendor:300
The SM561 is a very simple and versatile device to use. The frequency and spread% range is selected by programming S0 and S1 digital inputs. These inputs use three (3) logic states including High (H), Low (L), and Middle (M) to select one of the
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the Power Good and Crowbar functions. This pin should be connected to the common point of the output inductors.
Vendor:availPackage Cooled:INTELD/C:0423+
Vendor:INTELPackage Cooled:BGAD/C:0322+
Vendor:INTEL
Vendor:INTEL
Vendor:INTEL
The 165 and LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputsarediode-clamped...
Vendor:INTELPackage Cooled:BGA
Vendor:INTEL Package Cooled:BGAD/C:0548+
Vendor:INTELPackage Cooled:516D/C:BGA
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH1645 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels.
Vendor:INTELPackage Cooled:527D/C:BGA
Single channel T1/E1/J1 long haul/short haul line interfaces Supports HPS (Hitless Protection Switching) for 1+1 protection without external relays Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024 KHz Programmable T1/E1/J1 switchability allowing one bill of ma- terial for any line condition Single 3.3 V power supply with 5 V tolerance on digital interfaces Meets or exceeds specifications in ...
Vendor:INTELD/C:04
VCXO parts from ICS require that locations be provided to tune the load capacitance of the pullable crystal. This tuning serves to center the crystal's operating frequency relative to the VCXO, thereby increasing the range of frequencies that can be locked-to by the VCXO over that of an untuned board.
Vendor:INTELPackage Cooled:BGAD/C:04+