F02JA4LTP

Vendor:OriginPackage Cooled:SMDD/C:09+

This specification is intended to guarantee interface compatibility of the other members of the CY7C370 family with the CY7C371. This specification is met for the devices operating at the same ambient tem perature and at the same power supply voltage.

F02JK2E

Vendor:ORIGIN

Furthermore some critical parasitics have to be considered. These are shortened loops (e.g. in the ground line of the PCB board) close to the antenna and undesired loops in the antenna circuit. Shortened loops decrease Q of the circuit. They have the same effect like conducting plates close to the antenna. To avoid undesired loops in the antenna circuit it is recommended to mount the capac- itor Cres ...

F02JK6

Vendor:ORIGINPackage Cooled:SOT23D/C:06+ROHS

ICM-107B is a single-chip digital color-imaging device. It incorporates a 1152x864 sensor array capable of operating at up to 30 frames per second and sub-sampled quarter mega pixel resolution, operating at higher frame rate in progressive manner. Each pixel is covered by a color filter, which formed a so-called Bayer pattern. Correlated double sampling is performed by the internal ADC and timing circuit...

F02SL

Vendor:FUJIPackage Cooled:TSSOPD/C:00+

The data of Figure 13 is based on TJ(pk) = 150C; TC is variable depending on conditions. At high case temperatures, thermal limitations will reduce the power than can be handled to values less than the limitations imposed by second breakdown.

F02SL

Vendor:FUJIPackage Cooled:TSSOPD/C:00+

The data of Figure 13 is based on TJ(pk) = 150C; TC is variable depending on conditions. At high case temperatures, thermal limitations will reduce the power than can be handled to values less than the limitations imposed by second breakdown.

F031478

F032RM-004

Vendor:WIESON

F0333A245

Vendor:TQFP128Package Cooled:296D/C:NEC

Application Notes Differences between VPX 3220A and VPX 322xD Impact to Signal to Noise Ratio Control Interface Symbols Write Data into I2C Register Read Data from I2C Register Write Data into FP Register Read Data from FP Register Sample Control Code Xtal Supplier Typical Application

F035L

Package Cooled:SSOPD/C:O0+

The EVBD4400 evaluation board implements a single power phaseleg circuit on a double sided PCB with ground plane, using the proven ISOSMARTTM HALF BRIDGE DRIVER CHIPSET - IXBD4410, IXBD4411, IXDP630. The IXDP631 is optional. This board includes all parts required for the circuit implementation so that you can just follow the instructions in this document and connect the board to the load and power. T...

F03-647-0001

Vendor:WALTA

F036823

F037114

F038192

F0402E1R50FWTRM

D/C:07+

Characteristics, Switching Characteristics Under this heading, the most important operational electrical characteristics (minimum, typical and maxi- mum values) are grouped together with associated test conditions supplemented with graphs.

F0408S291

Vendor:TQFP128Package Cooled:1008D/C:NEC

Skyworks CX65105 Evaluation Board is used to test the performance of the CX65105 PA. The Evaluation Board schematic diagram is shown in Figure 9. The schematic shows the basic design of the board for the 1700 to 2200 MHz range. Figure 10 provides the Evaluation Board assembly diagram. Figure 11 provides the Evaluation Board layer detail.

F041ND

F042AHH

Vendor:ZILOGPackage Cooled:SSOP20D/C:05+

F045T120

F0500T

Vendor:50008Package Cooled:Teccor/LittelfuseD/C:N/A

Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device outside of its operating ratings. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(Max), the junction-to-ambient thermal resistance, JA, and the ambient temperature, TA. The maximum allowable power dissipation wi...

F0500T

Vendor:50008Package Cooled:Teccor/LittelfuseD/C:N/A

Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device outside of its operating ratings. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(Max), the junction-to-ambient thermal resistance, JA, and the ambient temperature, TA. The maximum allowable power dissipation wi...

F0500T0461.500

Vendor:65000Package Cooled:LF(TEC)D/C:2008

The following are trademarks of Conexant Systems, Inc.: Conexant™, the Conexant C symbol, and Whats Next in Communications Technologies™. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners.

F0500TRP

D/C:07+

Note: There are two versions available: one for 5 V logic and the other one for 3.3 V logic requiring additional supply via the V33V pin. The IC can be set to stand-by mode via an control input. In addition the 5 V-version offers a receive only mode feature to support diagnostic functions.

F0500TRP

D/C:07+

Note: There are two versions available: one for 5 V logic and the other one for 3.3 V logic requiring additional supply via the V33V pin. The IC can be set to stand-by mode via an control input. In addition the 5 V-version offers a receive only mode feature to support diagnostic functions.

F0505S-1W

Vendor:MORNSUNPackage Cooled:SIPD/C:09+

These SiGe HBT amplifiers exhibit a soft breakdown effect (VBCEO=7.5V minimum) which allows for large signal operation at VCE=5V. The user should insure that under large signal conditions the source and load impedances presented to the device dont result in excessive collector currents near breakdown. Small signal operation with VCE<7V is acceptable.

F050828

Vendor:FLTPackage Cooled:QFN-12D/C:06+

Received Data Output, push-pull CMOS driver output capable of driving standard CMOS or TTL loads. During transmission the Rxd output is inactive. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 kΩ (typ.) in shutdown mode. The voltage swing is defined by the applied Vlogic voltage

F050828

Vendor:FLTPackage Cooled:QFN-12D/C:06+

Received Data Output, push-pull CMOS driver output capable of driving standard CMOS or TTL loads. During transmission the Rxd output is inactive. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 kΩ (typ.) in shutdown mode. The voltage swing is defined by the applied Vlogic voltage

F050904

Vendor:FLTPackage Cooled:06+D/C:QFN-64

The ZL10037 is a fully integrated direct conversion tuner for digital satellite receiver systems. It provides excellent immunity to composite undesired channels. The device also contains a RF Bypass for connecting to a second receiver module.

F050914

Vendor:NOPackage Cooled:QFN-38D/C:06+

F050920

Package Cooled:06+D/C:QFN-36

F0509M-1W

Vendor:MORNSUNPackage Cooled:ORG PACKINGD/C:08+

The phase detector and the M divider force the VCO output fre- quency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.

F0509S/D-1W

Vendor:MORNSUNPackage Cooled:ORG PACKINGD/C:08+

F0509S-2W

Vendor:MORNSUNPackage Cooled:SIPD/C:09+

F0512D-2W

Vendor:MORNSUNPackage Cooled:DIPD/C:09+

F0515D-2W

Vendor:MORNSUNPackage Cooled:DIPD/C:09+

F05240000

Vendor:NECPackage Cooled:QFP/100D/C:05+

The CP3BT10 connectivity processor combines high perfor- mance with the massive integration needed for embedded Bluetooth applications. A powerful RISC core with on-chip SRAM and Flash memory provides high computing band- width, communications peripherals provide high I/O band- width, and an external bus provides system expandability.

F0547A249

Vendor:TQFP128Package Cooled:100D/C:NEC

Positive Supply Voltage. +5V Digital Circuit Ground Reset Input. The RST input pin contains a Schmitt voltage input to recognize external active high Reset inputs. The pin also employs an internal pulldown resistor to allow for a combination of wired OR external reset sources. An RC is not required for power-up, as the device provides this function internally.

F0547A249

Vendor:TQFP128Package Cooled:100D/C:NEC

Positive Supply Voltage. +5V Digital Circuit Ground Reset Input. The RST input pin contains a Schmitt voltage input to recognize external active high Reset inputs. The pin also employs an internal pulldown resistor to allow for a combination of wired OR external reset sources. An RC is not required for power-up, as the device provides this function internally.

F05B23VR

Vendor:SHINDENGEN ?Package Cooled:N/A?D/C:1125

The no-correction window acts as a filter for low frequency jitter and wander since the DPLL does not track the reference signal inside it. The size of the no-correction window is less than or equal to the size of the input jitter buffer on the T1 and CEPT devices to guarantee that no slip will occur in the received T1/CEPT frame.

F05B23VR

Vendor:SHINDENGEN ?Package Cooled:N/A?D/C:1125

The no-correction window acts as a filter for low frequency jitter and wander since the DPLL does not track the reference signal inside it. The size of the no-correction window is less than or equal to the size of the input jitter buffer on the T1 and CEPT devices to guarantee that no slip will occur in the received T1/CEPT frame.

F05J2ETP

Vendor:ORIGINPackage Cooled:SOT-23D/C:07+

Through the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block as needed. A total of 80 product terms are available from the local product term array. The product term allocator provides two important capabilities without affecting perfor- mance: product term steering and product term sharing.

F05J2ETP

Vendor:ORIGINPackage Cooled:SOT-23D/C:07+

Through the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block as needed. A total of 80 product terms are available from the local product term array. The product term allocator provides two important capabilities without affecting perfor- mance: product term steering and product term sharing.

F05J2ETP / EAS

F05J4LTP

Vendor:ORIGINPackage Cooled:SOT-23D/C:07+

The LM1881 Video sync separator extracts timing informa- tion including composite and vertical sync, burst/back porch timing, and odd/even field information from standard nega- tive going sync NTSC, PAL* and SECAM video signals with amplitude from 0.5V to 2V p-p. The integrated circuit is also capable of providing sync separation for non-standard, faster horizontal rate video signals. The vertical outp...

F05J4LTP ECS

F05J4LTP/ECS

Vendor:ORIGINPackage Cooled:SOT-23D/C:08+

Ever increasing CPU bus clock speeds, coupled with faster peripheral devices, have engendered I/O bottlenecks in high-speed, networked applications such as switches, routers and storage servers. The HyperTransport technology is a fast, non-proprietary, point-to-point link that offers the speed necessary for these advanced systems.

F05J4LTP/ECS

Vendor:ORIGINPackage Cooled:SOT-23D/C:08+

Ever increasing CPU bus clock speeds, coupled with faster peripheral devices, have engendered I/O bottlenecks in high-speed, networked applications such as switches, routers and storage servers. The HyperTransport technology is a fast, non-proprietary, point-to-point link that offers the speed necessary for these advanced systems.

F05J4TR\EC5

F05S05/1000Z

F0603C0R50FWTRM

D/C:07+

The LT®6650 is a micropower, low voltage 400mV refer- ence. Operating with supplies from 1.4V up to 18V, the device draws only 5.6µA typical, making it ideal for low voltage systems as well as handheld instruments and industrial control systems. With only two resistors the internal buffer amplifier can scale the 400mV reference to any desired value up to the supply voltage.

F0603C1R00FWTR

Vendor:AVXPackage Cooled:0603-1AD/C:08+

3. The SI-8300L series may not start up if the input voltage rises too rapidly. Do not use the SI-8300L series in applications where the input terminal, pin6, is opened and closed directly in a state where the input voltage is already applied.

F0603C1R00FWTR

Vendor:AVXPackage Cooled:0603-1AD/C:08+

3. The SI-8300L series may not start up if the input voltage rises too rapidly. Do not use the SI-8300L series in applications where the input terminal, pin6, is opened and closed directly in a state where the input voltage is already applied.

F0603C1R25FWTRM

D/C:07+

For A-to-B data flow, the device operates on the low-to-high transition of CLKAB if CEAB is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, CLKBA, and CEBA.

F0603C1R75FWTRM

Vendor:AVXPackage Cooled:0603-1.75AD/C:05+

Thermal Resistance, Junction-to-Case - IGBT Thermal Resistance, Junction-to-Case - Diode Thermal Resistance, Case-to-Sink - Module Mounting Torque, Case-to-Heatsink Mounting Torque, Case-to-Terminal 1, 2 & 3 ➂ Weight of Module

F0603C2R00FWTRM

D/C:07+

*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabil...

F0603C2R50FWTR

D/C:07+

The Fairchild Switch FST16861 provides 20-Bits of high- speed CMOS TTL-compatible bus switching. The low ON resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.

F0603C3R00FWTRM

Vendor:AVXPackage Cooled:N/AD/C:08+

The MSP430FG43x series are microcontroller configurations with two 16-bit timers, a high performance 12-bit A/D converter, dual 12-bit D/A converters, three configurable operational amplifiers, one universal synchronous/asynchronous communication interface (USART), DMA, 48 I/O pins, and a liquid crystal display (LCD) driver.

F0603E3R00FFSTRM(30V3A)

Vendor:AVX ?Package Cooled:04+?D/C:2616

Timer Clearing A negative edge or pulse at the TCL input longer than 150 ns will clear the timer and deactivate the reset outputs under normal running conditions (see Fig. 3). TCL will however have no effect either when VDD < VOFF or during the initialization period before the deactivation of the reset pins. Combined Voltage and Timer Action In Fig. 6 is a typical sequence of power-up, watchdog r...

F0603FA1000V032T

D/C:07+

At the burst's end the voltage on Cs, which is on the order of a few tenths of a volt, is amplified by a gain circuit which includes an offset current from the R2R ladder DAC driven by the X drive lines. The offset current from the R2R ladder repositions the output of the amplifier chain to coincide as closely as possible with the center span of the 60320's ADC, which can convert voltages

F0603FA2000V032T

Vendor:07+Package Cooled:40000

F0603FA2500V032T

Vendor:07+Package Cooled:40000

F0603FA5000V032T

Vendor:07+Package Cooled:40000

F0603HI1000V032T

Vendor:AEMD/C:4000

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage ...

F060S120

BOOT: This pin provides the high side rail for the HDRIVE output.An external capacitor (CBST) is connected between this pin and the drain of the external low side MOSFET. When the low side MOSFET is conducting Cbst is charged to 11V via an external diode tied to CAP. When the low side MOSFET turns off and the high side MOSFET turns on, the Cbst bootstraps itself up with the source of high side MOSFET,...

F060T060

F060T060

F062MJ7B/CGF

Package Cooled:DIP8D/C:00+

F064115F9

Package Cooled:06+D/C:800

The Hynix HYM76V8C755AT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes mem- ory. The Hyundai HYM76V8C755AT8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band- width.

F06769B

Vendor:THAERUPackage Cooled:08+D/C:160000

The IS41LV32256 is compatible with JEDEC standard SGRAMs. This 8-Mbit EDO memory offers a significantly lower latency and a faster memory cycle than the SGRAM. ISSI's IS41LV32256 3.3V 256K x 32 device is pin/voltage compatible with all standard SGRAM parts.

F06A02

Package Cooled:TO-220D/C:2002

F06A4

Vendor:STPackage Cooled:00+D/C:QFN-8

The F06A4 operates with one of four possible input reference frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). The frequency select inputs (FS1 and FS2) determine which of the four frequencies may be used at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency select input change. See Table 1.

F06A4

Vendor:STPackage Cooled:00+D/C:QFN-8

The F06A4 operates with one of four possible input reference frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). The frequency select inputs (FS1 and FS2) determine which of the four frequencies may be used at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency select input change. See Table 1.

F06C15C

Vendor:MOSPECPackage Cooled:TO-220D/C:05+

XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly addressed mem- ory transactions. The highly-efficient protocol yields over 95% utilization while allowing fine access granularity. The devices eight banks support up to four interleaved transactions.

F06C20

Vendor:MOSPECPackage Cooled:TOD/C:07+

F06C20C

Vendor:MOSPECPackage Cooled:08+D/C:2000

F06C20C

Vendor:MOSPECPackage Cooled:08+D/C:2000

F06C30C

Vendor:MOSPECPackage Cooled:TO-220D/C:05+

This flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive- going transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input.

F06F150S

Vendor:1380D/C:N/A

The Hynix HYM71V32755AT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The Hynix HYM71V32755AT8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band- width.

F06U20DP

Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design.

F072F

Vendor:TD/C:08+

F080095E

Vendor:STPackage Cooled:BGAD/C:00+

F08020A1

Package Cooled:DIP

The Sequencer can be a variety of logic operators, such as a FIFO loaded with various algorithms, an external software driven algorithm, or an internal state machine. This flexibility allows the designer to reconfigure the ECU for algorithmic intensive applications in which functions change on the next clock cycle, such as adaptive filtering.

F08020A1

Package Cooled:DIP

The Sequencer can be a variety of logic operators, such as a FIFO loaded with various algorithms, an external software driven algorithm, or an internal state machine. This flexibility allows the designer to reconfigure the ECU for algorithmic intensive applications in which functions change on the next clock cycle, such as adaptive filtering.

F08020AI

Note: 1. H=VIH, L=VIL, X=don't care 2. UB, LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8. When UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.

F0805B0R25FWTRM

D/C:07+

• Four crystal modes up to 40 MHz • Two external clock modes up to 40 MHz • Internal oscillator block: - 8 user selectable frequencies: 31 kHz to 8 MHz - OSCTUNE can compensate for frequency drift • Secondary oscillator using Timer1 @ 32 kHz • Fail-Safe Clock Monitor: - Allows for safe shutdown of device if clock fails

F0805B0R50FWTR

D/C:07+

(14) Interrupts: 21-source, 10-vectored interrupts 1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is refused. 2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address...

F0805B0R5FWTR

F0805B0R75FSTR

Vendor:ＡＶＸ　ＣＯＲＰ

F0805B0R75FWTR

D/C:07+

The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has been expanded to support the ISO/IEC7816-3 ...

F0805B0R75FWTRM

Vendor:AVXPackage Cooled:0805-750MAD/C:08+

The PAL/NTSC pin determines the default values for the DVE control registers. The default register values have been chosen so that standard PAL or NTSC video will appear at the DAC outputs immediately when a valid input digital video data stream is present and Vmute is Low at reset. The Vmute pin controls the "out of reset" operation of the Analog output signals. When "1" at reset, the ...

F0805B1R00FWTR

F0805B1R0FWTR

Vendor:AVXPackage Cooled:0805-1AD/C:08+

Measuring Diode Parameters The measurement of the five elements which make up the equivalent circuit for a packaged Schottky diode (see Figure 10) is a complex task. Various techniques are used for each element. The task begins with the elements of the diode chip itself.

F0805B1R0FWTR

Vendor:AVXPackage Cooled:0805-1AD/C:08+

Measuring Diode Parameters The measurement of the five elements which make up the equivalent circuit for a packaged Schottky diode (see Figure 10) is a complex task. Various techniques are used for each element. The task begins with the elements of the diode chip itself.

F0805B1R25FWTR

Vendor:AVXPackage Cooled:0805-1.25AD/C:08+

The S1M8821/22/23 is a high performance dual frequency synthesizer with integrated prescalers designed for RF operation up to 1.2GHz/2.0GHz/2.5GHz and IF operation up to 520MHz. The S1M8821/22/23 contains dual-modulus prescalers. The RF synthesizer adopts a 64/65 or a 128/129 prescaler(32/33 or 64/65 for the S1M8823) and the IF synthesizer adopts an 8/9 or a 16/17 prescaler. Using a proprietary digital phase...

F0805B1R25FWTRM

D/C:07+

Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports C 4ns setup to clock and 1ns hold on all control, data, and address inputs C Data input, address, and control registers C Fast 6.5ns clock to data out in the Pipelined output mode C Self-timed write allows fast cycle time C 10ns cycle time, 100MHz operation in Pipelined output mode Separate uppe...

F0805B1R25FWTRWP2)

F0805B1R50FWTR

D/C:07+

† TPS3106E09 and TPS3110K33 will be available in August 2001; all other versions will be available in October 2001. ‡ The DBVR passive indicates tape and reel of 3000 parts. The DBVT passive indicates tape and reel of 250 parts.

F0805B1R50FWTR(1.5A)

Vendor:AVX ?Package Cooled:99+?D/C:3000

F0805B1R50FWTRM

Vendor:KYOCERAPackage Cooled:0805-1.5AD/C:05+

The W78L52 architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, one watchdog timer and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64 K data storage space.

F0805B2R00FWTR

Vendor:AVXPackage Cooled:0805-2AD/C:08+

This product is specifically designed as a final stage for 802.11a equipment in the 4.9 - 5.9 GHz band. It can run from a 3.0V to 3.6V supply. Optimized on-chip impedance matching circuitry provides a 50Ω nominal RF input imped- ance. A single external output matching circuit covers the entire 4.9-5.9GHz band. The external output match allows for load line optimization for other applications or opti- m...

F0805B2R00FWTRM

Vendor:AVXD/C:.

The A128 devices contain the following: • ARM7TDMI 16/32-Bit RISC CPU • TMS470R1x system module (SYS) with 470+ enhancements • 128K-byte Flash • 8K-byte SRAM • Zero-pin phase-locked loop (ZPLL) clock module • Analog watchdog (AWD) timer • Real-time interrupt (RTI) module • Two serial peripheral interface (SPI) modules • Two serial communications interfac...