F711287FN

Vendor:TEXAS ?Package Cooled:1999?D/C:900

• 0.23 µm Process Technology • Single 3.0 V read, program and erase Minimizes system level power requirements • Industry-standard pinouts 56-pin TSOP (1) 80-ball FBGA (Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance Page mode Fast 8 bytes / 4 words access capabililty • Sector erase architecture 256 64K byte and 32K word se...

F711287FN

Vendor:TEXAS ?Package Cooled:1999?D/C:900

• 0.23 µm Process Technology • Single 3.0 V read, program and erase Minimizes system level power requirements • Industry-standard pinouts 56-pin TSOP (1) 80-ball FBGA (Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance Page mode Fast 8 bytes / 4 words access capabililty • Sector erase architecture 256 64K byte and 32K word se...

F711301/P

Vendor:NQRTELPackage Cooled:N/AD/C:9+

F711301AGFX

The logic signals coming from the typical motor controller IC are set up for driving N channel low side and P channel high side switches directly, and are usually 15 volt levels. Provision should be made for getting 5 volt logic signals to the MSK4351 of the correct assertion levels. Typically, the low side signals out of the controller are high active and the high side are low active. Inverters are shown...

F711301AGFX

The logic signals coming from the typical motor controller IC are set up for driving N channel low side and P channel high side switches directly, and are usually 15 volt levels. Provision should be made for getting 5 volt logic signals to the MSK4351 of the correct assertion levels. Typically, the low side signals out of the controller are high active and the high side are low active. Inverters are shown...

F711302AGGQ

Vendor:TID/C:07/08+

The ADS8381 is an 18-bit, 580 kHz A/D converter. The device includes a 18-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8381 offers a full 18-bit interface, a 16-bit option where data is read using two read cycles, or an 8-bit bus option using three read cycles.

F711317BGFN

Vendor:TIPackage Cooled:BGAD/C:N/A

4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The part also features various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 mA maximum when in full shutdown.

F711317BGFNR

F711322APPM

Package Cooled:QFP

The following specifications apply for VIN= 14V; VSHUTDOWN = Open; ILOAD = 10mA; TA = +25˚C; COUT = 10µF, 0.5Ω < ESR < 4.0Ω; unless otherwise specified. Bold Values indicate −40˚C TA 125˚C. (Note 4, Note 5)

F711349/P

Vendor:TIPackage Cooled:06+D/C:800

The device offers fast page access times of 25, 30, and 45 ns, with corresponding random access times of 65, 70, 85, and 90 ns, respectively, allowing high speed microproces- sors to operate without wait states. To eliminate bus conten- tion the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

F711349/P

Vendor:TIPackage Cooled:06+D/C:800

The device offers fast page access times of 25, 30, and 45 ns, with corresponding random access times of 65, 70, 85, and 90 ns, respectively, allowing high speed microproces- sors to operate without wait states. To eliminate bus conten- tion the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

F711353GFT

Vendor:TIPackage Cooled:BGA3535

Hynix HYMD232M646(L)6-K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD232M646(L)6-K/H/L series consists of eight 16Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin glass- epoxy substrate. Hynix HYMD232M646(L)6-K/H/L series provide a high performance 8-byte interface...

F711353GFT

Vendor:TIPackage Cooled:BGA3535

Hynix HYMD232M646(L)6-K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD232M646(L)6-K/H/L series consists of eight 16Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin glass- epoxy substrate. Hynix HYMD232M646(L)6-K/H/L series provide a high performance 8-byte interface...

F711360GGP

Vendor:TID/C:07/08+

• Best in class in DIP7, DIP8, TO220, I2Pak packages • Leadfree for DIP7 and DIP8 packages • Active Burst Mode to reach the lowest Standby Power Requirements < 100mW • Protection features (Auto Restart Mode) to increase robustness and safety of the system • Adjustable Blanking Window for high load jumps to increase system reliability • Isolated drain package for TO...

F711364PCM

Vendor:TIPackage Cooled:2005D/C:500

PROGRAM MEMORY Program Memory consists of a 2048-byte external memory (typically PROM) Words of this memory may be program instructions constants or ROM addressing data ROM addressing is accomplished by a 11-bit PC register which selects one of the 8-bit words contained in ROM A new address is loaded into the PC register during each in- struction cycle Unless the instruction is a transfer of control ...

F711389PCM

D/C:08+/09+

The MTV230M micro-controller is an 8051 CPU core embedded device specially tailored to LCD Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, OSD controller, 4 built-in PWM DACs, VESA DDC interface, 4-channel A/D converter, a 64K-byte internal program Flash-ROM and a 9K-word internal OSD character Flash-ROM.

F711389PCM

D/C:08+/09+

The MTV230M micro-controller is an 8051 CPU core embedded device specially tailored to LCD Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, OSD controller, 4 built-in PWM DACs, VESA DDC interface, 4-channel A/D converter, a 64K-byte internal program Flash-ROM and a 9K-word internal OSD character Flash-ROM.

F711398BGFW

The modulation and bias currents are programmable via the MSET and BSET control pins. By driving these pins with control voltages, the user has the flexibility to implement various average power and extinction ratio control schemes, including closed-loop control and look-up tables. The automatic laser shutdown feature allows the user to turn on/off the bias and modulation currents by driving the ALS pi...

F711437BGFT

Vendor:TIPackage Cooled:BGAD/C:N/A

The F711437BGFT supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The F711437BGFT operates as a Slave device. Both ...

F711437BGFT

Vendor:TIPackage Cooled:BGAD/C:N/A

The F711437BGFT supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The F711437BGFT operates as a Slave device. Both ...

F711443ACGFT

Package Cooled:N/AD/C:08+

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Derate lin...

F711443ACGFT

Package Cooled:N/AD/C:08+

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Derate lin...

F711443AGFT

D/C:01+

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Supply current specification does not include external FET gate charge currents. Actual supply currents will be higher and vary with operating frequency, operating voltages and the type of external switch elements used. See Applications Information.

F711444A

Vendor:TEXPackage Cooled:00+D/C:12

Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.

F711453AIP

Package Cooled:07+

F711460AGFN

Package Cooled:BGA

the actual fan speed. Power up default is FFh. 3.Fan status register: (FAN_STA , address : 10b) This register is read only. Its bit 0 is set to 1 when the actual fan speed is 20% outside the desired speed. Its bit 1 is set to 1 when fan speed is be- low 1920 rpm. Power up default is 10b.

F711460A-P

Vendor:TIPackage Cooled:BGAD/C:N/A

F711500AGFN

Vendor:MYLEXPackage Cooled:BGAD/C:00+

F711525PGC

Vendor:HUAWEIPackage Cooled:QFP

push-pull outputs which are sequentially pulsed in groupings of bursts; a 4-pole analog switch acts as the sample switch for all 4 Y lines. At the intersection of each X and Y line is an interdigitated electrode set as shown in Figure 1-6. Typically the outermost electrode is connected to X and the inner electrode connected to Y. Remaining Y lines not being sampled are grounded.

F711525PGC

Vendor:HUAWEIPackage Cooled:QFP

push-pull outputs which are sequentially pulsed in groupings of bursts; a 4-pole analog switch acts as the sample switch for all 4 Y lines. At the intersection of each X and Y line is an interdigitated electrode set as shown in Figure 1-6. Typically the outermost electrode is connected to X and the inner electrode connected to Y. Remaining Y lines not being sampled are grounded.

F711604PBLR

Vendor:TIPackage Cooled:TQFP168-2020D/C:99

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VD...

F711604PBLR

Vendor:TIPackage Cooled:TQFP168-2020D/C:99

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VD...

F711616CPZ

Vendor:TIPackage Cooled:0119D/C:900

Because of the true 4 quadrant method of output switching, the output switches will PWM between the ICOMMAND POSITIVE and ICOMMAND NEGATIVE states, with the average percentage based on ICOMMAND being a positive voltage and a negative voltage. With a zero voltage ICOMMAND, the output switches will modulate with exactly a 50% duty cycle between the ICOMMAND POSITIVE and ICOMMAND NEGATIVE states.

F711616CPZ

Vendor:TIPackage Cooled:0119D/C:900

Because of the true 4 quadrant method of output switching, the output switches will PWM between the ICOMMAND POSITIVE and ICOMMAND NEGATIVE states, with the average percentage based on ICOMMAND being a positive voltage and a negative voltage. With a zero voltage ICOMMAND, the output switches will modulate with exactly a 50% duty cycle between the ICOMMAND POSITIVE and ICOMMAND NEGATIVE states.

F711711/AX

F711711/P

F711711PJM

Vendor:TI

The FM803 is a supervisory device designed to monitor power supply or other system voltage. FM803 generates a reset pulse whenever the voltage being monitored is out of tolerance. Once asserted, the reset pulse is guaranteed to be valid for a minimum of 140ms (256ms typical ). The reset output of FM803 is of active low Open-Drain type and has an internal pull-up resistor.

F711746PGE

Vendor:TID/C:98+

Glass passivated high commutation triacs in a plastic envelope intended for use in circuits where high static and dynamic dV/dt and high dI/dt can occur loads. These devices will commutate the full rated rms current at the maximum rated junction temperature, without the aid of a snubber.

F711746PGE

Vendor:TID/C:98+

Glass passivated high commutation triacs in a plastic envelope intended for use in circuits where high static and dynamic dV/dt and high dI/dt can occur loads. These devices will commutate the full rated rms current at the maximum rated junction temperature, without the aid of a snubber.

F711754BPBL

Vendor:AUANTUMPackage Cooled:QFP

electrical stability and low thermal resistance. The module operates from a fixed positive voltage and requires no external matching which significantly reduces space, cost and enhances ease of use. The 6x6 mm package is self contained, incorporating 50 ohm input and output matching networks optimized for output power, linearity and efficiency. Celeriteks InGaP HBT technology offers a thermally rob...

F711754DPBL

Vendor:TIPackage Cooled:QFPD/C:01+

1) CPD isdefined as the value of the ICsinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC

F711754DPBL

Vendor:TIPackage Cooled:QFPD/C:01+

1) CPD isdefined as the value of the ICsinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC

F711857PGER(4370249)

Vendor:TIPackage Cooled:QFPD/C:06+

must be stable during the clock low-to-high transi- tion, and the data must change only when the SCL line is low. Memory Addressing To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit Device Select...

F711857PGER(4370249)

Vendor:TIPackage Cooled:QFPD/C:06+

must be stable during the clock low-to-high transi- tion, and the data must change only when the SCL line is low. Memory Addressing To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit Device Select...

F711860PWR

Vendor:TIPackage Cooled:TSSOP20D/C:01+

The SN65176B and SN75176B differential bus transceivers are integrated circuits designed for bidirectional data communication on multipoint bus transmission lines. They are designed for balanced transmission lines and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27.

F711862PGE

F711866PGE

F711O87PGF

Vendor:TIPackage Cooled:QFPD/C:02+

• 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out (FIFO) memories • 16K 9 (CY7C4261V) • 32K 9 (CY7C4271V) • 64K 9 (CY7C4281V) • 128K 9 (CY7C4291V) • 0.35-micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low powe...

F712017

Vendor:FUJIPackage Cooled:QFPD/C:02+

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropri...

F712017

Vendor:FUJIPackage Cooled:QFPD/C:02+

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropri...

F712037PGV

D/C:02+

Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference). Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit. 3Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 4Measured...

F7121-EL2

F712311ES

Vendor:FUJITSUPackage Cooled:QFPD/C:07+

F712523PGF

Vendor:TI CXD8784RPackage Cooled:0123D/C:2600

It is significant to note that this equation and Figure 7 apply to all 54C/74C devices. This is true because of the close match in drive characteristics of every device including MSI functions, i.e., the slope of the propagation delay vs load ca- pacitance line at a given voltage is typically equal for all de- vices. The only exception is high fan-out buffers which have a smaller ∆tpd/pF.

F7132P

Vendor:ROHMD/C:05+

Ground reference to LVDS and CMOS circuitry. For the LLP package, the DAP is used as the primary GND connection to the device. The DAP is the exposed metal contact at the bottom of the LLP-28 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance.

F7133391NOA

Package Cooled:08+D/C:800

F7133391NOA

Package Cooled:08+D/C:800

F7136P

Vendor:FUJID/C:05+

Reference frequency input. This externally provided reference gets divided by the selectable R divider, and is used to synthesize the desired output frequency. Typically this input is an ac-coupled sinusoid; however, a TTL or CMOS signal can also be used.

F7170AC

Vendor:MIT

Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30:

F71862FG

Vendor:QFPPackage Cooled:30D/C:FINTEK

AH286 is a monolithic fan motor controller with Hall sensors capability. It contains two complementary open-drain transistors for motors coil driving, automatic lock current shutdown, and recovery protections. In addition, rotor-state detection (RD) output is for Rotor-state detection. To avoid coil burning, rotor-lock shutdown detection circuit shut down the output driver if the rotor is blocked and then t...

F7201

Vendor:IORPackage Cooled:SOP-8

The F7201/-B are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words of 16 bits each. The F7201/-B are offered in a 48-pin TSOP(I) package, These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.

F7205

Vendor:IORPackage Cooled:SOP-8

The ILD205T/ 206T/ 207T/ 211T/ 213T/ 217T are optically coupled pairs with a Gallium Arsenide infra- red LED and a silicon NPN phototransistor. Signal information, including a DC level, can be transmitted by the device while maintaining a high degree of elec- trical isolation between input and output. The ILD205T/ 206T/ 207T/ 211T/ 213T/ 217T come in a standard SOIC-8A small outline package for surfa...

F7207

Vendor:IORPackage Cooled:SOP-8

The Fairchild Switch FSTU3125 provides four high-speed CMOS TTL-compatible bus switches. The low On Resis- tance of the switch allows inputs to be connected to out- puts without adding propagation delay or generating additional ground bounce noise. The A and B Ports are protected against undershoot to support an extended range to 2.0V below ground. Fairchilds integrated Under- shoot Hardened Circuit ...

F7210

Vendor:IORPackage Cooled:SOP-8

TO92 style package No stabilising capacitor required Typical TC 30ppm/C Typical slope resistance 0.65Ω 3% tolerance Industrial temperature range (Military temperature range available on request) Operating current 50µA to 5mA Transient response, stable in less than 10µs Alternative package options and tolerances available

F7210

Vendor:IORPackage Cooled:SOP-8

TO92 style package No stabilising capacitor required Typical TC 30ppm/C Typical slope resistance 0.65Ω 3% tolerance Industrial temperature range (Military temperature range available on request) Operating current 50µA to 5mA Transient response, stable in less than 10µs Alternative package options and tolerances available

F721500PN

Vendor:TIPackage Cooled:QFPD/C:02/03+

Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to Preliminary. Updated minimums in Table 13 and added notes to Table 14. Added to note 2 to Absolute Maximum Ratings. Changed speed grade -8 numbers for TSHCKO32, TREG, TBCCS, and TICKOF.

F721501A/P

F721582BGFN

D/C:08+/09+

F721595APZ

Vendor:SIEMENSPackage Cooled:SOPD/C:03+

The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct con- nection to a separate SNAPHAT housing contain- ing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high t...

F721629AGHF

Package Cooled:06+D/C:800

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADD8701 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid perf...

F721629AGLM

Package Cooled:06+D/C:800

650V avalanche rugged CoolMOS™ with built in switchable Startup Cell Active Burst Mode for lowest Standby Power @ light load controlled by Feedback signal Fast load jump response in Active Burst Mode 67/100 kHz fixed switching frequency Auto Restart Mode for Overtemperature Detection Auto Restart Mode for Overvoltage Detection Auto Restart Mode for Overload and Open Loop Auto Restart Mode f...

F721629AGLM

Package Cooled:06+D/C:800

650V avalanche rugged CoolMOS™ with built in switchable Startup Cell Active Burst Mode for lowest Standby Power @ light load controlled by Feedback signal Fast load jump response in Active Burst Mode 67/100 kHz fixed switching frequency Auto Restart Mode for Overtemperature Detection Auto Restart Mode for Overvoltage Detection Auto Restart Mode for Overload and Open Loop Auto Restart Mode f...

F721730B/P

F721730BPBK

F721813A/P

Vendor:TIPackage Cooled:BGAD/C:99+

Thermal Considerations The obvious advantage of the SOT-363 over the SOT-143 is combination of smaller size and two extra leads. However, the copper leadframe in the SOT-363 has a thermal conductivity four times higher than the Alloy 42 leadframe of the SOT-143, which enables it to dissipate more power.

F721813AX

F721850GFN

F721905PAGC

Vendor:TIPackage Cooled:QFP-64D/C:00+

1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, (cont.) positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.

F721961APZ

Vendor:LUCENTPackage Cooled:QFP144

Evaluating the accuracy of Maxim real-time clocks (RTCs) can be simplified using the modern personal computer (PC), an Internet connection, and RTC evaluation software. Whether you use a Maxim evaluation kit and its associated software to evaluate the accuracy of a Maxim real-time clock, or use your own software and hardware configuration, you can take advantage of the easy methods presented here for long-t...

F721961APZ

Vendor:LUCENTPackage Cooled:QFP144

Evaluating the accuracy of Maxim real-time clocks (RTCs) can be simplified using the modern personal computer (PC), an Internet connection, and RTC evaluation software. Whether you use a Maxim evaluation kit and its associated software to evaluate the accuracy of a Maxim real-time clock, or use your own software and hardware configuration, you can take advantage of the easy methods presented here for long-t...

F722504GHHES

Vendor:TIPackage Cooled:BGAD/C:07+

F7240

Vendor:IRPackage Cooled:SOP-8D/C:05+

The receiver section of the WE904/905 provide all of the required receiver functions including local oscillator synthesis (VCO), down-conversion, filtering, automatic gain control (AGC), automatic frequency control (AFC), FM/FSK demodulator and RSSI functions.

F727566-002

Vendor:FD/C:05+

F72820SG

Flash Initialization. Software is stored on an external Flash. At boot-up, the stored software is downloaded to the device. By using compilation options, software can be executed from the internal RAM (intensive operations) or executed from the flash. Execution is optimized by the use of an intermediate cache mem- ory.

F72951C

Vendor:N/APackage Cooled:SMDD/C:98+

This device is a single chip PC peripheral microcon- troller based on the Universal Serial Bus (USB) Version 1.1 specification. This device provides data exchange between a USB-equipped host computer and PC peripherals such as telephones, audio sys- tems and digital cameras. See Figure 1.1 for a pin layout diagram. See Figure 1.2 for the functional block diagram.

F7301

Vendor:IORPackage Cooled:SOP-8

Input bus select / I2C clock input. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin is only 3.3-V tolerant. When I2C is disabled (ISEL = low), a high level selects the 24-bit input, single-edge input mode. A low level selects the 12-bit input, dual-edge input mode. When I2C is enabled (ISEL = high), this pin functions as the I2C clock input (see the I2C re...

F7306

Vendor:IORPackage Cooled:SOP-8

Pin Description Address. The 15 address lines select one of 32,768 bytes in the FRAM array. The address value will be latched on the falling edge of /CE. Data. 8-bit bi-directional data bus for accessing the FRAM array. Chip Enable. /CE selects the device when low. The falling edge of /CE causes the address to be latched internally. Address changes that occur after /CE goes low will be ignored until the...

F731136/AX

ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a 1, the device is unable to verify that an erase or a byte/word program oper- ation has been successfully performed. If a program (Sector Erase) command is issued to a protected sector, the protected sector wil...

F731136D1/A

Pin Description Motor Supply Voltage Control Logic C Bridge 1 Control Logic C Bridge 1 Power Ground Return Bridge 1 Output Diagnostic Output Bridge 1 Output Bridge 2 Output Diagnostic Output Bridge 2 Output Control Logic C Bridge 2 Control Logic C Bridge 2 Logic Supply No Connect

F731136D1/P

Vendor:NQRTELPackage Cooled:N/AD/C:9+

F731182/P

Vendor:FUJITSUPackage Cooled:BGAD/C:07+

F7312

Package Cooled:SSOP-16

F73127APAG

Package Cooled:PQFP-64D/C:00+

General purpose pin 4 General purpose pin 3 Reset input 1: self-powered. 0: bus-powered Keyboard matrix sense input 1 Keyboard matrix sense input 2 Keyboard matrix sense input 3 Keyboard matrix sense input 4 Keyboard matrix sense input 5 Keyboard matrix sense input 6 Keyboard matrix sense input 7 Keyboard matrix sense input 8 Power enable for downstream port 1 Power enable for downstream p...

F73127APAG

Package Cooled:PQFP-64D/C:00+

General purpose pin 4 General purpose pin 3 Reset input 1: self-powered. 0: bus-powered Keyboard matrix sense input 1 Keyboard matrix sense input 2 Keyboard matrix sense input 3 Keyboard matrix sense input 4 Keyboard matrix sense input 5 Keyboard matrix sense input 6 Keyboard matrix sense input 7 Keyboard matrix sense input 8 Power enable for downstream port 1 Power enable for downstream p...

F731532APGE 08-0338-03

F731567A/P

D/C:08+/09+

The period required by the retransmit operation is now fixed and short. The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.) SuperSync FIFOs are part...

F731567A/P

D/C:08+/09+

The period required by the retransmit operation is now fixed and short. The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.) SuperSync FIFOs are part...

F731567AGDF

D/C:08+/09+

Isolated Hermetic Package, JEDEC TO-257AA Outline Output Voltages: 5V, 12V, 15V (Other Voltages Available) Output Voltages Set Internally To 1% or 2% Built-In Thermal Overload Protection Short Ciruit Current Limiting Product Is Available Screened To OM803

F731590

Vendor:TIPackage Cooled:N/AD/C:08+

F731590AGJM

D/C:08+/09+

• Ampelanwendung • Hinterleuchtung (LCD, Schalter, Tasten, Displays, Werbebeleuchtung) • Innen- und Außenbeleuchtung im Auto- mobilbereich (z.B. Instrumentenbeleuchtung und Bremslichter) • Ersatz von Kleinst-Glhlampen • Markierungsbeleuchtung (z.B. Stufen, Fluchtwege, u.ä.) • Signal- und Symbolleuchten