FDI14-250C

Vendor:3M ELECTRONIC PRODUCT DIVISIOND/C:N/A

The input/output pins (I/O 0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).

FDI2532

Vendor:FAIRCHILDD/C:`06+(pb-free)

The 8 'X' lines can be directly connected to the matrix without buffering. Only the X lines' positive edges are used to create the transient field flows used to scan the keys. Only one X line is active at a time, and it will pulse for a burst length determined by the 'gain' setting parameter.

FDI33N25

Vendor:FAIRCHILDPackage Cooled:TO-220/TO-262(I2PAK)D/C:`06+(pb-free)

FDI33N25

Vendor:FAIRCHILDPackage Cooled:TO-220/TO-262(I2PAK)D/C:`06+(pb-free)

FDI3532

For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low with transitions measured at 50%. The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of tSWTO. 3Guaranteed by characterization, not production tested.

FDI3632

Vendor:FAIRCHILDD/C:`06+(pb-free)

VOLLow-level output voltageUV = SOURCE AVVoltage gain, relative to SENSE0 V < RAMP − SOURCE < 5 V † All voltages are with respect to RTN unless otherwise stated. ‡ Currents are positive into and negative out of the specified terminal.

FDI3632

Vendor:FAIRCHILDD/C:`06+(pb-free)

VOLLow-level output voltageUV = SOURCE AVVoltage gain, relative to SENSE0 V < RAMP − SOURCE < 5 V † All voltages are with respect to RTN unless otherwise stated. ‡ Currents are positive into and negative out of the specified terminal.

FDI3652

Vendor:FAIRCHILDPackage Cooled:TO-262(I2PAK)D/C:`06+(pb-free)

The MAX5631/MAX5632/MAX5633 are 16-bit digital-to- analog converters (DACs) with 32 sample-and-hold (SHA) outputs for applications where a high number of programmable voltages are required. These devices include a clock oscillator and a sequencer that updates the DAC with codes from an internal SRAM. No external components are required to set offset and gain.

FDI3652

Vendor:FAIRCHILDPackage Cooled:TO-262(I2PAK)D/C:`06+(pb-free)

The MAX5631/MAX5632/MAX5633 are 16-bit digital-to- analog converters (DACs) with 32 sample-and-hold (SHA) outputs for applications where a high number of programmable voltages are required. These devices include a clock oscillator and a sequencer that updates the DAC with codes from an internal SRAM. No external components are required to set offset and gain.

FDJ1027P

Vendor:Fairchild

FDJ1028N

Vendor:Fairchild

NOTES: 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky ...

FDJ1028N

Vendor:Fairchild

NOTES: 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky ...

FDJ127P

D/C:04+

Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

FDJ128N

Vendor:FAIRCHILD/C:05+

Aqueous washable fu is the upper frequency limit for each model as shown in the table. Low frequency cutoff determined by external coupling capacitors. Environmental specifications and re-flow soldering information available in General Information Section. Units are non-hermetic unless otherwise noted. For details on case dimensions & finishes see Case Styles & Outline Drawings. Prices and Spec...

FDJ128N

Vendor:FAIRCHILD/C:05+

Aqueous washable fu is the upper frequency limit for each model as shown in the table. Low frequency cutoff determined by external coupling capacitors. Environmental specifications and re-flow soldering information available in General Information Section. Units are non-hermetic unless otherwise noted. For details on case dimensions & finishes see Case Styles & Outline Drawings. Prices and Spec...

FDJ128N/B28

FDJ128N_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

FDJ129P/A03

FDL37M602

FDL400

Vendor:FAIPackage Cooled:LL34D/C:05+

The 3-megapixel CMOS image sensor features Digital- ClarityMicrons breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitiv- ity) while maintaining the inherent size, cost, and inte- gration advantages of CMOS.

FDL4148

Hynix HYMD132G725B(L)8-M/K/H/L series is designed for high speed of up to and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined ...

FDL485B

Enable (input): Logic-compatible enable input. High input >2.1V typical. Low input <1.9V typical (-1 active high, -2 active low). Do not float. Fault Flag (Output): Active-low, open-drain output. Indicates overcurrent, UVLO, and thermal shutdown. Ground: Supply return. Supply Input: Output MOSFET source. Also supplies IC's internal circuitry. Connect to positive supply. Switch Output: Output MOSFET dra...

FDL6282

D/C:87

operating mode of the device. The pulse lasts for two cycles of the LFO oscillator as shown in Figure 4. Since the RST pin is clocked from the same divider string as the OUT pin, there will also be a pulse on the OUT pin when the RST pin pulses every 52 minutes.

FDLDA102V102HDFDM0

FDLDA102V123HDFDM0

FDLDA102V152HDFDM0

FDLDA102V183HDFDM0

FDLDA102V222HDFDM0

FDLDA102V272HDFDM0

FDLDA102V273HDFDM0

FDLDA182V103HNLDM0

FDLDA182V122HNLDM0

FDLDA182V123HELDM0

FDLDA182V153HELDM0

FDLDA182V222HNLDM0

FDLDA182V272HNLDM0

FDLDA182V392HNLDM0

FDLDA182V472HNLDM0

FDLDA182V822HNLDM0

FDLDA1C2V153HNLDM0

FDLDA1C2V472HNLDM0

FDLDA801V122HGLBM0

FDLDA801V183HGLBM0

FDLDA801V473HHLBM0

FDLL300

Vendor:FAIRCHILDD/C:05+

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because small parametric changes could cause the device not to meet its published specifications.

FDLL300_Q

Vendor:ＦＡＩＲＣＨＩＬＤ

FDLL300A

Vendor:Fairchild

Regulation is measured at constant junction temperature using low duty cycle pulse testing. Parts are tested for load regulation in the load range from 0.1mA to 150mA. Changes in output voltage due to heating effects are covered by the thermal regulation specification. Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below its nominal value measured at 1V ...

FDLL300A_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

FDLL300A-NL

FDLL333

Vendor:FAIRCHILDD/C:LL34

OUTPUT VOLTAGE PROGRAMMING Resistors R1 and R2 program the output voltage. An optional capacitor CX may be inserted across R1 to improve the transient response (see Figure 1). The value of R2 should be less than 100KΩ. The value of R1 can be determined using the following equation, note VREF is also referred to as VFBT.

FDLL400

Vendor:FAIRCHILDD/C:05+

If the port is left in a forced 1394b beta only (B1, B2, or B4) mode, then the TPB+ and TPBC terminals may be left unconnected or the TPB+ and TPBC terminals can be connected to the suggested normal termination network. The TPA+ and TPAC terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal must be pulled to ground through a 1.2-kΩ or less resistor.

FDLL4148 (ASTEC)

FDLL4148(LL34/ROHS)/FSC

FDLL4148_NL PBF

FDLL4148-NL

Hynix HYMD116M725B(L)8-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally p...

FDLL4148T

Vendor:FSC 0348

FDLL414B

Vendor:FSCD/C:04

FDLL4150

The UCC3808 is a family of BiCMOS push-pull, high-speed, low-power, pulse-width modulators. The UCC3808 contains all of the control and drive circuitry required for off-line or dc-to-dc fixed frequency current-mode switching power supplies with minimal external parts count.

FDLL4150_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

FDLL4151

Vcc = 2.3V~2.7V, TA = 0C to 70C, unless otherwise specified -12 # SymbolParameter Min. Max. READ CYCLE 1tRCRead Cycle Time120- 2tAAAddress Access Time-120 3tACSChip Select Access Time-120 4tOEOutput Enable to Output Valid-80 5tBA/LB, /UB Access Time-120 6tCLZChip Select to Output in Low Z10- 7tOLZOutput Enable to Output in Low Z5- 8tBLZ/LB, /UB Enable to Output in Low Z10- 9tCHZChip Deselectio...

FDLL4448

Vendor:FAIRCHILDD/C:O9+

The open-circuit detection provides a defined output voltage if the VDD or GND line is broken. Internal tem- perature compensation circuitry and the choppered off- set compensation enables operation over the full tem- perature range with minimal changes in accuracy and high offset stability. The circuitry also rejects offset shifts due to mechanical stress from the package. The non-volatile memory co...

FDLL4448

Vendor:FAIRCHILDD/C:O9+

The open-circuit detection provides a defined output voltage if the VDD or GND line is broken. Internal tem- perature compensation circuitry and the choppered off- set compensation enables operation over the full tem- perature range with minimal changes in accuracy and high offset stability. The circuitry also rejects offset shifts due to mechanical stress from the package. The non-volatile memory co...

FDLL457A

Vendor:FAIRCHILDD/C:LL34

connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with recommended values of 5 kΩ and 220 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal recei...

FDLL914

Vendor:FSCPackage Cooled:LL34D/C:07+

Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the ORP. Each ispLSI 2032 and 2032A device contains one Megablock.

FDLL914B

Vendor:FSCPackage Cooled:LL-34D/C:08+

FDM2452NZ

Vendor:FAIRCHILDPackage Cooled:QFN6D/C:07+

Parameter Carrier Frequency Operating Voltage (VDD_MEM) Operating Voltage (VDD_PIO) RF Output Power RX Sensitivity Load Impedance Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Average Current Consumption

FDM2509NZ

Vendor:FAIRCHILDPackage Cooled:QFN6D/C:07+

USB-IF Hi-Speed certified to the Universal Serial Bus Specification Rev 2.0 Interface compliant with the ULPI Specification revision 1.1 in 8-bit mode. Industry standard UTMI+ Low Pin Interface (ULPI.) Converts 54 UTMI+ signals into a standard 12 pin Link controller interface. Supports FS pre-amble for FS hubs with a LS device attached (UTMI+ Level 3) Supports HS SOF and LS keep-alive pulse. Includes full...

FDM2512NZ

Vendor:FAIRCHILDPackage Cooled:QFN6D/C:05+

These electrically erasable programmable memo- ry (EEPROM) devices are accessed by a high speed SPI-compatible bus. The M95320, M95320-W, M95320-R and M95320-S are 32Kbit devices organized as 4096 x 8 bits. The M95640, M95640-W, M95640-R and M95640-S are 64Kbit devices organized as 8192 x 8 bits.

FDM303

Vendor:FUJPackage Cooled:QFP-52D/C:04+

Data Inputs/Outputs: Inputs array data during program operation, when CE# and WE# are active. Data is internally latched during the write and program cycles. When CE# and OE# are active, the output sends array data, manufacturer code or device code. The data pins float to tri-state when the chip is deselected or the outputs are disabled.

FDM3300N

Vendor:FAIRCHILDPackage Cooled:microFET

DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50µA) Low Output Voltage, (IOL = 1.6mA) High Output Voltage, (IOH = 50µA) High Output Voltage, (IOH = 0.5mA) Low Output Voltage, (IOL = 50µA) High Output Voltage, (IOH = 50µA) 3-State Enable Time 3-State Disable Time Output Capacitance

FDM3300NZ

Vendor:FAIRCHILDPackage Cooled:SON-8D/C:07+

Two channels of EMI filtering Pi-style EMI filters in a capacitor-resistor-capacitor (C-R-C) network Greater than 40dB attenuation at 1GHz +8kV ESD protection on each channel (IEC 61000-4-2 Level 4, contact discharge) +15kV ESD protection in each channel (HBM) Supports AC signalsideal for audio applications Extremely low lead inductance for optimum filter and ESD performance 5-bump, 0.950mm X 1....

FDM3300NZA

Vendor:FAIRCHILDPackage Cooled:MLP-8D/C:6

!Features 1) Four channels of power MOS-H bridges are contained. 2) Available for PWM input. 3) Applicable for stepping-motor drive. 4) Separating VM into CH1, CH2 and CH3 / 4. 5) Low on-resistance 1.3Ω (typ.) 6) Low power consumption. 7) SSOP-B24 package.

FDM3622NZ

Vendor:FAIRCHILDPackage Cooled:MLP-8D/C:07+

Discontinuous mode operation provides high efficiency operation at light loads. A forced continuous control pin reduces noise and RF interference and can assist second- ary winding regulation by disabling discontinuous mode operation when the main output is lightly loaded.

FDM44528S9J

Package Cooled:07+D/C:PLCC

TSOP40 C 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . . . . . . . . 23 TSOP40 C 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . . . . . . . . 23 SO44 C 44 lead Plastic Small Outline, 525 mils body width, Package Outline. . . . . . . . . . . . . . . . 24 SO44 C 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data . . . . ....

FDM606P

Vendor:FAIRCHILDPackage Cooled:MLPD/C:07+

10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained.

FDM6296_NL

Vendor:ＦＡＩＲＣＨＩＬＤ

FDMA1023PZ

Vendor:FAIRCHILDPackage Cooled:QFN6D/C:07+

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so

FDMA1027P

Vendor:FAIRCHILDD/C:08+

Master mode and snapshot mode output signal. Active HIGH during readout. The two-wire serial interface register setting switches this pin between input and output. Master mode and snapshot mode output signal. Active HIGH when image data are on data output bus. The two-wire serial interface register setting switches this pin between input and output. Master mode output signal. Active HIGH during exposure...

FDMA430NZ

Vendor:FAIRCHILDPackage Cooled:QFN6D/C:07+

3.3 Volt Operation (SIO Block is 5 Volt Tolerant) LPC Interface ACPI 1.0/2.0 Compliant Fan Control -Fan Speed Control Outputs (2) -Fan Tachometer Inputs (2) Programmable Wake-up Event Interface PC98, PC99, PC01 Compliant Dual Game Port Interface MPU-401 MIDI Support

FDMC2523P

Vendor:FairchildPackage Cooled:MLP8D/C:08+

The S1M8821/22/23 is a high performance dual frequency synthesizer with integrated prescalers designed for RF operation up to 1.2GHz/2.0GHz/2.5GHz and IF operation up to 520MHz. The S1M8821/22/23 contains dual-modulus prescalers. The RF synthesizer adopts a 64/65 or a 128/129 prescaler(32/33 or 64/65 for the S1M8823) and the IF synthesizer adopts an 8/9 or a 16/17 prescaler. Using a proprietary digital phase...

FDMC2610

Vendor:FSCPackage Cooled:QFND/C:07+

DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes.

FDMC2674

Vendor:FSCPackage Cooled:QFND/C:07+

CURRENT LIMIT PROTECTION The LX8819 includes over current protection. When the output load current exceeds 1.4A (typical) the current limit protection circuit forces the regulator to decrease the output current in order to maintain safe levels.

FDMC3300NZA

Vendor:FAIRCHILDPackage Cooled:QFND/C:07+

C672x: 32-/64-Bit 300-MHz Floating-Point DSPs Upgrades to C67x+ CPU From C67x Family: C 2X CPU Registers [64 General-Purpose] C New Audio-Specific Instructions C Compatible With the C67x CPU Enhanced Memory System C 256K-Byte Unified Program/Data RAM C 384K-Byte Unified Program/Data ROM C Single-Cycle Data Access From CPU C Large Program Cache (32K Byte) Supports RAM, ROM, and External Memory External ...

FDMC5614P

Vendor:FAIRCHILDPackage Cooled:QFND/C:07+

The (+)Sense pin allows the regulator to compensate for limited amounts of IR voltage drop in the positive output connection resistance. This is the voltage drop incurred in the PCB trace between Vout (pins 9 & 10) of the regu- lator and the load some distance away. Connecting (+)Sense to the positive load terminal improves the voltage regu- lation at the load, particularly when the load current ...

FDMC5614P

Vendor:FAIRCHILDPackage Cooled:QFND/C:07+

The (+)Sense pin allows the regulator to compensate for limited amounts of IR voltage drop in the positive output connection resistance. This is the voltage drop incurred in the PCB trace between Vout (pins 9 & 10) of the regu- lator and the load some distance away. Connecting (+)Sense to the positive load terminal improves the voltage regu- lation at the load, particularly when the load current ...

FDMC8878

Vendor:FSCPackage Cooled:QFND/C:07+

NOTES 1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. 2See timing diagram below and Serial Interface section of this data sheet. 3Measured with the load circuit in Load Circuit for Timing Specifications and defined as the time required fo...

FDMF6700

Vendor:FAIRCHILDPackage Cooled:QFN40D/C:07+

Referenced to VCCA Voltage VCC Isolation Feature − If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range Ioff Supports Partial-Power-Down Mode Operation I/Os Are 4.6-V Tolerant Max Data R...

FDMF8705

Vendor:FAIRCHILDPackage Cooled:QFN56D/C:07+

135-mΩ -Maximum (5-V Input) High-Side MOSFET Switch 500 mA Continuous Current per Channel Short-Circuit and Thermal Protection With Overcurrent Logic Output Operating Range . . . 2.7-V to 5.5-V Logic-Level Enable Input 2.5-ms Typical Rise Time Undervoltage Lockout 10 µA Maximum Standby Supply Current Bidirectional Switch Available in 8-pin SOIC and PDIP Packages Ambient Temperature Range, C4...

FDMS2572

Vendor:FairchildPackage Cooled:MLP8D/C:02+

S3067 has the ability to bypass the internal VCO with an external source and also with the receive clock. The device generates 14/15, 15/14, 16/17 and 17/16 clocks based upon the received clock and an external clock to incorporate the FEC capability. The dividers support the first two rates shown in Table 4.

FDMS5672

Vendor:FairchildPackage Cooled:MLP8D/C:02+

NOTES: 1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB379. 4. For JC, the ca...

FDMS8660S

Vendor:FAIRCHILDPackage Cooled:QFN8D/C:07+

InputPulldown Non-inver ting differential clock input. InputPullupInver ting differential clock input. OutputDifferential output pair. LVPECL interface levels. OutputDifferential output pair. LVPECL interface levels. OutputDifferential output pair. LVPECL interface levels. OutputDifferential output pair. LVPECL interface levels. to internal input resistors. See Table 2, Pin Characteristics, for typic...

FDMS8660S

Vendor:FAIRCHILDPackage Cooled:QFN8D/C:07+

InputPulldown Non-inver ting differential clock input. InputPullupInver ting differential clock input. OutputDifferential output pair. LVPECL interface levels. OutputDifferential output pair. LVPECL interface levels. OutputDifferential output pair. LVPECL interface levels. OutputDifferential output pair. LVPECL interface levels. to internal input resistors. See Table 2, Pin Characteristics, for typic...

FDMS8670S

Vendor:FAIRCHILDPackage Cooled:QFN8D/C:07+

READY: is the acknowledgment from the addressed memory or I/O device that will complete the data transfer. The RDY signal from memory or I/O is synchronized by the HS-82C85RH Clock Generator to form READY. This signal is active HIGH. The HS-80C86RH READY input is not synchronized. Correct operation is not guaranteed if the Setup and Hold Times are not met.

FDMS8690

Vendor:FairchildPackage Cooled:MLP8D/C:08+

The MSK 5115-00 is an adjustable version in the series of high performance regulators. The diagram below illustrates proper adjustment technique for the output voltage. The series resis- tance of R1+R2 should be selected to pass the minimum regu- lator output current requirement of 10mA.

FDMS8890

Vendor:FAIPackage Cooled:QFN8

< Notice > 1. When power supply of S1T8825B is disconnected, CLK, DATA, EN port from MCU should be pulled low. 2. When power goes up first, R counter data should be entered earlier than N1 and N2 counter data. 3. When power goes up first, control data should be entered earlier than N1 and N2 counter data.

FDMS9600S

Vendor:FairchildPackage Cooled:MLP8D/C:08+

Load strobe input for a 12-bit address/data: A high level on the LD pin latches a 4-bit address (upper 4 bits: D11 to D8) of the internal 12-bit shift register into the internal address decoder, and writes 8-bit data (lower 8 bits: D7 to D0) of the shift register into an internal data latch selected by the latched address.

FDMS9620S

Vendor:FairchildPackage Cooled:MLP8D/C:08+

Number of channels : 8 Resolution : set 10-bit or 8-bit Conversion time : 6.13 µs (with 16-MHz machine clock, including sampling time) Continuous conversion of multiple linked channels possible (up to 8 channels can be set) One-shot conversion mode : converts selected channel only once Continuous conversion mode : converts selected channel continuously Stop conversion mode : converts selected c...

FDMS9820S

Vendor:FAIPackage Cooled:QFN8

FDN103

Vendor:MD/C:05+

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper- ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

FDN103A

Vendor:MOTD/C:05+

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, TA = 25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Measured by the voltage drop between I and Y pin at indicated current through the...